Image Processing Apparatus Having Function of Enlargement and/or Shrinkage of Image

This invention relates to an image processing apparatus having a function of enlarging and/or shrinking a source image with an arbitrary scale factor.

According to a conventional image processing technique, enlarging (or zooming) an image by z times or shrinking it by 1/z times was easily performed, if z is an integer. However, enlargement by n/m times (n and m are integers and n>m>o) or shrinkage by m/n times was difficult and required a long processing period with extremely complex software operations.

Heretofore, NN (Nearest Neighbor) method has been proposed to execute enlargement by n/m times and shrinkage by m/n times. However, it requires a large amount of complex calculations for each bit to be enlarged or shrinked. Therefore, even if the high-level software technique is employed, a long period of time must be spent.

Furthermore, image data is processed word by word in general. However, since the image data must be processed bit by bit in accordance with the NN method, processed bits must be packed word by word. This packing opeation also requires a long period of time.

An object of the present invention is to provide an image processing apparatus which can perform enlarging operation and/or shrinkage operation at a high speed without executive complex calculation.

An image processing apparatus of the present invention comprises means for receiving a plurality of original image data word by word, each data consisting of a fixed number of bits, an enlarging or shrinking circuit having a plurality of gating circuits each getting arbitrary bit or bits of the original image data according to a scale factor, a means for selecting one of the gating circuits in response to a signal representing a desired scale factor to open the selected gate, and means for outputting an image data which consists of bit or bits passing through the selected gating circuit. A mask circuit and a rotator may be used to perform a packing operation to pack the outputted image data into one word, if necessary.

For enlargement, each gating circuit gates those bits which are the same in number as those of the original image data and which contain two or more bits having the same content as one of the bits of the original image data. For shrinkage, the gating circuits gate different numbers of bits less than the number of bits of the original image data.

FIG. 1 shows a block diagram of an image processing apparatus according to an embodiment of the present invention;

FIG. 2(a) shows a diagram illustrating a data flow when a shrinking operation is performed in the embodiment;

FIG. 2(b) shows a diagram illustrating a data flow when an enlargement operation is performed in the embodiment;

FIG. 3(a) shows an output format of a shrinking circuit of the embodiment;

FIG. 3(b) shows an output format of an enlargement circuit of the embodiment;

FIG. 3(c) shows a data format to be entered into an input register of the embodiment;

FIG. 4 shows a table of a number of bits to be rotated (or shifted);

FIG. 5 shows a block diagram of the shrinking circuit of the embodiment; and

FIG. 6 shows a block diagram of the enlargement circuit of the embodiment.

According to the present invention, pixel data of a source image to be enlarged or shrinked are processed word by word without using complex calculation. Referring to FIG. 1, an image processing apparatus according to one embodiment of the present invention has an input register 1, a shrinkage circuit 2, an enlarging circuit 3, a mask circuit 4 having a temporary register, a rotator 5, an output register 6, and a read only memory (ROM 7), all of which are coupled to a common bus 10. The shrinking circuit 2 works to shrink a source image and may be omitted if shrinking operation is not required. The enlarging circuit 3 may be omitted if enlargement is not required. The mask circuit 4, the rotator 5 and the ROM 7 are used to simplify the packing opeation.

In this embodiment, it is assumed that one word consists of 8 bits (8 pixel data). The pixel data of the source image are entered into the input register 11 via a bus 11 word and a processed pixel data are derived from the output register 6 to a bus 12 word by word.

The source image usually consists of a plurality of words and is stored in a source memory (not shown). The source image is read out therefrom word by word. Each word consists of 8 bits of continuous pixel data in horizontal direction of XY co-ordinates and is entered into the input register 1 which has a capacity of 16 bits. When the shrinking operation is to be performed a word to be shrinked is entered into the shrinking circuit 2 and thereafter a shrinked pixel data is sent to the rotator 5 and the mask circuit 4 as shown in FIG. 2(a). While, in the enlargement operation, two consecutive words are entered into the input register 1 and sent therefrom to the rotator 5 and thereafter the rotated word is sent to the enlargement circuit 3 as shown in FIG. 2(b).

Shrinking Operation

In the shrinking operation, arbitrary bit or bits are picked up among 8 bits of pixel data according to a shrinking scale factor Ss (Ss=m/n). The shrinkage circuit 2 is formed of simple selecting circuits which are predetermined to pick up the bit or bits in accordance with the shrinkage factors. If the shrinking scale factor Ss is selected among seven factors 1/8, 2/8, 3/8, 4/8, 5/8, 6/8 and 7/8 and 8 bits pixel data are represented by A B C E D F G H as shown in FIG. 3(c), the bit or bits to be picked up are predetermined as shown in FIG. 3(a).

The pixel data (word) of FIG. 3(c) is sent to the shrinkage circuit 2 via the common bus 10, and the shrinkage circuit 2 has a selecting function to select one of the seven outputs shown in FIG. 3(a) according to the shrinkage scale factor Ss. Referring to FIG. 5, the shrinking circuit 2 has seven gate circuits 20 to 26 and a decoder 27 to select one of the seven gate circuits according to the shrinkage scale factor Ss. Since the shrinkage scale m/n is m/8, m (=1, 2, . . . , 7) as the numerator is used instead of Ss. Each bit of the input register 1 is connected to the gate circuits 20 to 26 as shown in FIG. 5. When m is 1, the decoder 27 outputs a signal for the shrinkage scale factor of 1/8 to activate or enable the gate circuit 20 only. Thus, the pixel data A is picked up. When m is 2, the gate circuit 21 is selectively enabled and the pixel data A and E are picked up. When m is 3, 4, 5, 6, or 7, the gate circuit 22, 23, 24, 25 or 26 is selected, respectively, and the pixel data ADG, ACEG, ACDEFH, ABDEFH and ABCDFGH are picked up. As shown in FIG. 5, the shrinking circuit 2 can be formed as a simple selector.

Since a number of bits of a shrinked pixel data is less than that or one word input data (8 bits of pixcel data), packing operation is required to pack outputs of the shrinking circuit 2 into one word.

The packing operation is executed by use of the rotator 5 and the masking circuit 4. The well-known shift register having a feedback loop to return a shift out bit or bits to its input can be used as the rotator 5. A barrel shifter is suitable as the shift register. A number of bits to be shifted is determined according to the shrinking scale factor as shown in FIG. 4. When the source image is shrinked by m/8 times, m bits are picked up from 8 bits of a first one word as shown in FIG. 3(a). The picked-up m bits are entered into the mask circuit 4 through the rotator 5. At this time the picked-up m bits are not shifted and are entered into 1st to mth bit positions of the mask circuit 4. In this embodiment the mask circuit 4 and the temporary register have 16-bit positions, respectively, for the enlargement operation and 8-bit positions can only used in the shrinking operation. An output of the mask circuit 4 is set at 1st to 8th bit positions of the temporary register.

For example, when the source image is shrinked by 3/8 times, 3 bits among 8 bits of a first word are picked up by the shrinking circuit 2. These 3 bits are not shifted and are entered into 1st to 3rd bit positions of the mask circuit 4. The mask circuit 4 masks the remainder 4th to 8th bit positions. Consequently, the 3 bits picked up from the first word are set into 1st to 3rd bit positions of the temporary register. Thereafter a second word subsequent to the first word is entered into the shrinking circuit 2 and 3 bits thereof are picked up. These subsequently shrinked 3 bits are shifted by 3 bit positions in the rotator 5 and entered into 4th to 6th bit positions of the mask circuit 4. At this time, the mask circuit 4 masks the bit positions (1st to 3rd and 7th to 8th) except for the 4th to 6th bit positions. Thus, the 3 bits picked up from the second word are set into the 4th to 6th bit positions of the temporary register. Then, a third word subsequent to the second word is entered into the shrinking circuit 2 and the picked up 3 bits are sent to the rotator 5 where they are shifted by 6 bit positions as indicated in FIG. 4. First two of the shifted three bits are entered into the 7th and 8th vacant bit positions of the temporary register via the mask circuit 4 which masks the 1st to 6th bit positions. As a result, 8 bit positions are filled up to form one word which corresponds to 3/8--shrinked word and which is sent to the output register 6 and then to a destination memory (not shown) which is coupled to the bus 12. The last bit of the three bits out of the input third word is shifted out from the rotator 5 and is rotated to a first bit position of the rotator 4. The rotated last bit is thereafter entered into the 1st bit position of the mask circuit 4 and is set in the 1st bit position of the temporary register. Successively, a fourth word is applied to the shrinking circuit 2 through the input register 1 and 3 bits are picked up by the shrinking circuit 2. The picked up 3 bits from the fourth word are shifted by one bit in the rotator 5 as shown in FIG. 4 and are written into the 2nd to 4th bit positions of the temporary register through the mask circuit. In such manner, shrinking operation proceeds and the shrinked pixel data of 8 bits is packed word by word. With respect to the other shrinking scale factors (m=1, 4, 5, 6, 7 or 8), m bits are picked up from each word by the shrinking circuit 2, shifted or rotated by the rotator 5 by the respective bits shown in FIG. 4, and written into the temporary register from which the shrinked data is read 8 bits by 8 bits. Data shown in FIG. 4 representing the number of bits to be shifted or rotated are stored in the ROM 7 and are read out thereof according to the scale factor m.

Enlargement Operation

When the source image is to be enlarged by 8/m times (m=1, 2, . . . ,7 or 8), a word entered into the input register 1 is sent to the rotator 5. In the enlargement operation 16 bit (two words) positions of the input register 1 and the rotator 5 one fully employed, while in the shrinking operation only 8 bits of the rotator and the input register are used.

At first, a first word (8 bits) and a second word (8 bits) (for example, A B C D E F G H A'B'C' D'E'F'G'H') are entered into the input register 1 of the 16 bits. The rotator 5 of the 16 bits shifts the 16 bits of the first and second words by number of bits designated in FIG. 4 in accordance with the scale factor. A start bit to be enlarged is located at the most significant bit (MSB) position. For the first enlarged word, no rotation is made as shown in FIG. 4. An output of the rotator 5 is sent to the enlarging circuit 3.

Referring to FIG. 6, the enlarging circuit 3 contains seven 8-bit gate circuits 30 to 36 which are coupled to the respective bit positions of the 8-bit input data lines of the circuit 3 such that the eight outputs from the first 8-bits of the input data shown in FIG. 3(b) may be respectively derived therefrom. A decoder 37 is also provided to receive a scale factor for which the denominator in the enlarging scale factor Se (=n/m=8/m) may be used and to select one of the seven gate circuits according to the inputted scale factor m. The selected one of the seven gate circuits 30 to 36 is enabled by the output of the decoder 37. If the source image is to be enlarged by 8/3 times, for example, the gate circuit 32 is enabled. Therefore, AAABBBCC is derived from the enlarging circuit 3 as a first enlarged output for the original pixel data and directly sent to the output register 6 through which this output is sent to the destination memory (not shown). Then, the same 16-bit input data is shifted in the rotator 5 by m bits (in the above case, 3 bits) such that the (m+1)th (4th) bit locates at a first bit position. Thus, if m is 3, the data D E F G H A'B'C'D'E'F' G'H' (where D E F G H are remaining bits of the pixel data of the first word and A'B'C'D'E'F' G'H' is the pixel data of the second word) is obtained by the rotator 5 and inputted to the enlarging circuit 3, and from the first eight bits D E F G H A'B'C' an output data DDDEEEFF is derived through the selected gate circuit 32 for m=3. This data is directly sent to the output register 6 as a second enlarged data for the first input word A B C D E F G H. Further, the rotator 5 peforms shift operation by 2m bits (6 bits in the above case) and first eight bits G H A'B'C'D'E'F' of the 6-bit shifted input words are subjected to the enlarging operation by the enlarging circuit 3 to obtain a third output data GGGHHHA`A` through the gate circuit 32. After the enlargement of the first word is thus completed, a third word A"B"C"D"E"F"G"H" of 8 bits in the source image is newly entered into the input register 1 instead of the first word. Thereafter the rotator 5 rotates 3m (9) bits and B' C'D'E'F'G'H'A" (B'C'D'E'F'G'H' are the remaining portion of the second word and A" belongs to the third word) obtained by the rotator 5 are inputted to the enlarging circuit 3. As a result an output data B'B'B'C'C'C'D'D' is derived through the gate circuit 32. Thus, whenever enlargement of one word is completed, a new word is entered into the input register. When the other enlargement scale factor (m=1, 2, 4, 5, 6, 7 or 8) is selected. kxm-bit (k=o, 1, 2, 3, . . . ) rotating operation is performed by the rotator and one of the seven gate circuits 30 to 36 is enabled according to the enlargement scale factor m.