Method for Converting the Number of Bits of Input Bit Stream

The present invention relates to image scaling by conversion of the length of an input bit stream, which represents the visual image pattern, to a selected length in response to a given scaling conversion ratio. It has been required to enlarge or reduce a size of input image to a desired image size, for example, letter size (81/2 inches by 11 inches) to metric B4 size, or vice versa.

Some approaches for the conversion of the image size has been proposed. One approach employs periodic deletion or insertion of bits wherein data bits are periodically deleted from or inserted to bit stream which represents one PEL (print element) line of the image. For example, a data bit in the bit stream is deleted every five bit positions in response to a scale conversion or reduction ratio of 4/5.

This approach, however, has an inherent problem that significant bits which might be located at every five bit are lost in the reduced bit stream, resulting in reduced image quality. Another approach uses a so-called bit conversion table. The table is prepared to minimize the loss of the significant bit transition, i.e., 1 to 0 or 0 to 1 transitions of the input image data. In the case of the conversion of B4 size having a width of 256 mm to A4 size having a width of 210 mm, the reduction ratio is represented by the formula; ##EQU1## To realize the ratio 0.8203, a scale conversion or reduction ratio of 5/6 is selected since a 5/6 conversion ratio provides a nearest value, as below: ##EQU2## The input image indicating bit stream for one horizontal scan or print line in the row direction of the B4 size image is divided into 6-bit groups. The conversion table is assembled to include all combinations of 6 bits to 5 bits conversion without the loss of image accuracy. Each 6-bit group is used as the address for accessing the table. This approach, however, has a disadvantage that it requires a relatively large memory space for the table. Japanese published patent application 55-114914 (Sanyo) discloses image scaling or conversion by the use of the above-described table.

The invention relates to methods and apparatus for converting a length or bit density of input bit stream representing a visual image. The image has plural PEL (picture element) scan or print lines forming a rectangular raster pattern. Each PEL line may be serially supplied to the apparatus. The apparatus is supplied with a selected scaling or conversion ratio and to determine the number of data bits to be inserted to or deleted from each scan or print line of the input bit stream. The input bit stream is divided or partitioned into a plurality of bit groups in accordance with the conversion ratio. The number of bit groups is equal to the number of data bits to be inserted or deleted for each said scan or print line. Scaling occurs by one data bit being inserted in or deleted from each of the bit groups. The bits in each bit group are successively determined if the adjacent two bits have the same binary value. A detection circuit is provided which produces a first output signal when the adjacent two bits have the same binary value, and produces a second output signal when the adjacent two bits have different binary value. A circuit responds to the occurrence of the first output signal in the bit group to effect an insertion of a bit adjacent the two identical bits for enlargement or a deletion of a data bit from the adjacent two identical bits for image reduction.

The insertion of one bit into the bit group or the deletion of one bit from the bit group inhibits further bit insertions or deletions in the instant bit group.

If the first output signal is not produced during the successive comparison of two bits in any bit group, that is, all of successive two bit combinations in the bit group indicate bit transitions, i.e., first bit of the two bits having one binary value and second bit having another binary value, one bit is forcibly inserted or one bit is forcibly deleted at the end of such bit group.

The above functions can also be employed in a programmable computer and are effected via program means.

The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.

FIG. 1 is a block diagram of a circuit for scaling an image by changing the number of bits of the input bit stream in accordance with the present invention.

FIG. 2 illustrates the comparison of a reduced image in accordance with the present invention with the reduced image by prior technology.

FIG. 3 illustrates waveforms in various circuit nodes in the block diagram shown in FIG. 1.

FIG. 4 is a circuit diagram of a gate circuit of an output circuit.

FIG. 5 illustrates input and output waveforms of the gate circuit in a reduction mode and an enlarge mode.

Referring to FIG. 1, a serial-in/parallel-out shift register 1 has two stages Q.sub.A and Q.sub.B. It is assumed that input bit stream shown as train A in FIG. 2 is serially applied to shift register 1 over input line 2. Clock signals f clock are applied to shift register 1 over input line 3. Output lines 4 and 5 of shift register 1 are connected to an Exclusive OR/inverter circuit 6; circuit 6 supplies a first or second output signal over line 7 connected to one input of AND circuit 8. The output line 5 of the shift register 1 is connected to one input of an output circuit 9. The f clock signals are also applied to 6 bit rate multipliers 10. The multipliers 10 have control input terminals A through F and produce an output signal on output line 11 as described hereinafter. Output line 11 is connected to the set input terminals of set/reset flip-flop 12 and to one input of AND circuit 13. Output line 12A of flip-flop 12 is connected to another input of each of the AND circuits 8 and 13. Outputs of the AND circuits 8 and 13 go to OR circuit 14. The output of the AND circuit 8 also goes to the reset terminal of the flip-flop 12. The clock input CK of flip-flop 12 is connected to the f clock line 3. The output line 15 of the OR circuit 14 is connected to one input of each of the AND circuits 16 and 17. The AND circuit 16 has another input line 18 and the AND circuit 17 has another input line 19. Output line 20 of the AND circuit 16 and output line 21 of the AND circuit 17 are connected to the output circuit 9.

Referring to FIGS. 1, 2 and 3, the operation of the apparatus shown in the FIG. 1 is now described.

The 6-bit binary rate multipliers 10 determine the number of data bits to be inserted to or delated from 64 bits (one scan or print line) of the input data bit stream train A in response to applied control signals A through F to produce a timing control pulse train on output line 11. The control signals A-F to multipliers 10 are produced by a table 24 which responds to one of various conversion ratios, such as B.sub.4 to A.sub.4, A.sub.3 to A.sub.4, A.sub.3 to B.sub.4, 240 to 203, etc. As apparent from FIG. 3, the timing control pulse train from multipliers 10 partitions the input data bit stream into plural multibit groups, the number of which equals the number of the deleted or inserted bits for each successive scan or print line of a raster of pels. For example, the pattern of the timing control pulse train indicates the number of deleted or inserted bits for each set of 64 bits received over line 2.

For this description, it is assumed that a conversion ratio of 52/64 is specified by the input pattern 001100 applied to terminals F through A, and the input data bit stream is as shown in FIG. 2 is applied to the input line 2. The ratio 52/64 approximates the reduction from B4 size to A4 size as follows: ##EQU3##

Various input patterns specify various conversion ratios as shown in FIG. 1. The ratio 52/64 indicates that twelve bits (the difference between 64 and 52) should be deleted from 64 bits; that is, one bit should be deleted from each group of 16 input bits. It is noted that the timing control pulse train of the multipliers 10 partitions the 16 bits into three groups.

Shift register 1 and the Exclusive OR/inverter circuit 6 determine if the adjacent two bits in each bit group have the same binary value. More particularly, input data bit stream is serially applied to the stages Q.sub.A and Q.sub.B. The stage Q.sub.A stores the current data bit while the stage Q.sub.B stores the immediately preceding data bit.

Both data bits are applied to the Exclusive OR/inverter circuit 6, which produces an up level or first output signal whenever both data bits are equal and produces down level or second output signal whenever the two input data bits have different binary values. In this example, the Exclusive OR/inverter circuit 6 produces the up level signals during periods, T.sub.0 -T.sub.1, T.sub.3 -T.sub.4, T.sub.7 -T.sub.8, etc.

Flip-flop 12 is set by the trailing edge or negative going edge of each timing control pulse on line 11 to produce an up level signal on output line 12A. In the exemplary embodiment, flip-flop 12 is set at the beginning of periods T.sub.4, T.sub.8, T.sub.12 and T.sub.20. The 6-bit binary rate multipliers 10 and the flip-flop 12 respond to the given conversion ratio signified at input terminals A-F to determine the number of data bits to be inserted to or deleted from each 64 bit set the input bit stream in order to partition that 64 bit set into plural bit groups. The set condition of flip-flop 12 allows the succeeding reduction or enlargement operation whenever adjacent data bits are equal. Flip-flop 12 is reset by an up level signal from the AND circuit 8. This AND circuit 8 up level signal is also a gating signal which conditions the reduction or enlarge operation, as will become apparent. As stated above, AND circuit 8 is controlled by the output signals of Exclusive OR/inverter circuit 6 and flip-flop 12. AND circuit 8 is activated whenever both inputs are at the up level. This condition is satisfied at the first occurrence of the up level signal on line 7 after the occurrence of an up level at the output line 11 of flip-flop 12. This activation of AND circuit 8 is shown in periods T.sub.4, T.sub.8 and T.sub.14 in FIG. 3. The up level signal of AND circuit 8 conditions AND circuits 16 and 17 through OR circuit 14 and also resets flip-flop 12 to inhibit further activation of the AND circuit 8 in the bit group being processed. Input lines 18 and 19 of AND circuits 16 and 17, respectively, receive a reduction signal or enlargement signal, respectively. The signal "reduction" is applied over line 18 when the reduction of the original image is desired, while the signal "enlargement" is applied over line 19 when the enlargement of the original image is desired.

In the exemplary reduction case, the reduction signal on line 18 is at up level while the enlarge signal is maintained at down level, whereby AND circuit 16 is activated to condition the output circuit 9 to delete a bit signal during each of the illustrated time periods T.sub.4, T.sub.8, T.sub.14 and T.sub.23 of FIG. 3.

In the case that all of the adjacent two bit combinations in a bit group have different binary values, one bit is forcibly inserted or one bit is forcibly deleted at the occurrence of the next up level signal from the multipliers 10. The example of such a bit group is shown by the bit positions 18 through 23 in the input data bit stream A in FIG. 2, in which all of the adjacent two bit combinations have different binary values. In this instance, Exclusive OR/inverter circuit 6 does not produce any up level signal on output line 7 during the processing of bits in the bit group; AND circuit 8 is therefore not activated resulting in no deletion of a bit as needed for reduction to occur. To forcibly insert or delete one bit in the constant bit group, AND circuit 13 is activated at the beginning of time period 23 by the up level signal of flip-flop 12 and the up level signal on output line 11. It is noted that flip-flop 12 maintains the up level signal on output line 12A since the flip-flop 12 has not been reset by AND circuit 8. The up level signal from the AND circuit 13 is applied to the both AND circuits 16 and 17 through OR circuit 14.

Output circuit 9 includes gate circuit 25 and a serial-parallel converter/shift register 26. The details of the gate circuit 25 are shown in FIG. 4. The gate circuit 25 includes inverter circuits 41 and 42, AND circuits 43 and 44 and OR circuit 45. Circuit 25 selectively gates the f clock signals and the 2f clock signals in response to the delete signal on output line 20 and the delay signal on output line 21, as shown in FIG. 5. In the reduction mode, AND circuit 43 is deactivated whenever the delete signal is on line 20, to inhibit f clock signal during the bit time period. The clock train on output line 23 is the sample signal or shift signal for converter 26, which is a serial-parallel converter/shift register. The data bit of train A during the above-described time period is not received by converter 26, so that the number of bits in the input bit group is reduced by one.

In the enlarge mode, the number of clock pulses on the output line 23 is increased by one for each bit group. When the delay signal on the line 21 is produced, AND circuit 44 gates the 2f clock signal on line 9A, i.e., two clock pulses during this bit period. Except during the bit period during which the delay signal is produced, AND circuit 43 gates the f clock pulses to OR circuit 45. Both clock pulse trains from AND circuits 43 and 44 are ORed by circuit 45 and shown in FIG. 5, whereby the number of clock pulses is increased by one during this bit period so that one data bit during this bit period is sampled twice; the number of the data bits in the bit group is increased by unity.

The logic processing circuit including the AND circuits 8, 13, 16 and 17, the OR circuit 14 and the output circuit 9, respond to the output signals of the Exclusive OR/inverter circuit 6 and the flip-flop 12 to insert one additional bit to the adjacent two identical bits or delete one bit from the adjacent two identical bits or forces a change at the end of a bit group if no two adjacent bits were identical.

FIG. 2 shows the comparison of the reduced output bit pattern C of the present invention with the output bit stream B reduced by the prior art periodical bit deletion. The reduction of the B4 size image to the A4 size image is shown. The bit stream B is obtained by periodically deleting the input bit every 6 bits in accordance with the 5/6 reduction ratio. It is apparent that the bit transitions "1 to 0" between the position 4 and 5, bit transition "0 to 1" between the positions 10 and 11, bit transition "1 to 0" between the positions 11 and 12, bit transition "0 to 1" between the positions 16 and 17, bit transition "1 to 0" between the the positions 17 and 18 are not included in the output bit stream B of the prior technique.

In the output bit stream C reduced by the present invention, all informationally or image significant bit transitions, which are lost in the bit stream B, are maintained, whereby the image quality is substantially improved in comparison with the bit stream B. It is particularly desirable to maintain these original significant or image bit transitions in the output bit stream, since the output bit stream would be processed by a utility apparatus, such as a data processing host apparatus. The resultant raster, accumulation of a plurality of scan or print lines into an array, are used by a visual presentation device, such as a video display terminal, dot matrix printer and the like.

The above description relates to the enlargement or reduction of the image in the row or scan direction.

The enlargement or reduction of the image in the column or transverse to the raster scan direction could be performed by storing the image, the row direction of which has been processed by the circuit of FIG. 1, to a memory by applying data bits in the column direction of the stored image to the input line 2 of the shift register 1 as the input data stream and by processing all columns of the stored image in the same manner as described.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.