Image Sensor Having Charge Storage Regions

The present invention generally relates to an image sensor, and in particular to an image sensor such as a charge-coupled device image sensor having charge storage regions. More particularly, the present invention relates to an image sensor capable of detecting a greatest charge amount and a smallest charge amount in real time by separately monitoring potentials of floating electrodes formed above respective charge storage regions. The present invention is suitably applied to a camera and so on.

As is well known, a solid image sensor such as a charge-coupled device (hereinafter simply referred to as a CCD image sensor) is widely used in various fields of a facsimile machine, a camera and so on. A conventional CCD image sensor has a function of only transferring stored charges which are generated by irradiation of light and which are then stored in charge storage regions. Such a CCD image sensor can be used in ah application in which the intensity of light to be processed is limited within a certain range, such as a facsimile machine. However, the CCD image sensor having only the charge transfer function, is not suitable for an application in which a dynamic range of light in intensity to be processed is great, such as a camera. For example, the amount of light applied to a photodiode built in the CCD image sensor may become excessive due to strong illuminance of an object. In this case, a charge storage region overflows with a stored charge. On the other hand, when the amount of light received by a photodiode is insufficient, the sensitivity of the image sensor is decreased, and thereby the image sensor do not sufficiently functions as an image sensor.

In order to overcome the above problems, the applicant has proposed an improved CCD image sensor in the Japanese Laid-Open Patent Application No. 61-226953. The proposed image sensor has an automatic gain control function, in which a time during which a charge is stored in a charge storage region, is determined by sensing an optical state of a CCD image sensor in real time. The optical state of the CCD image sensor is obtained by detecting an average in amounts of the charges which are generated by the respective photodiodes, and are then stored in the respective charge storage regions of the CCD image sensor. The storage electrodes (floating electrodes) formed above charge storage regions are mutually connected. A potential of the mutually connected floating electrodes is monitored. The potential changes, depending on the amount of light received by the CCD image sensor. The measured potential corresponds to the average amount of the charges stored in the charge storage regions. When the potential of the mutually connected floating electrodes exceeds a reference potential, the CCD image sensor is considered being about to overflow. Therefore at this time, a charge transfer operation is activated.

However, the proposed image sensor has disadvantages described below. The optical state of the CCD image sensor is monitored by obtaining the average amount of charges stored in charge storage regions. Therefore, the average amount of charges may be smaller than the reference level, through a charge storage region overflows with excessive charges. Further, the average amount may be kept almost constant, through the greatest charge amount and/or the smallest charge amount changes every moment. In other words, the average of the amounts of charges does not completely correspond to a change in intensity of light.

Accordingly, a general object of the present invention is to provide an image sensor in which the above disadvantages are eliminated.

A more specific object of the present invention is to provide an image sensor capable of monitoring an optical state of the image sensor by detecting a greatest storage charge amount and/or a smallest storage charge amount in real time.

The above objects of the present invention are achieved by an image sensor comprising elements described below. A plurality of charge storage regions store charges from respective photodiodes. The plurality of charge storage regions include respective floating electrodes, which varying in potential in accordance with amounts of charges stored in the respective charge storage regions. Charge transfer regions transfer the charges from the plurality of charge storage regions in response to a predetermined transfer clock. A plurality of potential monitoring transistors are connected to the respective floating electrodes for separately monitoring changes in potential of the respective floating electrodes. An output circuit produces an output signal which varies in accordance with one of the monitored potentials which is one of the highest potential and the lowest potential.

Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings.

FIG. 1 is a view showing a preferred embodiment of the present invention;

FIG. 2 is a view for showing an elevational cross section taken along a line II--II of FIG. 1 and for flow of a charge generated in a photodiode included in the embodiment;

FIG. 3 is a graph showing a relationship of a floating electrode potential vs. a storage charge amount;

FIGS. 4(A) through 4(D) show waveforms for explaining operations of embodiments of the present invention;

FIG. 5 is a view showing another preferred embodiment of the present invention;

FIG. 6 is a view showing yet another preferred embodiment of the present invention;

FIG. 7 is a circuit diagram of a control circuit 50 shown in FIG. 6; and

FIG. 8 is a circuit diagram of a modification of the circuit shown in FIG. 7.

A description is given of a preferred embodiment with reference to FIGS. 1 through FIG. 4. The embodiment is designed so as to detect a largest storage charge amount in a charge storage region which has a plurality of potential wells provided for respective photodiodes.

A CCD image sensor 1 includes a photo sensitive portion 5, a charge storage portion 7 and a transfer portion 9. These portions are formed on a single silicon substrate. The photo sensitive portion 5 includes n number of photodiodes. For the sake of simplicity, only four photodiodes 5.sub.1 -5.sub.4 are shown. This holds true for other structural elements of the CCD image sensor 1. As shown in FIG. 2, each of the photodiodes 5.sub.1 -5.sub.4 includes an n.sup.+ -type diffusion layer 11 formed in a p-type silicon substrate 10. A silicon oxide film 12, which is optically transparent, is formed on the entire surface of the silicon substrate 10. Light which enters in each of the photodiodes 5 generates a charge, or a pair of an electron and a hole due to light excitation energy of the light. The generated charges pass through a substrate portion under a bias gate electrode 6, to which a bias gate source voltage V.sub.BG is applied, and are then transferred to the charge storage portion 7.

The charge storage portion 7 has a plurality of charge storage regions, each of which has a metal-oxide-semiconductor (MOS) structure. That is, the charge storage regions comprise respective charge storage gates 7.sub.1 -7.sub.4, which are formed on the silicon oxide film 12 which is deposited on the silicon substrate 10. The MOS structure forms a capacitor, which stores a charge transferred from the related photodiode. The charge storage gates 7.sub.1 -7.sub.4 are separately kept in a floating state. The charge storage gates 7.sub.1 -7.sub.4 are hereinafter referred to as floating electrodes. It is noted that the floating electrodes described in the aforementioned Application are mutually connected in order to obtain the average of the amounts of stored charges.

The floating electrodes 7.sub.1 -7.sub.4 are provided with respective n-channel MOS transistors T11-T14 (hereinafter referred to as NMOS transistors). Sources of the NMOS transistors T11-T14 are connected to the floating electrodes 7.sub.1 -7.sub.4, respectively. Drains of the NMOS transistors T11-T14 are supplied with a positive constant source voltage V.sub.A, and gates thereof are supplied with a preset clock pulse signal P. When the preset clock pulse signal P is switched to a high level, the NMOS transistors T11-T14 are turned ON. Thereby, the positive source voltage V.sub.A is applied to the floating electrodes 7.sub.1 -7.sub.4, so that the floating electrodes 7.sub.1 -7.sub.4 are preset. The power source voltage V.sub.A is set equal to +5 volts, for example. The application of the power source voltage V.sub.A forms a potential well PW in a bulk portion of the silicon substrate 10 under each of the floating electrodes 7.sub.1 -7.sub.4, as shown in FIG. 2. The potential well PW obtained when there is no charge therein, is shown by a solid line B1 in FIG. 2. The charges generated at the photodiodes are stored in the respective potential wells PW. The potential of each of the floating electrodes 7 is altered, depending on the amount of the stored charge in the corresponding potential well PW. In general, a gate electrode of an n-channel MOS capacitor which is kept in the floating state, decreases in potential, as the stored charge becomes larger in amount, as shown in FIG. 3. Therefore, the floating electrodes 7.sub.1 -7.sub.4 follow the above. That is, the floating electrodes 7.sub.1 -7.sub.4 have an initial potential of 5 volts in the case where there is no storage charge in the respective potential wells PW. Then, the floating electrodes 7.sub.1 -7.sub.4 have respective decreased potentials in response to increased amounts of the respective stored charges. In other words, the potentials of the floating electrodes 7.sub.1 -7.sub.4 decrease toward zero volt, depending on increased amounts of the respective stored charges. A decreased potential is shown by a broken line B2 in FIG. 2.

The transfer portion 9 includes transfer electrodes 9.sub.1 to 9.sub.4. First and second transfer clock signals .phi..sub.1 and .phi..sub.2 are supplied to the transfer electrodes 9.sub.1 to 9.sub.4. The first and second transfer clock signal .phi..sub.1 and .phi..sub.2 have the same duty ratio and are 180.degree. out of phase. The charges stored in the respective potential wells PW are transferred to n-type regions 13 under the respective transfer electrodes 9.sub.1 -9.sub.4 in response to the application of a transfer gate clock signal C.sub.TG to a transfer gate 8. In FIG. 2, the solid potential curve is with respect to a case where no transfer gate clock signal C.sub.TG is applied to the transfer gate 8, and the broken potential curve is with respect to a case where the transfer gate clock signal C.sub.TG is applied to the transfer gate 8. Then, the charged are transferred in synchronism with the first and second transfer clock signals .phi..sub.1 and .phi..sub.2, and are sequentially read out through an output terminal OUT.

P-channel MOS transistors (hereinafter simply referred to as PMOS transistors) T21-T24 are provided for the floating electrodes 7.sub.1 -7.sub.4, respectively. Gates of the PMOS transistors T21-T24 are connected to the floating electrodes 7.sub.1 -7.sub.4, respectively. Drains of the PMOS transistors T21-T24 are connected to ground. It is noted that a resistance across a channel of each PMOS transistor T21-T24 changes, depending on the gate potential thereof, or the potential of the corresponding floating electrode 7.sub.1 -7.sub.4. Therefore, the PMOS transistors T21-T24 function as variable resistors. For example, the channel resistance of the PMOS transistor T21 varies depending on the potential of the floating electrode 7.sub.1. That is, the potential of the floating electrode 7.sub.1 varies depending on the amount of the charge stored in the potential well PW formed under the floating electrode 7.sub.1. Sources of the PMOS transistors T21-T24 are connected in common to a signal line L1.

One end of a resistor R21 is connected to the signal line L1. The other end of the resistor R21 is connected to a source of an NMOS transistor T25, a drain of which is connected to a positive source voltage V.sub.C. The positive source voltage is set equal to 5 volts, for example. A gate of the NMOS transistor T25 is supplied with a bias voltage V.sub.B1, and the NMOS transistor T25 is turned On. Thereby the other end of the resistor R21 may be connected directly to the V.sub.C line, and the the signal line L1 is reset at the potential of the voltage V.sub.C.

It is preferable that the resistor R21 has a resistance which is sufficiently large than the channel resistances of the PMOS transistors T21-T24. Thereby, the potential at the signal line L1 can be determined, depending on the smallest channel resistance out of the channel resistances of the PMOS transistors T21-T24. In other words, the potential at the signal line L1 is not affected by the PMOS transistors other than the PMOS transistor having the smallest channel resistance. It is noted that the photodiode associated with the PMOS transistor having the smallest channel resistance, receives the largest amount of light. Therefore, the potential of the signal line L1 indicates the largest amount of light. The resistance of the resistor R21 is actually selected so that when the PMOS transistors T21-T24 are in the reset state, the potential of the signal line L1 is approximately equal to the voltage determined by a resistor ratio of R21 to the PMOS transistor T21-T24.

The signal line L1 is connected to a gate of an NMOS transistor T26, a drain of which is supplied with the source voltage V.sub.A. A source of the NMOS transistor T26 is connected to a drain of an NMOS transistor T27, a source of which is connected to the ground. A reference voltage V.sub.REF1 is supplied to a gate of the NMOS transistor T27. The NMOS transistors T26 and T27 function as respective resistors. Channel resistance of the NMOS transistor T26 varies, depending on the potential of the signal line L1. On the other hand, channel resistance of the NMOS transistor T27 is kept constant due to the reference voltage V.sub.REF1 applied to the gate thereof. Therefore, an output signal extracted at a node between the NMOS transistors T26 and T27, is a voltage signal obtained by dividing the constant voltage V.sub.A by the channel resistances of the NMOS transistors T26 and T27. A ratio of voltage division is determined depending on the gate potential of the NMOS transistor T26, or in other words, the potential of the signal line L1.

A description is given of an operation of the embodiment with respect to FIG. 4 in addition to FIGS. 1 through 3. FIG. 4(A) shows a waveform of the preset clock pulse signal P, FIG. 4(B) shows potentials of the floating electrodes 7.sub.1 -7.sub.4, and FIG. 4(C) shows the output voltage signal Vo(max) indicating the largest amount of charge, which corresponds to the potential level of the signal line L1.

At the time of initialization, the charges generated in the photodiodes 7.sub.1 -7.sub.4 are sent to the charge storage portion 7 in response to the application of the bias gate source voltage V.sub.BG. Then the charges stored in the charge storage portion 7 are transferred to the transfer portion 9 by the application of the transfer gate clock signal C.sub.TG. Then, the charges are shifted in synchronism with the transfer clock signals .phi..sub.1 and .phi..sub.2, and are sequentially output. On the other hand, the signal line L1 is reset at the bias potential V.sub.C by the application of the bias voltage V.sub.B1. Further, the preset clock signal P is applied to the gates of the NMOS transistors, and thereby the floating electrodes 7.sub.1 -7.sub.4 are preset at the potential V.sub.A. Thereby, the entire image sensor 1 is initialized.

When light is irradiated on the light sensitive portion 5, the photodiodes 5.sub.1 -5.sub.4 generate charges, amounts of which correspond to energy amounts of light received by the respective photodiodes 5.sub.1 -5.sub.4. The generated charges are transferred to the potential wells PWs formed under the corresponding floating electrodes 7.sub.1 -7.sub.4. The charges depending on the respective energy amounts of the light are stored in the corresponding potential wells PWs. Now assuming that the largest amount of charges is stored in the potential well formed under the floating electrode 7.sub.1, the floating electrode 7.sub.1 becomes lower in potential than the other floating electrodes 7.sub.2 -7.sub.4. In other words, the potential of the floating electrode 7.sub.1 becomes closest to zero potential. Therefore, the channel resistance of the PMOS T21 is decreased the most, and thereby most of current passes through the PMOS T21 from the power source V.sub.C. Therefore, the PMOS T21 decreases the potential of the signal line L1. That is, the potential of the signal line L1 is determined depending on the channel resistance of the PMOS transistor T21. It can be seen from FIG. 4(B) and 4(C) that the potential of the signal line L1 is decreased so as to follow a decrease of the floating electrode 7.sub.1 which is the largest.

It is assumed that as shown in FIG. 4(B), at a time t.sub.2, the potential of the floating electrode 7.sub.2 becomes equal to the potentials of the floating electrodes 7.sub.1 and 7.sub.3, and then becomes lower than the potentials of the floating electrodes 7.sub.1, 7.sub.3 and 7.sub.4. Therefore, the PMOS transistor T22 has the smallest channel resistance, and thereby the potential of the signal line L1 is determined depending on the channel resistance of the PMOS transistor T22. As a result, after the time t.sub.2, the potential of the signal line L1 is decreased so as to follow a decrease in potential of the floating electrode 7.sub.2. Hereinafter, at a time t.sub.4, the potential of the floating electrode 7.sub.3 becomes equal to the potential of the floating electrode 7.sub.2, and then becomes lower than the potentials of the floating electrode 7.sub.1, 7.sub.2 and 7.sub.4. Therefore, the potential of the signal line L1 is determined in accordance with the channel resistance of the corresponding PMOS T23 which is the smallest. Therefore, the potential of the signal line L1 is decreased so as to follow a decrease in potential of the floating electrode 7.sub.3.

As can be seen from the above description, the potential change of the signal line exhibits the largest storage charge amount in real time. The potential of the signal line L1 is applied to the gate of the NMOS transistor T26. The combination of the NMOS transistors T26 and T27 divides the constant power source voltage V.sub.A in accordance with the potential of the signal line L1. Then the output voltage signal Vo(max), or the largest amount of the stored charge is output at the node of the NMOS transistors T26 and T27. The output voltage signal Vo(max) indicates the largest amount of the stored charge in real time. The output voltage signal Vo(max) may be used for controlling timing for applying the transfer gate clock signal C.sub.TG to the transfer gate electrode 8. For example, when the output voltage signal Vo(max) becomes lower than a predetermined threshold voltage V.sub.1 shown in FIG. 4(C), a certain potential well PW is considered being about to overflow with electrons. Therefore, at this time, the transfer gate clock signal C.sub.TG is applied to the transfer gate electrode 8. When the bias voltage V.sub.B1 is no longer applied to the gate of the NMOS transistor T25, the NMOS transistor T25 is turned OFF, and thereby the operation for detection of the largest amount of stored charge is stopped.

In the embodiment of FIG. 1, either one of the resistor R21 and the NMOS transistor T25 may be used. Where only the NMOS transistor T25 is used, the bias voltage V.sub.B1 is set equal to 1 volt, for example. A p-channel MOS transistor may be used in place of the NMOS T25. Where only the PMOS is used in place of the resistor R21 and T25, the bias voltage V.sub.B is set at 4 volts, for example.

A description is given of another embodiment of the present invention with reference to FIG. 5. In FIG. 5, the same elements as those in FIG. 1 are indicated by the identical reference numerals. The embodiment of FIG. 5 is designed so as to detect a smallest amount of stored charge.

Referring to FIG. 5, n-channel MOS transistors T31-T34 are provided for the respective floating electrodes 7-7.sub.4. Gates of the NMOS transistors T31-T34 are connected to the floating electrodes 7.sub.1 -7.sub.4, respectively. The positive power source voltage V.sub.A (5 volts, for example) are supplied in common to drains of the NMOS transistors T31-T34. Sources of the NMOS transistors T31-T34 are mutually connected to a signal line L12. Each of the NMOS transistors T31-T34 functions as a variable resistor. That is, the channel resistances of the NMOS transistors T31-T34 are varied in accordance with the respective gate potentials. It is noted that the channel resistances of the NMOS transistors T31-T34 increase as the respective potentials decrease.

An end of a resistor R31 is connected to the signal line L2. The other end of the resistor R31 is connected to a drain of an NMOS transistor T35, a source of which is connected to the ground. A gate of the NMOS transistor T35 is supplied with a bias voltage signal V.sub.B2, which may be identical to or different from the bias voltage signal V.sub.B1 in the first embodiment of FIG. 1. When the bias voltage signal V.sub.B2 is applied to the gate of the NMOS transistor T35, it is turned ON, and thereby the resistor R31 becomes connected to the ground. A resistance of the resistor R31 is selected so as to be sufficiently larger than channel resistances of the NMOS transistors T31-T34. Thereby, the potential of the signal line L2 can be determined, depending on the smallest channel resistance out of four channel resistances of the NMOS transistors T31-T34.

The signal line L2 is connected to a gate of an NMOS transistor T36. The power source voltage V.sub.A is supplied to a drain of the NMOS transistor T36, a source of which is connected to a drain of an NMOS transistor T37. A source of the NMOS transistor T37 is connected to the ground. A gate of the NMOS transistor T37 is kept at a reference voltage signal V.sub.REF2. The NMOS transistors T36 and T37 function as respective resistors which are connected in series. The constant voltage V.sub.A is divided depending on the potential of the signal line L2. A ratio of voltage division depends on the potential of the signal line L2. A divided output voltage signal Vo(min) is outputted at a node between the NMOS transistors T36 and T37. The output voltage signal Vo(min) exhibits the smallest storage charge amount in real time.

A description is given of an operation of the embodiment of FIG. 5 with reference to FIGS. 4(A), 4(B) and 4(D) in addition to FIG. 5.

At the commencement of the operation, initialization is carried out as in the case of the first embodiment of FIG. 1. By the initialization, the potentials of the floating electrodes 7.sub.1 -7.sub.4 are set at the initial potential V.sub.A (5 volts, for example). The potential of the signal line L2 is set nearly equal to the voltage determined by a resistance ratio of R31 to the NMOS transistors T31-T34.

The channel resistances of the NMOS transistors T31-T34 vary in accordance with the respective gate potentials which depend on charge amounts stored in the respective potential wells PWs. The floating electrode having the smallest amount of the stored charge, has the highest potential, or in other words, is closest to the source voltage V.sub.A. If the floating electrode 7.sub.1 has the highest potential, the corresponding NMOS transistor T31 has the smallest channel resistance at this time. Therefore, most of current from the power source V.sub.A passes through the NMOS T31, and thereby the potential of the signal line L2 is determined in accordance with the smallest resistance thereof. For example, if the floating electrode 7.sub.1 is still kept at the initial potential, no increase in the channel resistance of the NMOS transistor T31 occur. Therefore, the potential of the signal line is kept.

In the case of FIG. 4, after the initialization, the potential of the floating electrode 7.sub.2 is the highest. That is, the photodiode 5.sub.2 receives the smallest energy amount of light. During this time, the potential of the signal line L2 is determined in accordance with the channel resistance of the NMOS transistor T32 which depends on the potential of the floating electrode 7.sub.2. At a time t.sub.1, the potential of the floating electrode 7.sub.2 becomes equal to that of the floating electrode 7.sub.4, and then the potential of the floating electrode 7.sub.4 becomes the highest. Therefore, the channel resistance of the corresponding NMOS transistor T34 becomes the smallest, and thereby the potential of the signal line L2 is determined in accordance with the smallest channel resistance of the NMOS transistor T34. Then at a time t.sub.3, the potential of the floating gate 7.sub.1 becomes equal to that of the floating gate 7.sub.4, and then becomes higher than potentials of the other floating gates 7.sub.2 -7.sub.4. Therefore the potential of the signal line L2 is decided in accordance with the channel resistance of the NMOS transistor T31.

Responsive to the potential of the signal line L2, the constant power source voltage V.sub.A is divided, and the output voltage signal Vo(min) is output. The output voltage signal Vo(min) exhibits the smallest amount of the stored charge in real time. The output voltage signal Vo(min) may be used for controlling a time at which the transfer gate clock signal C.sub.TG is stopped. For example, when the output voltage signal Vo(min) becomes smaller than a predetermined threshold potential V.sub.2 of FIG. 4(D), which corresponds to a charge amount below which the detection of light cannot be carried out correctly.

In the embodiment of FIG. 5, either one of the resistor R31 and the NMOS transistor T35 may be used. A PMOS transistor may be used instead.

A description is given of yet another embodiment of the present invention with reference to FIG. 6. The embodiment of FIG. 6 corresponds to a combination of the structures of FIGS. 1 and 5. In FIG. 6, those parts which are the similar to those parts in FIGS. 1 and 5 are given the same designations and a description thereof will be omitted. Referring to FIG. 6, the gates of the PMOS transistors T21-T24 and the NMOS transistors T31-T34 are connected to the respective floating electrodes 7.sub.1 -7.sub.4. The output voltage signals Vo(max) and Vo(min) are supplied to a control circuit 50. The control circuit 50 generates the transfer gate clock signal C.sub.TG on the basis of the output voltage signals Vo(max) and Vo(min). When the output voltage signal Vo(max) becomes equal to or lower than the threshold level V.sub.1, the control circuit 50 generates the transfer gate clock signal C.sub.TG. Thereby, the charges stored in the potential wells PWs formed under the floating electrodes 7.sub.1 -7.sub.4 are transferred to the transfer portions 9.sub.1 -9.sub.4. This enables all the charges to be transferred, when a potential well PW is about to overflow with electrons. Similarly, when the output voltage signal Vo(min) becomes equal to or lower than the threshold voltage V.sub.2, the control circuit 50 generates the transfer gate clock signal C.sub.TG. This enables all the charges to be transferred when a minimum mount of charges necessary for exposure is obtained. That is, very weak light can be detected.

FIG. 7 shows a circuit of the control circuit 50 shown in FIG. 6. As shown, the control circuit 50 comprises a comparator 5.sub.1 and a C.sub.TG generator 5.sub.2. The comparator 5.sub.1 performs a discrimination operation between the output voltage signal Vo(max) and the threshold voltage V.sub.1. The C.sub.TG generator 5.sub.2 is triggered in response to an output signal of the comparator 5.sub.1, and then generates the transfer gate clock signal C.sub.TG. The generated transfer gate clock signal C.sub.TG is supplied to the transfer gate 8. The control circuit 50 may be built in the CCD image sensor 1, and may be provided as a peripheral circuit thereof.

FIG. 8 is a modification of the embodiment of FIG. 6. The portions 5, 7 and 9, the gates 6 and 8, and the control circuit 50 shown in FIG. 6 is omitted in FIG. 8 for the sake of simplicity. The feature of the modification is the presence of level shift circuits LS1-LS4, each provided for the respective floating electrodes 7.sub.1 -7.sub.4. It is desirable to operate the NMOS transistors T31-T34 within an operable voltage range as high as possible, because the NMOS transistors T31-T34 are of an n-channel type. On the other hand, it is desirable to operate the PMOS transistors T21-T24 within an operable voltage range as low as possible. The level shift circuit LS1 shifts the potential at the gate of the NMOS transistor T31 by a predetermined level. Similarly, the level shift circuits LS2-LS4 shift the potentials of the gates of the NMOS transistors T32-T34 by the predetermined level. The level shift circuit LS1 comprises NMOS transistors T41 and T42. A gate of the NMOS transistor T41 is connected to the gate of the NMOS transistor T31 A drain of the NMOS transistor T41 is provided with the power source voltage V.sub.A. A source of the NMOS transistor T41 is connected to a drain of the NMOS transistor T42, a source of which is connected to the ground. A gate of the NMOS transistor T42 is provided with a bias signal V.sub.BS. A level to be shifted can be adjusted by the level of the The bias signal V.sub.BS. n control a level shift amount of the level shift circuit LS1. Similarly, the level shift circuits LS2, LS3 and LS4 include NMOS transistors T43 and T44, T45 and T46, and T47 and T48. The signal line L2 is biased by an NMOS transistor T49, and the signal line L1 is biased by an NMOS transistor T50. It is noted that resistors such as the aforementioned resistors R21 and R31 are not employed in the modification of FIG. 8, because those resistors are necessarily elements for biasing the signal lines L1 and L2. In place of the NMOS transistors T49 and T50, only resistors such as the resistors R21 and R31 may be used for biasing the signal lines L1 and L2.

The present invention is not limited to the embodiments and the modification, and variations and modifications may be made without departing from the scope of the present invention.