Method and Apparatus for Controlling Storage Time in Charge Storing Photoelectric Converter

The present invention relates to a method and apparatus for controlling the storage time of a charge storing photoelectric converter.

A charge storing photoelectric converter composed of a plurality of light-detecting elements is well known in the art. The storage time of such a converter is controlled by one of the following methods:

(1) After the elapse of a selected storage time, the stored video signal is read out. Checking is then carried out to determine whether the signal level of the read-out video signal is appropriate for handling by the processing circuit. If the signal level is not appropriate, the storage time is set to another value and the above procedure is repeated until a video signal of the proper level is obtained. (This method is disclosed in Unexamined Published Japanese Patent Application No. 110209/80.)

(2) A single monitor light-detecting element is positioned adjacent to the plurality of light-detecting elements and the storage of video signals in the latter is completed when a predetermined amount of light is received by the monitor light-detecting element (See Unexamined Published Japanese Patent Application No. 64711/82).

(3) Each of the light-detecting elements is provided with a terminal for detecting the amount of light received and the storage of video signals is completed when any one of the terminals has received a predetermined amount of light.

The first method involves several storage operations before a video signal having the desired level is obtained, so that a prolonged period of time is necessary before the subsequent step of signal processing becomes possible. In the second method, the amount of charge stored in more than one light-detecting element is determined on the basis of the amount of light received by a single monitor element, and therefore, the peak value of the output video signal has undesirably great variations. The third method which makes use of the charges stored in one of the light-detecting elements responsible for actual photoelectric conversion outputs only a low quality signal.

Therefore, the primary object of the present invention is to provide a method and apparatus capable of determining the right storage time of a charge storing photoelectric converter without experiencing the defects of the conventional techniques.

In the method of the present invention, a plurality of monitor light-detecting elements are positioned adjacent to a group of light-detecting elements in a charge storing photoelectric converter, and the storage of charges in the group of light-detecting elements is completed when any one of the monitor light-detecting elements has received a predetermined amount of light.

The apparatus of the present invention includes a plurality of monitor light-detecting elements positioned adjacent to a group of light-detecting elements in a charge storing photoelectric converter, switch elements for applying a constant voltage to the respective monitor light-detecting elements when no charge is being stored in the group of light-detecting elements, comparators for comparing the terminal voltages of the respective monitor light-detecting elements with a reference voltage lower than the constant voltage while charges are stored in the group of light-detecting elements, and an OR gate producing the logical sum of the outputs of the comparators.

FIG. 1 is a block diagram showing a preferred embodiment of a storage time control apparatus of the present invention;

FIG. 2 is a circuit diagram showing an illustrative stored light detector;

FIG. 3 is a circuit diagram showing the configuration of the comparator shown in FIG. 2;

FIG. 4 is a schematic diagram illustrating the arrangement of monitor light-detecting elements with respect to a group of light-detecting elements;

FIG. 5 is a timing chart illustrating the operation of the apparatus shown in FIG. 1;

FIG. 6 is a graph showing the relation between the peak level of the video signal and the selectively illuminated light-detecting element;

FIG. 7 is a circuit diagram showing another illustrative stored light detector;

FIG. 8 is a timing chart used for explaining the operation of the circuit shown in FIG. 7;

FIG. 9 is a circuit diagram showing a third illustrative stored light detector; and

FIG. 10 is a timing chart describing the operation of the circuit shown in FIG. 9.

Several embodiments of the present invention will hereinunder be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a first embodiment of a storage time control apparatus according to the present invention. A group of light-detecting elements 2 included in a charge storing photoelectric converter such as a CCD sensor are charged when the logic level of a storage command signal S.sub.A produced by a storage control/signal processing circuit 3 is low and are cleared when the signal S.sub.A is high. When the logic level of a read signal S.sub.B produced by the circuit 3 changes from the low to the high level, a reading circuit 4 reads into the circuit 3 a series of video signal S.sub.C segments representing the charges stored in the group of light-detecting elements 2 and which together compose the video signal S.sub.C.

The apparatus shown in FIG. 1 also includes a stored light detector 1 composed of stored light detector circuits 1.sub.1, 1.sub.2, . . . 1.sub.n, a signal generator 10, and a NAND gate 11. As shown in FIG. 2, each of the stored light detector circuits, for instance, the detector 1.sub.i (i=1, 2, 3 . . . n), includes a switch element SW.sub.i-1 which is turned on and off depending upon the logic level of a storage command signal S.sub.A from circuit 3, a monitor light-detecting element M.sub.i which receives through the switch element SW.sub.i-1 a reference signal S.sub.D from the signal generator 10, and a comparator CO.sub.i composed of an operational amplifier which receives on its noninverting input terminal the reference signal S.sub.D through switch element SW.sub.i-1 and on its inverting input terminal a comparison signal S.sub.E from the signal generator 10.

As shown in FIG. 3, the comparator CO.sub.i includes a differential input stage made of FET devices T1 and T2, FET devices T3 and T4 providing active loads for the differential input stage, a constant current source composed of an FET device T5 and resistor R, FET devices T5 and T6 each functioning as a constant current source providing a current mirror for the constant current source formed by the device T5 and the resistor R, and an FET device T8 which has constant current supplying FET device T7 connected thereto as an active load and receives the output of the differential input stage as an input. Each of the elements T1, T2, T5, T6 and T7 is a p-channel MOS-FET, whereas the elements T3, T4 and T8 are each an n-channel MOS-FET.

In the comparator CO.sub.i, the voltage of a signal supplied to the gate of T1 (the noninverting input terminal of the differential input stage) is transferred to the gate of T8 in negative phase and to the output terminal of T8 in positive phase.

The monitor light-detecting element M.sub.i (i-1, 2, . . . n), whose equivalent circuit is shown in FIG. 2, is positioned adjacent to the group of light-detecting elements 2 as illustrated in FIG. 4. In FIG. 4, four light-detecting elements 2a are monitored by one unit M.sub.i. However, it should be understood that any number of light-detecting elements 2a can be monitored by a single monitor element.

The operation of the storage time control apparatus according to the first embodiment will now be described with reference to FIG. 5. When the logic level of the signal S.sub.A from the storage control/signal processing circuit 3 changes from high to low at t.sub.0 as by waveform (1), the light-detecting elements 2 start to store charges as indicated by waveform (2), and at the same time, the switch SW.sub.i-1 (FIG. 2) in each of the stored light detector circuits 1.sub.1, 1.sub.2, . . . 1.sub.n is opened. Then, the monitor light-detecting element M.sub.i also starts to store charge as a result of which the terminal voltage V+ of the element M.sub.i decreases in proportion to time, as shown by waveform (3). The symbol V+ indicates the change in the voltage at the terminal of the monitor light-detecting element M.sub.i that has received the maximum amount of light, whereas V.sub.1 + shows the change in the voltage at the terminal of any one of the other monitor light-detecting elements. The symbols V.sub.REF and V.sub.AGC respectively indicate the voltages of the reference signal S.sub.D and the comparison signal S.sub.E produced by the signal generator 10.

At t.sub.1, the terminal voltage V+ of the monitor element M.sub.i-MAX having maximum light reception becomes equal to V.sub.AGC, that is, the voltage of the comparison signal S.sub.E, whereupon the logic level of the output signal S.sub.i-MAX from the comparator CO.sub.i-MAX associated with the monitor element M.sub.i-MAX changes from high to low, as shown by waveform (4). At the time when the voltage V+ has decreased to V.sub.AGC, charge will have been stored in the light-detecting elements 2 to a level sufficient to provide an adequate video signal.

Before t.sub.0, output signals S.sub.1, S.sub.2, . . . S.sub.n from the comparators CO.sub.1, CO.sub.2, . . . CO.sub.n associated with the monitor elements M.sub.1, M.sub.2, . . . M.sub.n are at the high level, so that the NAND gate 11 produces a low level output signal S.sub.F. Therefore, if the comparator CO.sub.i-MAX associated with the monitor element M.sub.i-MAX produces a low level signal at t.sub.1, the logic level of the signal S.sub.F will change to high, as shown by waveform (5).

In response to this change, the storage control/signal processing circuit 3 which receives the output signal S.sub.F from the NAND gate 11 sends a reading signal S.sub.B to the reading circuit 4 at t.sub.2, as shown by waveform (6). The reading circuit 4 then supplies the circuit 3 with the charges of the light-receiving elements 2 in the form of a series of video signal S.sub.C segments. Upon receiving a predetermined number of video signal S.sub.C segments, the circuit 3 changes the logic level of the storage command signal S.sub.A to high at t.sub.3, as shown by waveform (1). As a result, the light-detecting elements 2 are cleared, as shown by waveform (2), and at the same time, the voltage V.sub.REF of the reference signal S.sub.D is again supplied to the monitor element M.sub.i in the detector circuit 1.sub.i through the switch element SW.sub.i-1 (see FIG. 3). As a result, the logic level of the output signal S.sub.i-MAX from the comparator CO.sub.i-MAX becomes high and the logic level of the output signal S.sub.F from the NAND gate 11 becomes low, as shown by waveform (5).

The above procedure completes the first operation of collecting video signal S.sub.C segments. Then, the circuit 3 produces a low-level storage command signal S.sub.A at T.sub.0 ', which starts the second and subsequent sequences of video signal collection in the same manner.

The level of the thus collected video signal S.sub.C segments will now be described. The group of light-detecting elements 2 is illuminated uniformly in the direction of their width (see FIG. 4) but not uniformly in their longitudinal direction. Therefore, light-detecting elements 2a.sub.MAX (four in FIG. 4) associated with the monitor element M.sub.i-MAX having maximum light reception produce video signal S.sub.C segments having different peak levels V.sub.PK as shown in FIG. 6. The signal level V.sub.PK of each of the four light-detecting elements 2a.sub.MAX was measured by shielding from light the three elements other than the particular element under measurement.

A light-detecting element 2a whose peak level V.sub.P is the highest of all the video signal S.sub.C segments collected (see waveform (7)) is not necessarily found among the four elements 2a.sub.MAX associated with the monitor element M.sub.i-MAX. However, as will be shown below, the peak level V.sub.P will not exceed a value four times as high as the average level V.sub.AVG of the video signal S.sub.C segments.

With the amount of charge stored in the monitor light-detecting element M.sub.i-MAX designated by Q.sub.m-MAX, the average amount of charge stored in the four light-detecting elements 2a.sub.MAX associated with that monitor element by Q.sub.pd-MAX, the amount of charge stored in another light-detecting element 2a.sub.PEAK which may output a video signal of the peak level V.sub.p by Q.sub.pd-PEAK, and the amount of charge stored in the monitor element M.sub.i-PEAK associated with that element by Q.sub.m-PEAK, the following relation is estabished between Q.sub.m-MAX and Q.sub.m-PEAK :

The two peak values of charge storage have the following relation:

where K is a constant of proportionality that depends on the dimensions of the light-detecting element 2a and the monitor element M.sub.i.

If Q.sub.pd-PEAK exceeds a value four times as high as Q.sub.pd-MAX, namely, if

the following equation is obtained (on the assumption that no charge is stored in the three light-detecting elements other than 2a.sub.PEAK associated with the monitor element M.sub.i-PEAK):

From Relations (2) and (3), Equation (4) can be rewritten as:

but this result is obviously inconsistent with the requirement expressed by Inequality (1).

Therefore, Q.sub.pd-PEAK will not exceed a value four times as high as Q.sub.pd-MAX. In other words, the light-detecting element 2a.sub.PEAK will not output a video signal S.sub.C segment greater than the value of P.sub.1 shown in FIG. 6. Since in no case will the light-detecting element 2a.sub.MAX produce a peak output level V.sub.PK greater than P.sub.1, the highest peak level V.sub.p of the video signal S.sub.C is V.sub.PK =P.sub.1.

If V.sub.AVG, the average level of the video signal S.sub.C, is assumed to be the level of the video signal S.sub.C segments obtained when all light-detecting elements 1a are illuminated uniformly, that level is determined by the difference between V.sub.REF and V.sub.AGC, which are respectively the voltages of the reference signal S.sub.D and the comparison signal S.sub.E produced by the signal generator 10. This is indicated by:

As already mentioned, the peak level V.sub.P for all video signal segments is not more than four times as high as their average level V.sub.AVG, and hence the latter can be set at a level which is one-fourth of the maximum level of the video signal that can be handled by the storage control/signal processing circuit 3.

As a further advantage, the light-detecting elements 2 are positioned separately from the monitor element M.sub.i.

Further details of the operation of the stored light detector circuit 1.sub.i shown in FIG. 2 will now be discussed along with an explanation of another configuration of that circuit and its operation.

After the switch element SW.sub.i-1 in the detector circuit 1.sub.i (FIG. 2) is opened, the terminal voltage of the monitor element M.sub.i (the voltage at the noninverting input terminal of the comparator CO.sub.i) decreases linearly with time (t-t.sub.0) as shown in waveform (3) of FIG. 5. The linearity of this change is expressed by:

where i.sub.p is the photo-current flowing through the monitor element M.sub.i, i.sub.d is the dark current flowing through that element, and C.sub.j is the junction capacitance of M.sub.i.

Rearranging Equations (6) and (7), the storage time, or equivalently the period extending form t.sub.0 to t.sub.1 when the voltage V+ is equal to V.sub.AGC at the inverting input terminal of the comparator CO.sub.i, is expressed as follows:

As is clear from Equation (8), the storage time (r.sub.1 -t.sub.0) required by the stored light detector circuit l.sub.i of FIG. 2 decreases as more dark current i.sub.d flows through the monitor element M.sub.i. Therefore, if the reading circuit 4 is designed so as to compensate for the dark current of the video signal S.sub.C, and if the magnitude of the dark current i.sub.d flowing through the monitor element M.sub.i is not negligibly smaller than the photo-current i.sub.p, the level of the video signal S.sub.C will be undesirably low.

FIG. 7 shows another embodiment of the detector circuit 1.sub.i which avoids such a disadvantage. In this embodiment, the detector circuit 1.sub.i further includes a switch element SW.sub.i-2 that is opened when the logic level of the storage start command signal S.sub.A becomes low and a dark monitor light-detecting element M.sub.i '. The circuit is so configured that the reference signal V.sub.AGC is supplied to both the dark monitor element M.sub.i ' and the inverting input terminal of the comparator CO.sub.i through the switch element SW.sub.i-2. The dark monitor element M.sub.i ' is identical to the monitor element M.sub.i except that the former is shielded from light. Therefore, M.sub.i ' has the same levels of dark current i.sub.d and junction capacitance C.sub.j as M.sub.i.

The operation of the detector circuit 1 according to the second embodiment will be described with reference to FIG. 8. In FIG. 8, V+' represents the change in the voltage at the noninverting input terminal of the comparator CO.sub. i when no dark current i.sub.d flows through the monitor element M.sub.i and the dark monitor element M.sub.i ', whereas V+ represents a voltage change at the same terminal when some dark current is flowing. If the amount of dark current i.sub.d is not zero, the logic level of the output signal S.sub.i from the comparator CO.sub.i becomes low at time t.sub.1 '. However, in the presence of the dark monitor element M.sub.i ', the potential V- at the inverting input terminal of comparator CO.sub.i decreases linearly as shown in FIG. 8 starting at t.sub.0, which is the time when both switch elements SW.sub.i-2 and SW.sub.i-1 are opened. Therefore, the logic level of the output signal S.sub.i from the comparator CO.sub.i becomes low at t.sub.1 as in the case when i.sub.d =0.

The potential V- at the inverting input terminal of the comparator CO.sub.i is given by:

As discussed above, the stored light detector circuit 1.sub.i shown in FIG. 7 is capable of compensating for dark current i.sub.d, and even in the presence of dark current flowing through the monitor element M.sub.i, the circuit yields results equivalent to those obtained when i.sub.d =0. Therefore, the stored time (t-t.sub.0) required in this circuit is represented by Equation (10), which is equivalent to Equation (8) except that i.sub.d is zero. That is:

The actual storage time is t.sub.1 -t.sub.0. As in the case of the embodiment shown in FIG. 2, the detector circuit 1.sub.i of Fig. 7 returns to its initial state at t.sub.3.

In the discussion above of the embodiments shown in FIGS. 2 and 7, the offset voltage of the comparator CO.sub.i is assumed to be negligible. However, in some cases, this offset voltage causes significant effects on the differential voltage .DELTA.V given by Equation (6). FIG. 9 shows a further embodiment of the stored light detector circuit l.sub.i in which the undesired effects of the offset voltage are eliminated.

The detector circuit 1.sub.i shown in FIG. 9 includes a switch element SW.sub.i-3 provided between the inverting input terminal and the output terminal of the comparator CO.sub.i. The switch element SW.sub.i-3 is opened when the storage command signal S.sub.A changes to the low level. The detector circuit 1.sub.1 further includes a switch element SW.sub.i-4 which is also opened when the signal S.sub.A changes to the low level and through which the comparison signal S.sub.E is fed to the noninverting input terminal of the comparator CO.sub.i, an inverter IN for inverting the signal S.sub.A, and a switch element SW.sub.i-5 connected between the monitor element M.sub.i and the noninverting input terminal of the comparator CO.sub.i and which is closed when the logic level of the output terminal of the inverter IN becomes high.

The operation of the detector circuit 1.sub.i shown in FIG. 9 will be described with reference to FIG. 10. Before t.sub.0, the logic level of the storage command signal S.sub.A is high, and as shown in FIG. 9, the switch elements SW.sub.i-1, SW.sub.i-3 and SW.sub.i-4 are closed whereas the switch element SW.sub.i-5 is open. Therefore, the comparator CO.sub.i, having its output terminal and inverting input terminal connected by the switch element SW.sub.i-3, operates as a voltage follower circuit. The noninverting input terminal of the comparator CO.sub.i is supplied with the comparison signal S.sub.E (V.sub.AGC). Thus, V-, which includes the offset voltage V.sub.OF of the comparator CO.sub.i, is given by:

At the time t.sub.0, the logic level of the command signal S.sub.A becomes low, whereupon the switch elements SW.sub.i-1, SW.sub.i-3 and SW.sub.i-4 are opened and the switch element SW.sub.i-5 is closed. As a result, the voltage V- at the inverting input terminal of comparator CO.sub.i decreases linearly with time as shown in FIG. 10.

The symbol V-' in FIG. 10 represents the change in voltage at the inverting input terminal of the comparator CO.sub.i included in the circuit of FIG. 7. In the embodiment of FIG. 7, if the comparator CO.sub.i has an offset voltage V.sub.OF of, for example, a positive polarity, the inverting input terminal of CO.sub.i is supplied with a voltage equal to the sum of V-' and V.sub.OF, and as a result, the output signal S.sub.i of the comparator CO.sub.i changes to the low level at the time t.sub.1 ". However, with the circuit 1.sub.i of FIG. 9, the voltage at the inverting input terminal of the comparator CO.sub.i is V-' minus V.sub.OF, and the output signal S.sub.i of CO.sub.i changes to the low level at the time t.sub.1 (FIG. 10). Therefore, the circuit 1.sub.i of FIG. 9 is entirely free from the undesired effect of the offset voltage V.sub.OF.

The potential profile for time t.sub.1 when signal S.sub.i changes to the low level is given by:

From this equation, the storage time determined by the detector circuit 1.sub.i of FIG. 9 is given by (which is identical to Equation (10)):

Switch elements SW.sub.i-1 and SW.sub.i-2 shown in FIG. 7, as well as switch elements SW.sub.i-3, SW.sub.i-4 and SW.sub.i-5 shown in FIG. 9, may be n-channel MOS-FETs. The NAND gate 11 shown in FIG. 1 functions substantially as a low-truth OR gate. The stored light detector circuit formed according to any of the embodiments shown above may be easily assembled in one package together with the charge storing photoelectric converter having a plurality of light-detecting elements 2. This integrated assembly ensures very easy signal processing and packaging.

According to the present invention, the proper storage time of charge storing photoelectric converters such as CCD sensors and MOS sensors can be provided by a single storage operation even under conditions where the amount of light received varies significantly. Furthermore, the invention provides a video signal of good quality that has a minimum change in the peak level. Therefore, the invention can be effectively applied to a charge storing photoelectric converter used in an autofocusing device in cameras.