Logarithmic Amplifier

The present invention relates to temperature compensated logarithmic amplifiers suitable for use with video signals.

A variety of different techniques exist for providing a logarithmic operation on an input voltage video signal. One of the most common approaches is to use a diode connected in the feedback path of an operational amplifier. The output voltage of such a combination is a logarithmic function. The bandwidth range of logarithmic amplifiers of this type is limited by a number of independent factors, including the open loop gain of the operational amplifier.

The bipolar transistor as is well known has an inherent logarithmic characteristic defined in equation (1).

Taking the natural log:

where

V.sub.BE =base to emitter voltage

V.sub.t =KT/q (thermal voltage)

I.sub.c =collector current

I.sub.s =saturation leakage current (temperature dependent).

Equation (2) shows the problem of using bipolar transistors to perform a logarithmic operation; namely, I.sub.S and V.sub.t are temperature dependent and provide separate and distinct temperature effects.

The object of this invention is to provide a logarithmic amplifier which uses bipolar transistors and is compensated for I.sub.S and V.sub.t and has temperature compensated D.C. stabilization.

This object is achieved by a DC stabilized logarithmic amplifier which in response to an input video signal V.sub.in having blanking and picture information intervals provides a temperature compensated logarithmic signal V.sub.out(comp) which is compensated for V.sub.t and I.sub.S, comprising:

a. A logarithmic amplifier cell having first and second matched bipolar transistors connected to compensate for I.sub.S and a third transistor connected in series with the second transistor for providing a constant collector current I.sub.REF through the second transistor, a voltage V.sub.out being taken from the junction of the second and third transistors;

b. feedback means including:

i. a voltage to current convertor responsive to V.sub.in and an error signal to provide the collector current I.sub.c for the first transistor during picture information intervals;

ii. means for producing a black reference current I.sub.BLK and for summing such I.sub.BLK current with the output of said voltage to current converter during the blanking interval to provide the collector current I.sub.c during blanking for the first transistor; and

c. a clamp feedback circuit producing the error signal and during the blanking interval being responsive to V.sub.out to adjust the error signal so that I.sub.c equals I.sub.REF thereby providing temperature compensated D.C. stabilization for V.sub.out ; and

d. a 1/Vt amplifier responsive to V.sub.out for correcting the thermal voltage Vt to provide a compensated voltage V.sub.out(comp) during the picture interval.

FIG. 1 is a block diagram of a logarithmic amplifier in accordance with the invention;

FIG. 2 depicts waveforms for signal parameters shown in FIG. 1; and

FIG. 3 is a schematic diagram of the logarithmic amplifier cell shown in FIG. 1.

Turning now to FIG. 1 which shows a block diagram of a logarithmic amplifier 10 in accordance with the invention. The input voltage signal V.sub.in is applied to a voltage to current convertor 12. An error signal produced by a clamp feedback circuit 14 is also applied to the voltage to current convertor 12. The output of the voltage to current convertor 12 is applied to a summing circuit 13 which produces the collector current I.sub.c used to drive a logging transistor Q.sub.1 in a log amplifier cell 16. See FIG. 3. The voltage to current convertor 12 does not require accurate DC offset stabilization due to the use of the feedback clamp circuit 14. During blanking, the summing circuit 13 receives a DC reference current I.sub.BLK produced by a black reference insert circuit 18. I.sub.BLK reference current is selected so that as shown in FIG. 2 the output V.sub.out and also V.sub.out(comp) (not shown) are straight line functions in response to an exponential V.sub.in. The clamp feedback circuit (14) samples the output voltage V.sub.out during a blanking interval of the input video voltage signal V.sub.in and adjusts the DC correction error signal, so as to change the value of I.sub.c in a manner which will be described later. See FIG. 2. The feedback clamp circuit 14 continuously provides the same error signal to the voltage to current convertor 12 during the picture information interval. This signal is only adjusted during the blanking interval. The feedback clamp circuit 14 generates the DC correction error signal by comparing the signal V.sub.out with a zero volt reference. FIG. 2 shows several representative wave forms of signals V.sub.in, I.sub.c, and V.sub.out. The input voltage V.sub.in, in linear space, includes a blanking interval and picture information interval. The output of the voltage to current convertor (I.sub.c) is also in the linear space. During the blanking interval, a control signal causes the black reference insert circuit 18 to add in a current I.sub.BLK and a control signal causes the clamp feedback circuit 14 to sample V.sub.out of the log amplifier cell 16 and adjust the D.C. error signal provided to the voltage to current convertor 12. The arrangement to temperature compensate for I.sub.S will now be described in connection with the circuit shown in FIG. 3.

As shown in FIG. 3, two matched bipolar transistors Q.sub.1 and Q.sub.2 have their bases connected. Collector current for the logging transistor Q.sub.1 is the current I.sub.c produced by the voltage to current convertor 12. A fixed reference voltage V.sub.BIAS is applied to the base of the transistor Q.sub.3 which is connected to the transistor Q.sub.2. The transistor Q.sub.3 provides a constant current source and produces a constant collector current I.sub.REF which is a function of the level of V.sub.BIAS. I.sub.REF is the emitter current and approximately the collector current for transistor Q.sub.2. The output V.sub.out is taken at the junction of the emitter of transistor Q.sub.2 and the collector of transistor Q.sub.3. A transistor Q.sub.4 is connected so that its collector is coupled to the positive potential V. This same potential is applied to the collector of transistor Q.sub.2. The emitter of transistor Q.sub.4 is electrically connected to the base of both the matched transistors Q.sub.1 and Q.sub.2. The input current I.sub.c also provides driving current through the base of the transistor Q.sub.4. This particular circuit arranging is such that the output voltage V.sub.out is compensated for I.sub.S. A conventional 1/VT amplifier 17 compensates for Vt and produces the output signal V.sub.out(comp). The operation of amplifier 17 will be discussed later.

The operation of the log cell 16 will now be described. First, I.sub.S of the logging transistor Q.sub.1 is assumed to be the same as I.sub.S for the matching transistor Q.sub.2. By Kirchoff's voltage law:

From Equation (1):

Equation (4) demonstrates that the output voltage V.sub.out has been temperature compensated for I.sub.S. During the blanking interval the clamping feedback circuit 14 in response to the control signal samples the output voltage V.sub.out to adjust the error signal. By using a "0" reference voltage as an input to circuit 14 and comparing it with V.sub.out, I.sub.c is forced to equal I.sub.REF. I.sub.c during such interval is equal to I.sub.BLK since V.sub.in is equal to zero. Since I.sub.c equals I.sub.REF, from Equation 5, V.sub.out is made equal to zero and V.sub.out is D.C. stabilized. The current I.sub.REF is a constant.

During blanking at the output of the log cell 16 V.sub.out includes a V.sub.t term. With the equation (5) being set equal to zero, and I.sub.c =I.sub.REF the value of V.sub.t is irrelevant and will not affect the clamping operation. Thus the clamping operation is unaffected by both I.sub.S and V.sub.t. I.sub.S is removed and V.sub.t is forced to be irrelevent by equation (5) being set equal to zero. This is what is meant by temperature compensated D.C. stabilization for V.sub.out. The 1/V.sub.t compensated amplifier 17 is required to compensate for V.sub.t on the V.sub.out signal and produces V.sub.out(comp). Amplifier 17 has a gain which is dependent on 1/V.sub.t. This gain can be accomplished as will be understood to these skilled in the art by including transistors matched to log transistor Q.sub.1. Its offset voltage drift need not be specified and is not of a concern because of the location at the clamp feedback circuit 14.

In operation during the picture interval, increasing the current I.sub.c causes V.sub.out(comp) to increase. Similarly, when I.sub.c decreases, V.sub.out(comp) decreases. V.sub.out(comp) is compensated for I.sub.S and V.sub.t.

The invention has been described in detail with particular reference to certain preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.