Method and Device for Regenerating the Integrity of the Bit Rate in a Plesiosynchronous System

(1) Field of the Invention

The present invention pertains to a method and a device for regenerating the integrity of the bit rate in a plesiosynchronous (i.e. nearly synchronous) system.

(2) State of the Prior Art

A data communication network or a pulse code modulation (PCM) telephonic network is said to be plesiosynchronous when the switching centers located along the path of a link between two subscribers have bit rates which are unequal yet very close to each another. The result of this is that each center sends its immediate neighbour a little more or a little less data than the latter is capable of handling. The reception will be said to be hyposynchronous when the clock frequency of the receiver is slightly lower than that of the transmitter, and the receiver will therefore necessarily lose data. In the opposite situation, the reception will be called hypersynchronous. In this case, the receiving sector will not receive sufficient data, and it will have to fill in the gaps with filler bits which are generally "unintelligible".

The receiving circuit of a subscriber receives, in a given time interval, a number of bits which is different from the number transmitted by its correspondent.

It will be said then that the network does not comply with the integrity of the bit rate of the message. This does not affect normal PCM phonic links where certain samples of speech may be skipped or repeated without altering the intelligibility of the message between the disturbances. However, for links which are scrambled from end to end, the loss of bit rate integrity means that the encoded message is shifted away from the decoding key, causing a total loss of intelligibility.

The object of the present invention is a method to remedy this loss of intelligibility which results from a disturbance by restricting it to an acceptable period of time. This method should be capable of being applied to links framed according to the CEPT standard as well as other standards such as, for example, the RITA standard.

According to the invention, which applies to transmissions by frames of several time intervals, the bits of useful information are multiplexed, during transmission, with at least one cyclical bit, in synchronism with the data for which, upon arrival, it is sought to regenerate the number of bits transmitted during each time interval, the said cyclical signal bit being called a "marker" and possessing a structure by which the start of its cycle can be unambiguously identified.

The present invention will be better understood from the following detailed description of a mode of embodiment taken as a non-exhaustive example and illustrated by the appended drawings of which:

FIG. 1 is a block diagram of a network according to the invention,

FIG. 2 is a block diagram of a marker processing circuit which uses the method of the invention, and

FIGS. 3, 4 and 5 are block diagrams of details of the embodiment of the circuits depicted in FIG. 2.

The present invention is used in plesiosynchronous communications networks in which the digitalized data (speech and other miscellaneous data) are transmitted in a temporal medium called a frame, which comprises time intervals, the number of bits contained in a time interval and the number of time intervals per frame varying according to the standards applied.

According to the CEPT standard, a frame comprises 32 time intervals of eight bits each. According to the RITA standard, the frame comprise 24 time intervals of six bits each.

The bit rate possible in each time interval is 64 k bits/s per CEPT frame, and 48 k bits/s per RITA frame.

In a homogeneous digital network, the order of the bits is invariant. The bits can therefore be made to play independent roles and, consequently, to multiplex several sub-channels in one and the same time interval.

As a non-exhaustive example, to connect a CEPT network with a RITA network, an interface called a "bridge" is used. In the CEPT-to-RITA direction, only six bits per time interval of the CEPT frame can be transmitted through this interface, the other two bits being lost. In the RITA-to-CEPT direction, six of the eight bits of the time interval of the CEPT frame are significant, the two additional bits being either insignificant or redundant.

Furthermore, certain systems can be used to coalesce (or combine) several consecutive time intervals to form only one channel with a data transfer rate which is a multiple of the basic rate.

Only a very brief description is given below of the marker processing circuits on the transmitting side of a plesiosynchronous communications network, since these circuits are trivial per se and can be easily adapted by the specialist to the alternative embodiments which he might choose, depending on the characteristics of the said network.

The circuits depicted schematically in FIG. 1 comprise a source transmitter 1 linked to an addressee receiver 2 by transit circuits 3, the set of elements 1 to 3 forming a part or the totality of a plesiosynchronous network.

The transit circuits 3 may comprise several intermediate circuits RI.sub.1 to RI.sub.n which work together with several intermediate transmitters EI.sub.1 to EIn through links L1 to Ln provided by cables, directional radio links etc., and there are similar links 4,5 linking the elements 1 and 2 to the element 3.

The source transmitter 1 comprises essentially a data generator 6 and a marker generator 7 linked to a multiplexer 8 the output of which is linked by a transmission circuit to the link 4. The generator 6 digitalizes, if necessary, the useful signals which it receives from various analog sources and constitutes frames, each time interval of which comprises, in a preferred mode of embodiment of the invention, two bit positions reserved for the markers introduced into the multiplexer 8 by the generator 7, and B positions for the useful signals. The marker generator 7 and the multiplexer 8 are, of course, synchronized, by means which are not depicted and are obvious to the specialist, with the frames of the generator 6. The marker generator 7 is a generator of fixed or changing binary sequences, the construction of which is obvious to the specialist. The transmission circuit 9 is a circuit which is capable of sending the link 4 the frames that come from the multiplexer 8. It is, for example, a telephonic transmission circuit for a link 4 by cable telephone.

The addressee receiver 2 comprises a reception circuit 10 which is capable of receiving the signals that come through the link 5. It is followed by a demultiplexer 11 which is capable of presenting the useful information signals at an output 12 and the markers introduced by the generator 7 at an output 13. This demultiplexer 11 is, of course, synchronized with the frames received. If the positions of the markers are fixed, the demultiplexer 11 sends the output 13 the bits of all the time intervals which are in these positions. If these positions change, the demultiplexer 11 is also controlled in accordance with the law governing this change, which is obviously the same in the transmitter 1 and the receiver 2. This law of change may, for example, be determined by a pseudo-random sequence generator, its corresponding generator being set in the receiver 2. The sequence used can further exhibit cryptological qualities, i.e. it will not be possible to reproduce the sequence without knowledge of an encoding key and it will not be possible to calculate this key on the basis of a sample in the sequence. The outputs 12 and 13 of the demultiplexer 11 are linked to a marker processing circuit 14 which will be described below with reference to FIG. 2. This circuit 14 is linked to an information-processing circuit 15 which corresponds to the generator 6 of the transmitter 1. This circuit 15 processes the useful information bits of the time intervals received to restore this information, if necessary, after digital-analog conversion.

The circuit 14, which is depicted in greater detail in FIG. 2, comprises an input terminal 16 linked to the output 12 of the demultiplexer 11, and an input terminal 17 linked to the output 13 of this multiplexer.

The input 16 is linked to the input of a random-access memory 18 which, in the present case, has a capacity of 4,096.times.B bits. The output of the memory 18 is linked to the circuit 15.

The terminal 17 is linked to a marker-detecting (code comparator) circuit 19, the output of which is linked to a page-skipping control circuit 20 and to an input of an OR circuit bearing the reference 21.

The circuit 14 also has a terminal 22 to which an active edge of an initialization signal is sent from circuits not depicted in the figure, when starting up or at the start of reception of a communication, in a way known in itself. The terminal 22 is linked to the second input of the circuit 21 as well as to the zeroizing inputs of a page-writing counter 23 and a reading addresses counter 24. The output of the circuit 21 is linked to the zeroizing input of a line-writing counter circuit 25.

The circuit 14 further comprises a multiplexer 26, to the input of which are linked, on the one hand, the output of the counter 25, the two least significant wires and, in a preferred mode of embodiment of the invention, the most significant wire of the output of the counter 23 via an inverter 27 (in the present case, the output of the counter 23 comprises three wires as eight "pages" of writing are provided for) and, on the other hand, to the output of the counter 24. In the present case, the output of the counter 25 comprises nine wires which represent the least significant portion of the twelve-wire link to the multiplexer 26, the most significant wires of which come from the counter 23. The output of 24 comprises, of course, twelve wires.

The output of the multiplexer 26 is linked to the addressing input of the memory 18. A clock signals generating circuit 28 is linked to the read/write control input of the memory 18, to the control input of the multiplexer 26 and to the clock signal inputs of the counters 23 to 25. The output of the counter 25 is linked to the input of the circuit 20, the output of which is linked to the counting input of the counter 23. The circuit 28 is synchronized with the frames received.

FIG. 3 depicts a mode of embodiment of the page-skipping control logic circuit 20. It comprises an AND gate bearing the reference 29, with six inputs in the present case, these six inputs being linked to the most significant wires of the output of the counter 25. The output of the gate 29 is linked to an input of another AND gate 30 with two inputs, the other input of which is linked to the output of the circuit 19. The output of the gate 30 is linked to the counter 23. When this output is in the binary state "1", it permits the counter 23 to go forward under the action of the clock signal H.

FIG. 4 is the block diagram of an example of an embodiment of the circuit 19. The terminal 17 is linked to the series input of a shift register 31 or that of an analog circuit, such as a random-access memory for example, the capacity n of which equals at least the number of bits needed to identify the marker of a cycle. The circuit 19 comprises a second register 32 which is identical to the register 31 and which is initialized with the marker code given by the generator 33 similar to the generator 7 of the source transmitter. The output of each of the n cells of the register 31 is linked to an initial input of an exclusive-OR gate 34.sub.1 to 34.sub.n respectively, each second input of which is linked to an output of a corresponding cell of the register 32. Should the marker code have a fixed structure, the register 32 becomes unnecessary and the second input of the gates 34.sub.1 to 34.sub.n will be carried to the appropriate logic level by direct cabling. The outputs of the gates 34.sub.1 to 34.sub.n are linked to the inputs of an adder 35. The bit available at the output of the adder represents the distance of Hamming between the code present in the register 31 and the reference marker. In the circuit of FIG. 4 all the outputs, except the least significant outputs S.sub.O and S.sub.1 of the adder 35 are linked to NOR gate 36, the output of which is linked to a terminal 37 which constitutes the output terminal of the circuit 19. This terminal is therefore in the state "1" so long as the distance of Hamming is less than 4.

The choice of the markers is not restricted solely to the bit sequences. A marker character may comprise any number whatever of bits transmitted within the same time interval of the frame, occupying fixed or variable positions (according to a known law) of the transmitting and receiving ends. If, in a composite transmission network, time intervals according to CEPT standards are used for certain sections and time intervals according to RITA standards are used for other sections, it will not be possible to use the bit positions which are abandoned in the CEPT-to-RITA "bridge" (interface) for the CEPT time intervals.

In a particular example of an embodiment, we can take two fixed bits M.sub.2 and M.sub.2 forming a "dibit" which can assume the values "1" and "2" (01 and 10 respectively in binary notation). The marker cycle consists of a succession of "dibits" "1" and "2". The reception of a "0" or a "3" will reflect a transmission error. The reverse situation ("0" or "3" instead of "1" or "2" ) is also possible.

Since the markers are inserted at the input of the network (in the transmitter 1) in synchronism with the message which it is sought to regenerate the number of bits sent upon arrival (in the receiver 2), the interval between the starting of consecutive marker cycles undergoes the same alterations and is lengthened or shortened in the same way as the useful binary data flow.

To restore the same number of bits at the output of the network as at the input, it suffices to:

(1) Ensure the integrity of the number of marker cycles. This condition is fulfilled if the marker cycle is long enough before the duration of the frame and if the start of the cycle is not made undetectable through the loss of binary integrity and/or errors due to poor transmission in the network,

(2) Ensure the restoration in each marker cycle of the same number of bits as at the input. If these bits are the same at the output as at the input, the output bit rate is intelligible. If the passage through the network has caused a shift in the plesiosynchronism, the bit rate becomes unintelligible until a fresh start of the marker cycle makes it possible to "pick up the thread" of the transmission.

The useful binary data flow coming to the terminal 16 is recorded in the buffer memory 18 comprising several "pages", each of which contains a certain number of "lines". The capacity of this memory corresponds to the binary data flow transmitted during one marker cycle. In the present case, the memory 18 comprises eight pages of 512 lines each, with each line containing B bits giving a total capacity, as indicated above, of 4096.times.B bits.

The writing and reading in the memory 18 are controlled by the clock 28 which is itself synchronized with the incoming frames. The writing addresses are given by the counters 25 and 23, and the reading addresses by the counter 24 which is independent of the two preceding counters. The reading addresses move forward cyclically without any break in sequence. It is therefore at the reading stage that the bit is re-justified according to the detection of the marker cycles. The detection of the start of the cycle sets up the MR signal (at the output of the circuit 19) which should cause the counter 23 to skip to a page start. This MR signal zeroizes the counter 25. The end of the cycle of this counter 25 makes the counter go forward by one page. Similarly, when the MR signal arrives slightly ahead of the end of the counter 25 cycle, it makes the counter 23 skip to the start of the following page.

By contrast, when the MR signal arrives slightly after the end of the counter 25 cycle, it should not cause a second skipping of a page.

To meet these page-skipping conditions, the three least significant wires of the counter 25 output, for example, are overlooked and the "AND" condition is set up on the other wires (gate 29). Thus, the gate 30, which enables the MR signal to reach the counter 23 is on only when the six most significant bits of the counter 25 output (i.e. from line 504 to 511--last line--of the counter 25) are all at "1".

If the marker is not identified, i.e. in the absence of the MR signal, the two counters 25 and 23 continue their development.

At the start of a communication, the counter 24 is zeroized and designates the line "0" of the page "0". The writing address is initialized at the line "0" of the page "4" (upon the transmission of an initialization signal, the counter 23 is indeed zeroized, but owing to the presence of the logic inverter 27 at its most significant output 2.sub.2 =4, it sends the value "4" as a page address to the memory 18). This makes it possible to take both a hypersynchronism and a hyposynchronism in the network into account at the start of the communication. The data read in the first three pages of the memory 18 are then unintelligible.

The criteria which determine the choice of the marker are: precise temporal identification at the start of the cycle, sound resistance to deterioration due to the network, compatibility with the networks passed through (especially as regards the disparity of the binary "1"s and "0"s), easy detection and swift recovery of binary integrity after disturbances.

Thus, in one mode of embodiment, it was decided to insert two marker bits M1 and M2 into each time interval at the binary positions 2 and 4 for the CEPT standard and the RITA standard.

So that it can be recognized whether a shifted marker is ahead or behind, its cycle must last more than twice the short cycle. The selected cycle durations are hence the result of a compromise between two contradictory requirements.

The code transmitted in a marker cycle should be easy to produce and identify; it should unambiguously define the starting frame of the cycle even in the presence of disturbances due to transmission errors and plesiosynchronism, and it should have a low probability of accidental imitation by error packets.

In a first example of an embodiment, the marker has a cycle of 512 dibits. It is made up of 506 "2's followed by six "1"s. The start of the cycle is identified by the successive observation of the sequence:

It is very easy to identify this marker by a simple condition of combinatorial logic in a window of twelve figures. An example of a logic identification circuit, well-known in the prior art, is depicted in FIG. 5. This circuit is similar to the one in FIG. 4, but the registers 31 and 32 have been duplicated at 31a, 31b, 32a, 32b, to store the two bits of each dibit separately; the exclusive-OR gates too are duplicated at 34a, 34b to compare each bit of a dibit separately and to input an OR gate 34c giving a single result for the entire dibit.

The distance of Hamming is increased by one unit for each error and by two units for each shift. The identification of the marker is obtained even in the presence of a transmission error, overlooking the least significant output SO of the adder 35.

The distance of Hamming between a marker and a shifted marker can be increased either by increasing the number of symbols contained in the window of comparison (but this would amount to complicating the logic identification condition) or by optimizing the sequence of symbols contained in the window.

In a second example of a mode of embodiment, the sequence of seven dibits is used (between oblique strokes) =

The distance of Hamming resulting from any shift whatever, ranging from -3 to +3, is 4 at the minimum. This is what is used in the circuit of FIG. 5. It is also possible to overlook the output S.sub.1 of the adder 35, making it possible to identify the marker in the presence of two transmission errors.