Timing Data Reproduction System

The present invention relates to a timing data reproduction system for a digital receiver.

In digital communications utilizing frequency shift keying (FSK), only the digital signal is transmitted so that the timing data required for sampling the incoming data signal must be generated in a receiver so as to decode the incoming data signal correctly.

To this end, there has been devised and demonstrated a system using a pilot tone signal. That is, when a telephone circuit or line is used for data transmission, the carrier is modulated in a suitable manner so as to transmit the data. A pilot tone is transmitted on an idle frequency band which is not used for the data transmission. At the receiving side, in response to this pilot tone the timing data for sampling is received.

Since the data and the pilot tone are sent by different frequency bands, in addition to a data receiver an additional receiver for receiving the pilot tone must be provided. Thus the pilot tone system is disadvantageous in that it is very complicated in construction.

There has also been devised and demonstrated a system wherein the zero-crossings of the received base-band signal are directly detected or the transition points of the two-valued signal obtained by the reshaping of the received signal so as to control the frequency or phase of a local oscillator which generates the sampling timing clock, thereby synchronizing the sampling clock with the incoming data signal. This system has also some problems as will be described below.

In the zero-crossing detection system, all of the signals to be processed cannot be digitized because the analog signal must be used for the zero-crossing detection. In the system wherein the transitions of the two-valued signal, the differentiation of the signal is needed for the direct transition detection. In order to overcome this problem, there may be considered to detect the transition time points by means of the digital sampling, but this is possible only at a considerably high sampling frequency. Furthermore, in the case of the ultra-high speed data transmission through for instance an optical transmission line, it would be extremely difficult to obtain directly the time relationship between the zero-crossings and the sampling time points. Even in the case of the low-speed data transmission through telephone networks with FSK modes, the incoming data signal must be sampled at a frequency considerably higher than the baud rate of the incoming data signal in order to detect the baud timing data. If it is attemped to process all these operations with the use of a microcomputer in full-digital manner, the overhead of the microcomputer would be inhibitively increased. For instance, assume that the transmission speed be 600 bauds and 16 samplings be made for one baud. Then one sampling must be executed in such a short time as 1/(600.times.16).apprxeq.104.times.10.sup.-6 seconds. Such high sampling speed surpasses even a highest processing speed of the microcomputer.

There is also known a timing data reproduction system of the type using a squaring circuit and a narrow-band filter. However the narrow-band filter must have a high Q and must be correctly tuned to the frequency of a predetermined baud rate. When the Q factor is too low, the reproduced timing signal will be considerably adversely affected by jitter. When the narrow-band filter is not correctly tuned, off-set of the phase of the reproduced timing signal will occur, resulting in phase error. In addition, in order to attain in the form of an analog circuit a narrow-band filter which has a high Q factor and is correctly tuned, the timing data reproduction system needs component parts which must operate at an extremely higher degree of accuracy in an extremely highly reliable and dependable manner. In addition, the system would require a large number of ALUs, thus increasing the cost.

One of the objects of the present invention is therefore to provide a timing data reproduction system which is extremely simple in construction and may find easier applications in various fields.

As herein described, the present invention provides a timing data reproduction system comprising a shift register and an oscillator of the type whose output frequency or phase may be controlled in response to the input, whereby the timing data for sampling may be derived from the incoming data signal.

FIG. 1 is a view used for the explanation of the fundamental principle of the present invention;

FIG. 2 is a block diagram of a first embodiment of the present invention;

FIGS. 3 and 4 are timing charts used for the explanation of the mode of operation of the first embodiment shown in FIG. 2 for forcing the sampling clock to synchronize in phase with the incoming data signal when the former is leading and lagging behind the latter, respectively;

FIG. 5 shows a timing chart used for the explanation of some countermeasures against malfunctions of a timing data reproduction system which arises even when the sampling clock is in perfect synchronization with the incoming data signal;

FIG. 6 is a block diagram of a second embodiment of the present invention;

FIG. 7 is a block diagram of a third embodiment of the present invention;

FIG. 8 is a block diagram of a fourth embodiment of the present invention;

FIG. 9 is a block diagram of a fifth embodiment of the present invention;

FIGS. 10 and 11 show timing charts used for the explanation of the mode of operation of the fifth embodiment for synchronizing the sampling clock with the incoming data signal when the former is leading and lagging behind the latter;

FIG. 12 is a block diagram of a sixth embodiment of the present invention;

FIG. 13 is a block diagram of a seventh embodiment of the present invention; and

FIGS. 14 and 15 are timing charts used for the explanation of the mode of operation of the seventh embodiment for synchronizing the sampling clock with the incoming data signal when the former is leading and lagging behind the latter, respectively.

Referring first to FIG. 1, the underlying principle of the present invention will be described. It is assumed the codes forming time-serial data are received at a predetermined time interval Tb and one of the codes is rectangular waveform pulse P. The lead or lag of the phase of the incoming pulses P at a sampling time point is explained as follows; A sampling time point t is defined by the following relation

(See also FIG. 1). The pulse P.sub.0 shown at (a) in FIG. 1 is sampled at t=0. That is, the center of the pulse P coincides exactly with the sampling time point. Therefore the pulse P is correctly in phase with the sampling time point. The pulse P.sub.1 shown at (b) in FIG. 1 lags behind the pulse P shown at (a) by a time .tau.. That is, the sampling time point (t=0) leads the center of the pulse P.sub.1 by .tau.. The pulse P.sub.2 shown at FIG. 1(c) leads the pulse P.sub.0 by .tau.. That is, the sampling time point (t=1) lags behind the center of the pulse P.sub.2 by .tau..

In FIG. 1(a), the function x(t) is plotted along the ordinate while the time t, along the abscissa. Then FIG. 1(b) shows the function x(t-.vertline..tau..vertline.), and FIG. 1(c), the function x(t+.vertline..tau..vertline.).

As shown in FIG. 1, not only the pulse P.sub.0 which is in phase with the sampling point (t=0) but also the pulses P.sub.1 and P.sub.2 may be sampled as far as the following relation may be held:

where .tau. is the lead or lag in time of the center of the pulse P with respect to the sampling time point as described above. However the incoming data are inevitably subjected to distortions, noise, jitter and so on during transmission so that it is necessary to coincide the sampling time point with the center of the pulse P. In other words, the further the sampling time point leads or lags the center of the incoming pulse P, the greater the sampling errors become. Mathematically the following relationship must be always satisfied:

To this end, it will be required to detect whether the sampling time point t leads or lags behind the center of the incoming pulse P so as to establish a correct sampling time point. In other words, the timing information must be in phase with the center of each of the pulse codes of the incoming data.

Next the scheme for detecting whether the sampling time point leads or lags behind the center of the pulse P will be described. Each data pulse P is detected or sampled two or three times at a time interval of Tb/2, and the two or three sampled values are compared with each other so as to detect whether the sampling time point leads or lags behind the center of the sampled data pulse P. Then the two or three sampled values have one of the following three relationships:

The relationship (I) indicates that the sampled values obtained by the successive samplings at an interval of Tb are equal. Therefore the lead or lag of the timing pulse point or .tau. cannot be detected. The second relationship may be interpreted as .tau.<0. That is, the sampling time point leads the center of the data pulse P. The third relationship (III) may be interpreted as .tau.>0. That is, the sampling time point lags behind the center of the data pulse P.

Therefore it follows that in order to make the phase error .tau. of the sampling time point zero, the sampling time point must be delayed in phase when the second relationship (II) is detected. Alternatively, the repetition frequency of the sampling pulses must be lowered. In like manner, when the third relationship (III) is detected, the sampling point time must be advanced in phase or the repetitive frequency of the sampling pulses must be increased. To this end, a sampling timing pulse oscillator may be incorporated into a phase locked loop (PLL) so as to cause the sampling pulses to follow the transmission frequency and phase of the incoming data pulses.

In FIG. 2 is shown a block diagram of a first embodiment of the present invention. It includes first and second D flip-flops D.sub.1 and D.sub.2, a shift register SR, first, second and third Exclusive-Or gates E.sub.1 -E.sub.3, first and second AND gates A.sub.1 and A.sub.2 and a variable phase, voltage-controlled oscillator. A wave-shaping circuit for reshaping the incoming data pulses is not shown.

Next the mode of operation of the first embodiment will be described. An incoming, binary data pulse signal SSX is applied to the terminal D of the flip-flop D.sub.1 which receives at its terminal C the clock signal SVCO from the voltage-controlled oscillator VCO. In response to the positive edge of the clock pulse, the flip-flop D.sub.1 is triggered so as to sample the incoming data pulse signal SSX. The output signal SD.sub.1 is transmitted from the terminal Q to the input terminal ISR of the shift register SR with a capacity of two bits. In this embodiment, the flip-flop D.sub.1 serves as a sample and hold circuit, thereby preventing the malfunctions of the Exclusive-Or gates E.sub.1 and E.sub.3. Every time when the clock pulse SVCO is applied to the input terminal C of the shift register SR, the latter is triggered in response to the positive edge of the clock pulse so as to shift the data signal SD.sub.1 by one bit. The signal SQ.sub.1 which appears at the output terminal Q.sub.1 is therefore one bit behind the data signal SD.sub.1 applied to the input terminal ISR. The output signal SQ.sub.2 which appears at the output terminal Q.sub.2 lags behind the input signal SD.sub.1 by two bits.

Exclusive-Or gate E.sub.1 detects whether or not the data signal SD.sub.1 coincides with the output signal SQ.sub.1 from the output terminal Q.sub.1 of the shift register SR and gives the output "1" when they do not coincide with each other. In like manner, Exclusive-Or gate E.sub.2 detects whether or not the output signals SQ.sub.1 and SQ.sub.2 from the shift register SR coincide with each other and gives the signal "1" when they do not coincide with each other. The third Exclusive-Or gate E.sub.3 compares the data signal SD.sub.1 at the input terminal ISR of the shift register SR with the output signal SQ.sub.2 therefrom and generates the signal "1" when they do not coincide with each other.

The oscillator VCO is such that its frequency or phase may be externally controlled, and its center frequency is set to a frequency two times the Baud rate of the incoming data signal SSX. The flip-flop D.sub.2 functions as a frequency divider which delivers the output whose frequency is one half (1/2) of the output frequency of the oscillator VCO. More particularly, the flip-flop D.sub.2 responds to the positive edge of the output signal SVCO so as to reverse the output. The output signal SD.sub.2 which appears at the output terminal Q of the flip-flop D.sub.2 is used as the clock for sampling the incoming data pulse signal.

AND gate A.sub.1 receives the output E.sub.3 from the first Exclusive-Or gate E.sub.1, the output SE.sub.3 from the third Exclusive-Or gate E.sub.3 and the output SD.sub.2 from the second flip-flop D.sub.2. When all the inputs to the AND gate A.sub.1 are "1"s, the gate A.sub.1 gives the output SA.sub.1 to the input terminal SLOW of the oscillator VCO so that the output signal SVCO of the oscillator VCO may be delayed in phase or decreased in frequency. AND gate A.sub.2 receives the output SE.sub.2 from the second Exclusive-Or gate E.sub.2, the output SE.sub.3 from the third Exclusive-Or gate E.sub.3 and the output SD.sub.2 from the second flip-flop D.sub.2. When all the inputs are "1"s, the gate A.sub.2 gives the output signal SA.sub.2 to the input terminal FAST of the oscillator VCO so that the output signal SVCO from the oscillator VCO may be advanced in phase or increased in frequency.

The output signal SD.sub.2 from the second flip-flop D.sub.2 are applied to both the AND gates A.sub.1 and A.sub.2 because of the reasons to be described below. As described above, the first, second and third Exclusive-Or gates E.sub.1, E.sub.2 and E.sub.3 compare the input signal SD.sub.1 to the shift register SR with its output SQ.sub.1, the output SQ.sub.1 with the output SQ.sub.2 and the input signal SD.sub.1 with the output signal SQ.sub.2, respectively. These comparison operations are executed at a time interval of Tb/2; that is, at a frequency a half of the pulse duration of the incoming data pulses (See FIG. 1). When each comparison operation is executed at the timing of 1.5Tb, 2.5Tb and so on of the input data signal SD.sub.1 at the input terminal ISR of the shift register SR; that is, when the sampling time point coincides with the ends of the incoming data pulse P, the results of the comparison operations may be neglected. However each comparison operation is executed at the timing of 0Tb, 1Tb, 2Tb and so on; that is, when the data pulse at a reference time point is sampled, the output signal SD.sub.2 from the second flip-flop D.sub.2 enables AND gate A.sub.1 or A.sub.2 so that the comparison result may be applied to the oscillator VCO.

When the incoming, time serial data pulses are sampled in response to the positive edges of the clock signal SD.sub.2 from the second flip-flop D.sub.2, the sampling errors may be minimized. When the output signal SD.sub.2 from the second flip-flop D.sub.2 is at a high level or "1", the effective incoming data (that is, the data sampled at the reference time points such as 0Tb, 1Tb and so on) appear at both the input terminal ISR and the output terminal Q.sub.2 of the shift register SR. On the other hand, when the clock signal SD.sub.2 is at a low level or "0", no effective incoming data are obtained from the terminals ISR and Q.sub.2 while the effective incoming data appears at the terminal Q.sub.1 of the shift register SR. This will be explained mathematically as follows:

(I) When the clock signal SD.sub.2 is "1", x (t0+.tau.) appears at the input terminal ISR; x (t0-Tb/2+.tau.) appears at the output terminal Q.sub.1 ; and x (t0-Tb+.tau.), at the output terminal Q.sub.2.

(II) When the clock signal SD.sub.2 is "0", x (t0-Tb/2+.tau.) is present at the input terminal IRS; x (t0-Tb+.tau.) appears at the output terminal Q.sub.1 ; and x (t0-3Tb/2+.tau.) appears at the second output terminal Q.sub.2.

As described above, it is only when the clock signal SD.sub.2 is "1" when the logic circuit of the type shown in FIG. 2 can detect whether or not the sampling pulse is in phase with the incoming data pulse. More particularly, assume that both the clock signal SD.sub.2 and the output signal SE.sub.3 from the third Exclusive-Or gate E.sub.3 are "1"s; that is, there exist the effective incoming data at both the input terminal ISR and the second output terminal Q.sub.2 of the shift register SR and are different in logic level from each other. Then (a) when the incoming data signal SD.sub.1 and the output signal SQ.sub.1 at the first terminal Q.sub.1 are different in logic level from each other, the output signal SE.sub.1 from the first Exclusive-Or gate E.sub.1 is "1" and consequently the output signal SA.sub.1 from the first AND gate A.sub.1 is "1". This means that the clock signal SD.sub.2 or the sampling pulse leads the incoming data signal SSX. Therefore the output SAL (="1") from the first AND gate A.sub.1 is impressed at the SLOW terminal of the oscillator VCO so that the oscillation phase is delayed or the oscillation frequency is decreased, thereby making the absolute value of the sampling phase error .tau. zero. (b) When the output signal SQ.sub.1 at the output terminal Q.sub.1 is different in logic level from the output signal SQ.sub.2 at the second output terminal Q.sub.2 of the shift register SR, the output signal SE.sub.2 from the second Exclusive-Or gate E.sub.2 becomes "1" and consequently the output signal SE.sub.2 from second AND gate A.sub.2 becomes also "1". This means that the clock signal SD.sub.2 or the sampling pulse lags behind the incoming data pulse SSE. Therefore the output signal SA.sub.2 (="1") is applied to the FAST terminal of the oscillator VCO so that the oscillation phase may be advanced or the oscillation frequency may be increased, thereby making the sampling phase error .tau. zero.

From the foregoing explanation it is apparent that the output SA.sub.1 from the first AND gate A.sub.1 and the output signal SA.sub.2 from the second AND gate A.sub.2 cannot be "1" simultaneously If both the outputs SE.sub.1 and SE.sub.2 from the first and second Exclusive-Or gates E.sub.1 and E.sub.2 were "1"s at the same time, the output signal SE.sub.3 from the third Exclusive-Or gate E.sub.3 would be "0" because the signals SD.sub.1, SQ.sub.1 and SQ.sub.2 are all binary logic signals.

In FIG. 3 is shown the timing chart of the signals of the first embodiment described above with reference to FIG. 2. It shows the process for progressively delaying the phase of the sampling pulse which is initially shown as leading the incoming data pulse so as to synchronize the leading or positive edge of the sampling clock pulse SD.sub.2 with the center B of the data pulse P'. More particularly, as indicated by the arrow A, the sampling time point or the positive edge of the sampling clock pulse SD.sub.2 initially leads the center of the data pulse P (the incoming data SSX) considerably. However as described above the output signal SA.sub.1 from first AND gate A.sub.1 is repeatedly applied to the SLOW terminal of the oscillator VCO so that the sampling time point is progressively delayed. Finally the positive edge of the sampling clock pulse SD.sub.2 is made to synchronize correctly with the center of the data pulse P' as indicated by the arrow.

In FIG. 4 is shown the timing chart illustrating the process for progressively advancing the phase of the sampling clock pulse SD.sub.2 which is initially shown as lagging behind the data pulse P so as to correctly synchronize the sampling clock pulse SD.sub.2 with the center of the data pulse SSX. More particularly, initially the sampling time point or the positive edge of the sampling clock pulse SD.sub.2 lags behind the center of the data pulse P as indicated by the arrow A', but the output signal SA.sub.2 from second AND gate A.sub.2 is repeatedly applied to the FAST terminal of the oscillator VCO so that the sampling time point or the positive edge of the sampling clock pulse SD.sub.2 is progressively advanced and finally correctly synchronized with the center of the data pulse P' as indicated by the arrow B'.

In FIG. 5 is shown the timing chart when the sampling clock pulse SD.sub.2 is initially in phase with the data pulse SSX; that is, there exists no sampling phase error. Since the positive edge of the sampling clock pulse SD.sub.2 correctly coincides with the center of the data pulse P (SSX) as indicated by the dotted-line arrow, the sampling clock pulse SD.sub.2 is correctly in phase with the data pulse. At the positive edges C and C" and at the negative edge C' the transition of the data pulse SSX occurs. Since the logic circuit shown in FIG. 2 operates on the binary-state signal or two-valued signal, the sampled value at the point C, C' or C" must be "0" or "1". In general, the incoming data signal SSX is subjected to waveform distortions and jitter occurs during transmission so that the transition point C, C' or C" or the leading or trailing edge of the data pulse SSX is caused to be displaced or fluctuated in the range indicated by the dotted lines in FIG. 5. (This phenomenon will be referred to as "jitter" simply in this specification.) Because of jitter, even when the sampling clock pulse SD.sub.2 is in correct phase relationship with the incoming data pulse SSX; that is, even when there is no sampling phase difference, the sampling clock pulse SD.sub.2 may be detected as being out of phase with the data pulse SSX at the transition point C, C' or C". As a result, the sampling clock pulse SD.sub.2 is adversely affected, causing jitter. However, these adverse effects may be satisfactorily minimized by setting the loop gain of the phase-locked loop to a suitable small value or by providing suitable loop filter means. These and other countermeasures are well known to those skilled in the art, so that no further description shall be made in this specification.

From the timing charts shown in FIGS. 3 and 4, it might have been noticed that the output signal SE.sub.3 from the third Exclusive-Or gate E.sub.3 plays no role in the first embodiment shown in FIG. 2. That is, when the reliability of the first embodiment shown in FIG. 2 is so high that the normal operations may be ensured at any time, the third Exclusive-Or gate E.sub.3 may be eliminated. In the normal operations, if the logic circuit shown in FIG. 2 would not experience any adverse external effects such as noise, the output signal SQ.sub.1 from the first output terminal Q.sub.1 of the shift register SR would be equal in logic level to the input signal SD.sub.1 and the output signal SQ.sub.2 from the second output terminal Q.sub.2 of the shift register SR when the sampling clock pulse SD.sub.2 is "1" (so that the effective data pulses exist both at the input and second output terminals ISR and Q.sub.2 of the shift register SR) and moreover when the input signal SD.sub.1 and the second output signal SQ.sub.2 of the shift register SR coincide with each other. However because of noise or the like, the first output signal SQ.sub.1 will not coincide with the input signal SD.sub.1 (and the second output signal SQ.sub.2) in some cases. The third Exclusive-Or gate E.sub.3 is incorporated in the logic circuit shown in FIG. 2 in order to avoid such malfunctions as described above due to the external and internal noise. That is, no output signal SE.sub.3 can be derived from the third Exclusive-Or gate E.sub.3 when the input and second output signals SD.sub.1 and SQ.sub.2 are equal in logic level even when the first output signal SQ.sub.1 from the first output terminal Q.sub.1 of the shift register SR does not coincide with the input and second output signals SD.sub.1 and SQ.sub.2. As a consequence neither first AND gate A.sub.1 or second AND gate A.sub.2 is disabled, so that malfunctions may be avoided. The foregoing explanation may suffice to make those skilled in the art understood the function of the third Exclusive-Or gate E.sub.3.

A second embodiment of the present invention shown in FIG. 6 is substantially similar in construction to the first embodiment shown in FIG. 2 except that instead of the first flip-flop D.sub.1 which serves as a sample and hold circuit, flip-flops D.sub.1 and D.sub.1', are interconnected between first AND gate A.sub.1 and the SLOW terminal of the oscillator VCO and between second AND gate A.sub.2 and the FAST terminal of the oscillator VCO. These flip-flops D.sub.1 and D.sub.1' serve also as a sample and hold circuit and are substantially similar in construction. The second embodiment is further differentiated from the first embodiment in that the terminal C of the flip-flop D.sub.2 is connected through a delay line DL to the clock input terminal C of the shift register SR. A time delay Td attained by the time-delay circuit DL is so selected as to satisfy the following relationship:

The function of the time-delay circuit DL is to prevent a shift in the shift register SR immediately before the signal is set in the flip-flop D.sub.1 or D.sub.1' in response to the positive edge of the output signal SD.sub.2 from the flip-flop D.sub.2. In the second embodiment the sum of the time-delay provided by the Exclusive-Or gates E.sub.1, E.sub.2 and E.sub.3, AND gates A.sub.1 and A.sub.2 and the time-delay circuit DL must be greater than the operating time of the D-type flip-flops D.sub.1, D.sub.1' and D.sub.2.

Referring back to FIG. 2, the output signals SA.sub.1 and SA.sub.2 of first and second AND gates A.sub.1 and A.sub.2 may be expressed in logical symbolic form as follows:

where .LAMBDA.=logic AND, and .sym.=Exclusive-Or.

Eqs. (4) and (5) may be rewritten as follows:

where V=logic OR and SQ.sub.1 =logic NOT of the statement SQ.sub.1.

A logic circuit implementing these equations (4') and (5') is structurally different from the logic circuit shown in FIG. 2 but may accomplish the same functions.

A third embodiment shown in FIG. 7 is subsantially similar in construction to the first embodiment shown in FIG. 2 except that the third Exclusive-Or circuit E.sub.3 is eliminated and that a first inverter N.sub.1 is interconnected between the first Exclusive-Or gate E.sub.1 and the second AND gate A.sub.2 while a second inverter N.sub.2 is interconnected between the second Exclusive-Or gate E.sub.2 and the first AND gate A.sub.1. These first and second inverters N.sub.1 and N.sub.2 may inhibit that the output signals SE.sub.1 and SE.sub.2 from the first and second Exclusive-Or gates E.sub.1 and E.sub.2 becomes "1" simultaneously. The mode of operation of the third embodiment may be apparent to those skilled in the art when reference is made to FIGS. 3 and 4.

As described elsewhere, the Exclusive-Or gates E.sub.3 shown in the first embodiment (See FIG. 2) may be eliminated when the incoming data pulse SSX is not so adversely affected by noise and not so adversely distorted in shape during transmission that no malfunction of the logic circuit will result. The elimination of the third Exclusive-Or gate E.sub.3 may be also possible by such an arrangement that the inputs to the SLOW and FAST terminals of the oscillator VCO may cancel each other if the output signals SA.sub.1 and SA.sub.2 from first and second AND gates A.sub.1 and A.sub.2 should be "1" simultaneously as will be described below.

A fourth embodiment of the present invention implementing the foregoing logical operations is shown in FIG. 8. The mode of the fourth embodiment is apparent to those skilled in the art when reference is made to the timing charts shown in FIGS. 3 and 4.

In the fourth embodiment, the output signals SA.sub.1, and SA.sub.2' from the first and second AND gates A.sub.1' and A.sub.2' may be expressed in the following logical symbolic form: ##EQU1##

A fifth embodiment of the present invention shown in FIG. 9 may implement the fundamental equations (1'), (2') and (3') described elsewhere in conjunction with the underlying principle of the present invention.

The output signals SA.sub.3 and SA.sub.4 from first and second AND gates A.sub.3 and A.sub.4 may be expressed in logical symbolic form as follows: ##EQU2## The logic "1" output signal SA.sub.3 from the first AND gate A.sub.3 is applied to the FAST terminal of the oscillator VCO so that the oscillation phase may be advanced or the oscillation frequency may be increased. The logic "1" output signal SA.sub.4 from the second AND gate is applied to the SLOW terminal of the oscillator VCO so that the oscillation phase may be delayed or the oscillation frequency may be decreased.

The mode of operation of the fifth embodiment will be described first with reference to FIG. 10. FIG. 10 shows the time chart of the process for progressively delaying the sampling time point, which is shown as leading the center of the data pulse P (SSX) as indicated by the arrow A, so as to correctly synchronize the sampling time point or the positive edge of the sampling clock pulse SD.sub.2 with the center of the data pulse P' as indicated by the arrow B. That is, as with the case of the first embodiment the output signal SA.sub.4 is repeatedly applied to the SLOW terminal of the oscillator VCO so that the oscillation phase may be progressively delayed or the oscillation frequency may be progressively decreased.

The process for synchronizing the sampling clock pulse SD.sub.2 with the data pulse SSX (p) when the clock pulse SD.sub.2 is initially detected as lagging behind the center of the data pulse p as indicated by the arrow A' may be understood with reference to FIG. 11. That is, the output signal SA.sub.3 is repeatedly applied from first AND gate A.sub.3 to the FAST terminal of the oscillator VCO so that the phase of the sampling clock pulse SD.sub.2 may be progressively advanced so as to correctly synchronize the positive edge of the sampling clock pulse SD.sub.2 with the center of the data pulse P' as indicated by the arrow B'.

A sixth embodiment of the present invention shown in FIG. 12 is substantially similar in construction to the fifth embodiment shown in FIG. 9 except that the third Exclusive-Or gate E.sub.3 is eliminated because of the reason described elsewhere referring to the fourth embodiment shown in FIG. 8. The mode of operation will be apparent from the time charts shown in FIGS. 10 and 11.

In the sixth embodiment, the output signals SA.sub.3' and SA.sub.4', from the first and second AND gates A.sub.3' and A.sub.4' may be expressed in logical symbolic form as follows: ##EQU3##

A seventh embodiment of the present invention shown in FIG. 13 may implement the fundamental equations (1), (2), (3), (1'), (2') and (3') and is therefore a combination of the first embodiment shown in FIG. 2 and the fifth embodiment shown in FIG. 9.

More particularly, the output signals SA.sub.1 and SA.sub.4 from the first and fourth AND gates A.sub.1 and A.sub.4 are applied to a first OR gate O.sub.1, and the output SO.sub.1 from the first OR gate O.sub.1 is applied to the SLOW terminal of the oscillator VCO. The output signals A.sub.2 and A.sub.3 from the second and third AND gates A.sub.1 and A.sub.3 are applied to a second OR gate O.sub.2, and the output signal SO.sub.2 from the second OR gate O.sub.2 is applied to the FAST terminal of the oscillator VCO.

The output signals SO.sub.1 and SO.sub.2 may be expressed in logical symbolic form as follows:

In FIG. 14 is shown the time chart for the process for progressively delaying the phase of the sampling clock pulse SD.sub.2, which is initially shown as leading the data pulse SSX as indicated by the arrow A, so as to correctly synchronize it with the sampling clock pulse as indicated by the arrow B. That is, the output signal SO.sub.1 from the first OR gate O.sub.1 is repeatedly applied to the SLOW terminal of the oscillator VCO so that the sampling phase of the sampling clock pulse SD.sub.2 is progressively delayed and finally correctly synchronized with the center of the data pulse SSX.

In FIG. 15 is shown the time chart of the process for progressively advancing the sampling phase of the sampling clock pulse SD.sub.2, which is initially shown as being lagging behind the data pulse SSX as indicated by the arrow A', so as to correctly synchronize the former with the latter as indicated by the arrow B'. That is, the output signal SO.sub.2 from the second OR gate O.sub.2 is repeatedly applied to the FAST terminal of the oscillator VCO so that the phase of the sampling clock pulse SD.sub.2 is progressively advanced and finally correctly synchronized as indicated by the arrow B'.

In summary, according to the present invention, contrary to the prior art systems, no differentiation is needed to obtain the zero-crossings; it is not necessary to increase the sampling frequency; no high Q filter is needed; the sampling frequency equal to two times of the baud rate of the incoming data pulse may suffice; and the zero-crossings may be detected not directly but indirectly. Thus there may be provided an accurate timing signal or data reproduction system which may easily digitalized and fabricated at low costs.