Digital Word Synchronizing Arrangement

Our invention relates to a digital word synchronizing arrangement. In particular, our invention relates to an arrangement or a method for achieving synchronization with digital synchronizing words provided at selected intervals in a digital message.

Sequences of digital signals are frequently used to transmit data, because such sequences can be transmitted rapidly and efficiently. However, such rapid transmission requires equally rapid and efficient synchronization of the data receiver with the words forming the information of the transmitted data message. Without such synchronization, the beginning and end of each information word is unknown, resulting in meaningless data. The synchronization problem is increased if the transmission medium is noisy or subject to fading, as it frequently is if the medium is a radio channel. For these and other reasons, predetermined synchronizing words are provided sequentially at spaced locations or times in a data message to provide a data receiver with the opportunity to recognize the synchronizing words and synchronize itself so as to accurately detect where the information parts or words of the data message begin and end.

Briefly and in accordance with our invention, we compare the received digital signals in a message with a stored predetermined digital synchronizing word. Upon the initial correct comparison indicating a correctly received synchronizing word, we compare the next four subsequently received synchronizing words with the stored predetermined synchronizing word. If any two of these four subsequent comparisons indicates a correctly received synchronizing word, we produce an in-synchronization signal to indicate that word synchronization has been achieved, and to indicate that information words can then be accurately read and utilized. However, if less than two of these four subsequent comparisons indicate a correctly received synchronizing word, we resume comparison of the subsequent digital signals until another initial correct synchronizing word is indicated. We then compare the next four synchronizing words, and if any two are correct, we produce an in-synchronization signal. If less than two are correct, we start again. This process is repeated as often as needed, or until no more synchronizing words are received.

The subject matter which we regard as our invention is particularly pointed out and distinctly claimed in the claims. The structure and operation of our invention, as well as advantages, may be better understood from the following description given in connection with the accompanying drawing, in which:

FIG. 1 shows a diagram illustrating a digital message for which our synchronizing arrangement is intended to be used;

FIG. 2 shows a block diagram illustrating our synchronizing arrangement; and

FIG. 3 shows a flow chart or diagram illustrating the operation of our arrangement of FIG. 2.

While persons of ordinary skill in the art will, after reading this description, appreciate that our invention can be used with various formats of data messages having various synchronizing words, we have selected the sequential data format of FIG. 1 to explain the operation of our invention. This data format is intended to be used to transmit a data message in cellular radio telephone systems. And while we describe our invention with binary types of data, persons skilled in the art will appreciate that our arrangement can be used with other types of data, such as ternary signals. The data format comprises a total of 1032 bits, and the bit number that starts each part of the format is indicated. The format of FIG. 1 starts with 101 dotting bits, which typically are alternate 1's and 0's to achieve bit synchronization. Next, starting with bit 102, the first synchronizing word of 11 bits is transmitted. In the cellular data message standard mentioned, this synchronizing word is comprised as follows: 11100010010. While other synchronizing words can be used, the indicated format is desirable in that it has a relatively small chance of being repeated in a message word. Following the first synchronizing word, a first message word of 40 bits starting with bit 113 is transmitted. These bits have binary values that convey the desired message. Next, starting with bit 153, 37 dotting bits are transmitted. These are followed by the second synchronizing word which is identical to the first synchronizing word. The second synchronizing word is followed by a second message word, which typically is the same as the first message word. This sequence is repeated to provide a total of 11 sequences comprised of dotting bits, a synchronizing word, and a message word. And, the synchronizing words are typically equally spaced by 77 bits: 40 bits of a message word plus 37 synchronizing bits. However, such equal spacing or time interval is not essential.

One of the reasons that this format was selected was that it typically enables a radio receiver to achieve bit synchronization and word synchronization in a relatively short time and with reasonable accuracy. This accuracy is improved if a word synchronizing arrangement in accordance with our invention is utilized.

FIG. 2 shows a block diagram that illustrates our synchronizing arrangement. While a typical preferred embodiment of our invention would more likely be achieved by means of a microprocessor and associated memory circuits, we have provided the block diagram of FIG. 2 in order to facilitate the understanding of our arrangement.

As shown, our arrangement includes a receiver 10 which receives and processes incoming signals from either a wire or radio medium, and if necessary, demodulates these signals. If these signals include speech or other information, they can be applied to appropriate circuits. The data signals are applied to a signal conditioner 11 which, if the data is in the form of modulated signals, converts these signals to digital signals having the appropriate or desired voltage levels. These digital signals are applied to a bit synchronization circuit 12 which, as known in the art, produces a clock signal of the appropriate frequency that is synchronized with the incoming bit signals. The clock signal is applied to various portions of our arrangement as needed. The bit signals are applied to a synchronizing word comparator or comparison circuit 13 which compares the incoming bit signals with a stored synchronizing word having the desired or predetermined bit sequence in a storage circuit 14. This comparison may be either in series or in parallel. Each time a correct sequence of synchronizing word bits (such as the 11100010010 mentioned) is found from this comparison, the comparator 13 produces an output signal that is applied to a good synchronizing word counter 15. When reset, the comparator 13 operates in a bit by bit mode to look at each new bit to determine if that new bit plus the prior (ten) bits form the correct synchronizing word. After an initial detection of a correct synchronizing word, the comparator 13 operates in a position mode and only looks at the 11 (or appropriate number of) bits which occur at the time or position of the next synchronizing word.

The counter 15 has appropriate outputs that respectively indicate a count of 1 good word, or a count of 2 good words, or a count of 3 or more good words as shown. Each time a count of 1, or a count of 2, or a count of 3 is reached, an enable signal is applied to a synchronizing word position indicator 16. If the count of counter 15 is less than 1, the indicator 16 is disabled.

The position indicator 16 is arranged to count clock bits from the circuit 12 so that when the indicator 16 is enabled by the initial detection of a synchronizing word, it can count the number of bits to indicate the time position or location of the next expected synchronizing word. After being enabled by an initial detection of a synchronizing word, the indicator 16 produces an output 1, 2, 3 or 4 respectively for the time or position in which succeeding synchronizing words 1, 2, 3 or 4 should appear. Thus, with reference to FIG. 1 again, if the first synchronizing word (bits 102 through 112) is correctly detected, the position indicator 16 can then count the number of bits to indicate the position of the second synchronizing word. This count would be the first message word of 40 bits plus the next 37 dotting bits, so that at the appearance of bit 190 of the second synchronizing word, the indicator 16 provides an output signal at output 1 to indicate that the first synchronizing word, after a detection of the initial synchronizing word, is in position. An output signal is provided at outputs 2, 3 and 4 to indicate the time or position of the second, third and fourth synchronizing words respectively after the initial detection of a synchronizing word. Of course, the initial detection may occur at any location in the message shown in FIG. 1. Each of the outputs 1, 2, 3 and 4 are applied to the synchronizing word comparator 13 to cause the comparator 13 to operate in the position mode and look for a synchronizing word at the proper time or position.

When the word position indicator 16 produces an output 4, this indicates that four synchronizing word positions have occurred since the initial correctly detected synchronizing word. This 4 output is applied to an enable input of an in-synchronization output gate 18.

This 4 output from the indicator 16 is applied to open or enable an in-synchronization output gate 18. If the good word counter 15 has reached a count of 3 or more, its 3 output is passed by the enabled gate 18 to indicate that word synchronization has been achieved by detection of a first correct synchronizing word, and by detection of two additional synchronizing words during the next four synchronizing word positions. When passed by the gate 18, this in-synchronization signal can be utilized by a decode circuit 21 to indicate to the receiver 10 or other circuits that word synchronization has been achieved, and hence the message words of FIG. 1 can be accurately and correctly decoded or utilized.

The position indicator 16 is also provided with an output to indicate the end of the position of synchronizing word 4. This output is applied to reset the word comparator 13 for bit by bit comparison, and to reset the word counter 15 and the position indicator 16 to zero. Upon this reset, the arrangement starts looking for an initial synchronizing word again, whether an in-synchronization output was produced or was not produced.

FIG. 3 shows a flow chart or diagram illustrating the operation of the arrangement of FIG. 2, and also illustrating the operation that would be performed by a microprocessor and appropriate memory circuits to achieve the same function as that provided by the arrangement of FIG. 2. With respect to FIG. 3, a start function is initiated by a start circuit 30 to clear or reset the various circuits as indicated by the block 31. This permits the sequential digital bits to be shifted into the word comparator as indicated by the block 32.

Bits continue to be shifted into the word comparator as long as no initial synchronizing (sync in FIG. 3) word is detected as indicated by the decision block 33. However, once an initial synchronizing word is detected, the circuit waits for additional synchronizing and message words as indicated by the block 34. Each time a subsequent synchronizing word position occurs, the decision block 35 determines whether a correct synchronizing word is present or detected. If the determination is no, a word counter 37 is incremented. If the determination is yes, a correct synchronizing word counter 36 is incremented, which in turn increments the word counter 37. Thus the word counter 37 is incremented each time a correct or incorrect synchronizing word appears or is detected.

The count output of the block 37 is applied to a decision block 38 which determines when five synchronizing words (including the initial synchronizing word) have been received. As long as less than five synchronizing words (including correct and incorrect) have been received, the decision block 38 keeps the block 34 waiting for synchronizing and message words. When five synchronizing words (including correct and incorrect) have been received, a block 39 opens the output gate 18. A decision block 40 determines whether three of these five words are correct. If not, the arrangement is restarted to look for an initial synchronizing word on a bit by bit comparison. If three words are correct, an in-synchronization signal is sent by the block 41 to the output gate 18 of FIG. 2. If the decision block 42 indicates the gate 18 is open, the in-synchronization signal is applied to a block 43 to decode the message words. After this decoding, the circuit is restarted to look for another message.

It will thus be seen that we have provided an improved word synchronizing circuit which operates to provide word synchronization in response to a first good synchronizing word detection, followed by two additional good synchronizing word detections during the next four synchronizing word positions. And while we contemplate that the synchronizing words are equally spaced in time, this may not be necessary in some applications. With our synchronizing arrangement operating with the data message of FIG. 1, we have found that with a bit error rate of 0.05, our synchronizing arrangement produces a correct in-synchronization output signal for 69.2% of the time, and with an error or false indication of an in-synchronization condition only once every 39.8 hours.

While the arrangement shown in the FIGURES and described is our preferred embodiment, persons skilled in the art will appreciate that modifications may be made. Therefore, while our invention has been described with reference to a particular embodiment, it is to be understood that modifications, particularly in terms of circuit implementation, may be made without departing from the spirit of the invention or from the scope of the claims.