Detecting Accurrences of Redundant Digital Codewords

The invention relates to detection of redundant digital codewords repeatedly transmitted over a digital transmission system, (including analog links using modems or the like), for example digital radio and telephone systems.

Various digital codeword detectors and detection schemes are known in the art. One technique involves scanning for N consecutive identical codewords. For example, if the codeword is 8 bits long, then all 8 bits of a first codeword must identically match all 8 bits of the second codeword. If successful, then the third codeword is tested for an identical match of all 8 bits, and so on up to N codewords.

Another detection technique involves scanning for N consecutive occurrences of grouped majority vote equal values for all bit-positions of the codeword. For example, a first group of five codewords is tested for each bit-position. In the first bit-position of each of the five codewords, a majority vote determines whether a one or a zero will be assigned to the first bit-position in a trial codeword, i.e., a three out of five majority vote in the first bit-position of the five codewords determines the first bit-position value in the trial codeword. A majority vote is then taken of the values in the second bit-positions in the five codewords, which three out of five majority vote determines the value of the second bit-position in the trial codeword. If the codeword is 8 bits long, then this process continues until all 8 bit-positions have been tested and an 8 bit trial word has been generated. A new group of five more codewords is then tested in like manner to generate a second trial word. If this second trial word is identical to the first trial word, then a third group of five codewords is tested, and so on until N consecutive identical trial words have been generated.

The present invention provides an improved digital codeword detection system, characterized by its simplicity and efficiency.

Corresponding bit-positions for consecutive codewords are checked, counting the number of ones and zeros for each bit-position. When there are at least J.sub.M equal bit values (ones or zeros) for all n bit-positions of the codeword, in M or less consecutive codewords, the detection process is complete.

Received data containing the codewords is stored in memory having a capacity of at least n.times.M. Every n.sup.th bit is read from the memory, preferably starting with one of the bits of the most recent codeword. Two different counters count the ones and zeros in this sequence of M bits, and the two counts are compared with the preset value J.sub.M. If either counter equals or exceeds J.sub.M, the outputs of comparators provide both a bit detected signal and a bit value signal. The bit detected signal is stored in a memory having a capacity of at least n bits, and the bit value signal is stored in a memory having a capacity of at least n bits.

The sequence is repeated for another set of M bits by reading every n.sup.th bit from the first memory starting with another of the bits of the most recent codeword. After all n bit-positions have been checked, the bit detected memory yields a codeword detected signal if a bit detected signal has been received for each of the n bit-positions. The bit value memory yields a codeword value provided by the values in the n bit-positions therein.

FIG. 1 is a schematic circuit diagram of a digital codeword detector constructed in accordance with the invention.

FIG. 2 is a schematic circuit diagram of the count and compare logic of FIG. 1.

FIG. 1 shows a digital codeword detector generally designated 10. Data from transmission line 12 is received by a receive unit 14. This receive unit is known in the art, and will only be briefly described. A clock recovery circuit 16, such as a phase locked loop, extracts the clock signals from the data. These clock signals are delivered to a retime circuit 18, such as a retime flip-flop, to retime or synchronize the data to the recovered clock. The extracted clock signals from circuit 16 are also delivered to a state controller 20 which outputs framing configuration and bit sequencing identification on bus 22. The extracted clock signals from circuit 16 are also delivered on output clock line 24. Buses 22 and 24 are connected to the remaining circuitry, to be described, for bit sequencing and clocking.

The data on line 12 may be either serial or parallel. In some applications involving high speed serial or parallel data on transmission line 12, a demultiplexing unit, not shown, may be provided at the output of circuit 18 to output a plurality of parallel data channels as controlled and timed by the bit sequencing and framing configuration identification from state controller 20. The data output on bus 26 may be serial or parallel.

Data from receive unit 14 is stored in a codeword memory 28 having a capacity of n.times.M, where n is the number of bits in a codeword and M is a number of consecutive codewords in a given framing format or configuration. The framing configuration identification output on bus 22 from state controller 20 provides group synchronization signals, and provides word synchronization signals for noncyclic codes. These synchronization signals control bit sequencing for identifying the codeword bit-positions of the received group of data bits, and control entry into memory 28. The codeword bit-positions are either absolute (for noncyclic codes) or relative to an arbitrarily chosen start of a codeword (cyclic codes). Codeword memory 28 is any form of storage which can be accessed for storage and retrieval of data, e.g., shift register, random access memory, etc.

Read logic 30 reads every n.sup.th bit from memory 28 starting with one of the bits of the most recent codeword as designated by the bit sequencing control on bus 22 from state controller 20. Read logic 30 transfers these data bits to count and compare logic 32. Read logic 30 reads the value of the same bit-position for successive, and successively older, codewords. This read process continues until M bits have been read or until the count and compare logic 32 signals that it has made a positive determination of the bit value, whichever comes first. Read logic 30 then reads every n.sup.th bit from memory 28 starting with another bit of the most recent codeword as controlled by the bit sequencing configuration on bus 22. In the same manner, the read process is repeated for all n bit-positions of the codewords.

Count and compare logic 32 determines the number of ones and zeros in each sequence of bits received from memory 28 and compares these numbers to a preset threshold value J.sub.M, designated 34. When the number of ones or zeros equals or exceeds J.sub.M, a bit detected signal 36 is generated which is fed back to read logic 30 to terminate the read process. The bit detected signal 36 is also sent to a bit detected memory 38 having a capacity of at least n bits, which keeps track of the number of detected bits in the codeword. Count and compare logic 32 also transmits a bit value signal 40 to a bit value memory 42 having a capacity of at least n bits, which saves the values of the different bit-positions of the codeword. The bit-positions for the detected bit values are determined by the bit sequencing configuration from bus 22 of state controller 20. Read logic 30 and count and compare logic 32 may be replicated to allow for sufficient processing power, i.e., parallel processing, if needed for sufficiently fast processing of the bit-positions in the codewords. When all bits of the codeword have been detected, a codeword detected signal 44 is generated by bit detected memory 38. Bit value memory 42 yields the codeword value on bus 46.

FIG. 2 shows count and compare logic 32 of FIG. 1. Data codeword bits on line 31 from read logic 30 are delivered to separate counters 48 and 50. Counter 48 is incremented by each bit having a value of one, and is thus a ones counter. Counter 50 receives the data bits through an inverter 52 such that counter 50 is incremented by bit values of zero on line 31, and hence counter 50 is a zeros counter. The number of ones counted by counter 48 is delivered to a comparator 52 which compares the ones count against the preset threshold number J.sub.M. If the number of ones exceed J.sub.M, then a high signal is generated at output 54. The number of zeros counted by counter 50 is delivered to a comparator 56 which compares this count against J.sub.M and outputs a high signal at 58 if the zeros count exceeds J.sub.M.

Outputs 54 and 58 are input to an OR gate 60 which yields bit detected signal 36 of FIG. 1 if either comparator 52 or 56 goes high. J.sub.M is usually chosen to be a fairly high percentage of M, depending on the degree of detection confidence desired. If output 54 goes high, the bit value for that bit-position is one, and output 54 provides bit value signal 40 of FIG. 1. If output 58 goes high, the bit value for that bit-position is zero, and output 54 is low to thus provide bit value signal 40 as a zero. Counters 48 and 50 are reset to 0 by the bit sequencing control on bus 22 when the count and compare logic starts processing a new bit-position.

The invention includes the method for detecting redundant digital codewords repeatedly transmitted over a digital transmission system, namely: reading a given bit-position of each of M codewords; counting the values of the M bit-positions; comparing this count against a predetermined threshold J.sub.M and outputting a bit value signal and a bit detected signal when the count equals or exceeds J.sub.M ; and repeating this sequence of steps for each of the remaining bit-positions in the codewords. Ones and zeros are separately counted for the M bit-positions, and the ones count and the zeros count are separately compared against the same J.sub.M. The outputs of the comparisons are ORed to provide the bit detected signal. The bit value signal is provided by the output of one of the comparisons.

In the preferred method, a group of M codewords are stored in codeword memory 28 having a bit capacity of at least n.times.M, where n is the number of bits in a codeword. Every n.sup.th bit is read from memory 28 starting with a given bit. The ones and zeros in the M bits are counted and compared against J.sub.M. If either count equals or exceeds J.sub.M then the bit value and bit detected signals are generated. The bit value signal is stored in a memory having a capacity of at least n bits, and the bit detected signal is stored in a memory having a capacity of at least n bits. These steps are repeated for each of the remaining of the n bit-positions in the codewords. A codeword detected signal is generated from the bit detected signal memory if the latter reaches a content of n bits. A codeword value signal is provided by the bit value signal memory.

Memory 28 is initially filled with M codewords. If this group of M codewords does not provide n detections, i.e., there are less than n bit detected signals as evidenced by memory 38 having a content less than n, then memory 28 is updated with one new codeword and the oldest codeword is discarded or written over. Data may be written to memory 28 one bit at a time (n entries make up a codeword) or several bits at a time if the data is received on parallel circuits or is demultiplexed into parallel circuits. If memory 28 is updated bit by bit, the respective bit-position of the codeword is checked as soon as it is written to memory 28 and the comparison is finished in time to start processing the next bit position as soon as the next bit is written to memory 28. The oldest bit in memory 28 is discarded or overwritten. If memory 28 is updated word by word, the comparison is started with any of the bit-positions and the processing of all n bit-positions is completed before the next word is stored in memory 28.

It is recognized that various modifications are possible within the scope of the appended claims.