Transistor Constant Bias Circuits

The present invention concerns improvements in or relating to bias circuits, notably circuits that will provide constant bias current and will operate from a low supply voltage--e.g. a supply voltage of the order 0.9 volts.

When designing circuits, the need often arises to generate a supply-independent current bias. A known design of bias circuit is shown in FIG. 1. The arrangement is that described in United Kingdom Patent Application GB No. 2007055. The circuit shown comprises a bias transistor T1, the collector load of which includes a pair of resistors R1, R2, which latter serve as a voltage/current divider. Feedback voltage/current is taken from the junction of the pair of resistors R1, R2 and is applied to the base of the bias transistor T1. The voltage/current, at the collector output of the bias transistor T1, is referred to the base of a drive transistor T2.

The first resistor R1 is connected to the supply voltage rail Vs, and the emitters of the two transistors T1, T2, both NPN type bipolar transistors, are connected to circuit earth. The drive transistor T2 serves thus as a current sink. This bias circuit has a peaked current versus supply voltage characteristic, the characteristic C1 shown in FIG. 3. For practical purposes this bias circuit thus provides current that is reasonably constant over a limited range of supply voltage in the region of the characteristic maximum. The resistor values are chosen so that the range of supply voltage matches the working range of the circuit application, but because of the peaked nature of the characteristic the working range is necessarily much restricted, and applications therefore severely limited. The current value may be scaled by appropriate choice of the ratio of transistor emitter areas.

The PNP inverse of the above circuit is also known, and may be employed as a current source.

To provide current constancy over a wider range of supply voltage, it is also known to cascade the NPN bias circuit and its PNP inverse as shown in FIG. 2. See also the article entitled "Optimum Design of Two Cascaded Peaking Current Sources" by V. Gheorgiu et al., IEEE Journal of Solid-State Circuits, Vol SC-16 No. 4 August 1981 pages 415-417, in which cascading is described. The circuit of figure comprises a PNP bias circuit including a bias transistor T1', a pair of collector load and base feedback resistors R1', R2' and a drive transistor T2'. This circuit is cascaded to the NPN circuit of FIG. 1 just described, the drive transistor T2' replacing the first resistor R1. This circuit has a twin-peaked characteristic--characteristic C2 shown in FIG. 3. Although this has an improved response, the peaking can be most pronounced when the circuit is overcompensated, and great care therefore must be taken in selecting the circuit components.

The present invention is intended to provide a bias circuit capable of operation at low supply voltage--e.g. a supply voltage of the order 0.9 volts--and of supplying bias current reasonably constant in value independent of supply voltage and transistor parameters.

According to the present invention thus there is provided a bias circuit comprising:

an NPN type bipolar bias transistor;

a resistor, in the collector path of the bias transistor, connected to apply feedback to the base of the

bias transistor; and,

an NPN-type bipolar drive transistor, the base of which is connected to the collector of the bias transistor;

Characterised by:

the PNP-type inverse of the aforesaid transistor-resistor-transistor circuit connected therewith in a ring configuration; and,

a start-up current bias circuit connected to a point in the ring configuration.

In the circuit aforesaid, once current flow is established by the start-up circuit, current constancy is maintained by feedback in the ring. The output current may be taken from any suitable point in the ring.

It is convenient to adopt as start-up circuit, a circuit comprising: a bias transistor; a pair of resistors, in the collector path of the bias transistor, and connected to apply feedback to the base of the bias transistor; and, a drive transistor, the base of which is connected to the collector of the start-up bias transistor, the collector of which is connected to the point in the ring configuration. The start-up transistors may be NPN-type, for example, and may be connected thus to the collector of the NPN drive transistor of the bias circuit.

In the drawings accompanying this specification:

FIGS. 1 and 2 are circuit diagrams for two known types of bias circuit;

FIG. 3 is a graph showing the current-voltage characteristics of the two circuits shown in the preceding FIGS. 1 and 2; and,

FIG. 4 is a circuit diagram for a bias circuit modified in accord with this invention.

So that this invention may be better understood, an embodiment thereof will now be described and particular reference will be made to FIG. 4 of the drawings. The description that follows is given by way of example only.

In the circuit shown FIG. 4 a first bias transistor T1 has a feedback resistor R2 in its collector path, and the base of a first drive transistor T2 is connected to the collector output of the first bias transistor T1. Both these transistors are of NPN bipolar type and the end of the resistor R2 furthest from the collector is connected to the base of the first bias transistor to provide feedback. These components, which together form a first peaking current bias sub-circuit, are combined with a second peaking current bias sub-circuit, the PNP inverse of the first. This latter thus comprises a pair of PNP-type bipolar transistors, namely a second bias transistor T1' and a second drive transistor T2', the base of the latter T2' being connected to the collector output of the former T1' and a second resistor R2' being included in the collector path of the second bias transistor T1' and connected to the base of this transistor for feedback. The two peaking current bias sub-circuits are connected together in a ring configuration, the drive transistors T2, T2', in each case, being connected in the collector path of the bias transistors T1', T1, respectively, of the other sub-circuit. The combination thus far described will reject variation in supply voltage. However, initially, no transistor will be conducting and it is necessary to inject or extract current to initiate operation. Any suitable start-up circuit may be used for this purpose. It is convenient however to use a peaking current bias circuit of a somewhat similar construction to the first mentioned sub-circuit, this start-up circuit comprising a third bias transistor T1" and a third drive transistor T2" the base of which is connected to the collector of the third bias transistor T1" and the collector of which is connected to a point in the ring configuration--eg. to the collector of the first drive transistor T2, as shown. The collector path of the third transistor T1" includes a pair of third resistors R1", R2" which are connected in series between the collector and the supply rail Vs. Feedback is taken from the junction of these two resistors R1", R2" and applied to the base of the third bias transistor T1". A feature of the start-up circuit is that the value of the intermediate resistor R2" is inordinately high and such therefore that the characteristic of this start-up circuit peaks sharply and at very low supply voltage.

This start-up circuit will thus provide a current peak as the supply voltage increases at start-up and no appreciable current loading thereafter as the supply voltage attains normal operating value. Once current is injected into the ring configuration the sub-circuit transistors each turn on and because of feedback in the ring will thereafter maintain current appreciably constant irrespecitve of subsequent variation in supply voltage and transistor parameters.

Typical component values are presented in the table appearing below:

The intended application for the above described circuits is to integrated circuit design for Radio Paging Receivers. The circuit design for such devices is not straight forward due to low battery voltage requirements (end life 0.9 v) and low current consumption. However, the invention will find application to other low supply, low current circuits.