Current Stabilizing Arrangement

The invention relates to a current stabilizing arrangement.

For various purposes current sources are required which provide an accurately adjustable constant current. Such a current source may for example be used as the power supply for an oscillator circuit which produces a signal of constant frequency. Such current sources are also employed in accurate digital-analog converters. To realize a constant current it is a prerequisite that the current source should be independent of temperature variations.

Current sources are known in a multitude of embodiments. Some of these comprise means for eliminating errors caused by temperature variations.

To obtain a high degree of temperature independence the supply voltage in the known current sources should comply with stringent requirements in respect of constancy and temperature independence or use must be made of constant temperature-independent reference voltages or currents (see for example U.S. Patent No. 3,573,504).

It is an object of the invention to realize an adjustable current source which is temperature independent to a high degree, while no stringent requirements have to be imposed on the constancy of the supply voltage and no reference voltage or current is required, with the additional advantage that the arrangement can be realized comparatively simply in the form of a monolithic integrated circuit.

For this, the invention is characterized in that the arrangement includes

A THREE-TERMINAL CIRCUIT, KNOWN PER SE, COMPRISING TWO PARALLEL BRANCHES BETWEEN AN INPUT TERMINAL AND A COMMON TERMINAL, OF WHICH ONE BRANCH INCLUDES AT LEAST THE COLLECTOR-EMITTER PATH OF A FIRST TRANSISTOR AND THE OTHER BRANCH AT LEAST THE BASE-EMITTER JUNCTION OF A SECOND TRANSISTOR IN SERIES WITH A RESISTOR, THE COLLECTOR OF THE SECOND TRANSISTOR BEING CONNECTED TO AN OUTPUT TERMINAL AND THE BASE OF THE FIRST TRANSISTOR BEING DRIVEN WITH A SIGNAL WHICH IS DERIVED FROM THE INPUT SIGNAL IN SUCH A WAY THAT FOR A CONSTANT CURRENT AT THE INPUT TERMINAL A CURRENT WITH A NEGATIVE TEMPERATURE COEFFICIENT APPEARS AT THE OUTPUT TERMINAL,

A TWO-TERMINAL CIRCUIT, KNOWN PER SE, WHICH COMPRISES TWO PARALLEL BRANCHES, WHICH BY MEANS OF A CURRENT DIVIDING CIRCUIT ARE COUPLED IN SUCH A WAY THAT THE CURRENTS WHICH FLOW THROUGH THE TWO BRANCHES ARE IN A FIXED RATIO TO ONE ANOTHER, WHILE AT LEAST ONE SEMICONDUCTOR JUNCTION WHICH IS INCLUDED IN THE ONE BRANCH IS BY-PASSED BY A SERIES CONNECTION OF AT LEAST ONE SEMICONDUCTOR JUNCTION AND A RESISTOR WHICH IS INCLUDED IN THE OTHER BRANCH, AT LEAST ONE OF THE TWO SAID SEMICONDUCTOR JUNCTIONS BEING THE BASE-EMITTER JUNCTION OF A TRANSISTOR, IN SUCH A MANNER THAT BETWEEN THE TERMINALS OF SAID TWO-TERMINAL CIRCUIT A CURRENT WITH A POSITIVE TEMPERATURE COEFFICIENT APPEARS,

A CURRENT MIRROR CIRCUIT, KNOWN PER SE, WHOSE INPUT TERMINAL IS CONNECTED TO THE OUTPUT TERMINAL OF SAID THREE-TERMINAL CIRCUIT AND ALSO TO THE ONE TERMINAL OF THE SAID TWO-TERMINAL CIRCUIT, WHOSE OTHER TERMINAL IS CONNECTED TO THE COMMON TERMINAL OF SAID THREE-TERMINAL CIRCUIT, THE OUTPUT TERMINAL OF SAID CURRENT MIRROR CIRCUIT BEING CONNECTED TO THE INPUT TERMINAL OF THE THREE-TERMINAL CIRCUIT.

To compensate for higher-order temperature errors, according to a further aspect of the invention, the arrangement may comprise a squaring circuit to which at least a current which is proportional to the current which flows between the terminals of said two-terminal circuit is applied. The squaring circuit has an output circuit in which a current flows which is proportional to the sqaure of the current which flows through said two-terminal circuit. This output circuit connects the input terminal of the first current mirror circuit to the common terminal of said three-terminal circuit.

The invention will be described in more detail with reference to the Figures, of which:

FIG. 1 shows a current source, known per se,

FIG. 2 shows a second current source, known per se,

FIG. 3 schematically shows a first embodiment of an arrangement according to the invention,

FIG. 4 shows a multiplying circuit, known per se,

FIG. 5 schematically shows a second embodiment of an arrangement according to the invention, and

FIG. 6 shows a detailed embodiment of an arrangement according to the invention.

FIG. 1 shows a known current source arrangement which provides a current with a negative temperature coefficient. The circuit arrangement has an input terminal A, an output terminal A', and a common terminal B. A first current path, which is formed between the terminals A and B, comprises the collector-emitter path of a transistor T.sub.1, which in the shown example is of the npn-type. A second current path is formed between the terminals A' and B and comprises the collector-emitter path of a transistor T.sub.2, of the same conductivity type as the transistor T.sub.1, in series with a resistor R.sub.1. The base of transistor T.sub.1 is connected to the emitter of transistor T.sub.2 and thus to one end of the resistor R.sub.1, the other end being is connected to the common terminal B. The emitter of transistor T.sub.1 is also connected to the terminal B so that the resistor R.sub.1 shunts the base-emitter junction of transistor T.sub.1. The collector of transistor T.sub.1 is connected to the input terminal A, while the collector of transistor T.sub.2 is connected to the output terminal A'.

It is assumed that a constant current I.sub.c flows through the terminal A. Through the terminal A' a current I.sub.1 flows. When the currents I.sub.1 and I.sub.c are of the same order of magnitude, the base currents of the transistors T.sub.1 and T.sub.2 will be approximately equal, provided that the effective emitter areas of the transistors T.sub.1 and T.sub.2 are equal. The current which flows through the resistor R.sub.1 is then equal to the current I.sub.1, which will be evident when the direction of the base currents as shown in FIG. 1 is considered. The current I.sub.1 causes a voltage drop I.sub.1 R.sub.1 across the resistor R.sub.1. Said voltage drop is in shunt with the base-emitter junction of transistor T.sub.1, and thus equals the base-emitter voltage V.sub.be of transistor T.sub.1. Expressed in a formula this becomes: ##EQU1## For V.sub.be the known expression is valid: ##EQU2## where k is the Boltzmann constant,

T the absolute temperature of transistor T.sub.1,

q the charge of the electron and

I.sub.c the collector current of transistor T.sub.1,

i.sub.o the leakage current of the transistor

when operated in the reverse direction. The current I.sub.o is also temperature dependent, which temperature dependence may be expressed as: ##EQU3## in which n.sub.i.sup.2 = BT.sup.3 e.sup..sup.-qV go.sup./kT

.mu..sub.n = CT.sup..sup.-n

where A, B and C are constants, .mu..sub.n the electron mobility and V.sub.go the linearly extrapolated gap voltage at 0.degree. K (see for example "Physics of Semiconductor Devices", by S. M. Sze, page 27, 39, 41, 269). When I.sub.c /I.sub.o is substantially greater than one and with the substitutions D = A.B.C and .eta..sub.i = 4 -n, the following equation applies to the base-emitter voltage of transistor T.sub.1 : ##EQU4## The logarithm of the temperature can be developed around a reference temperature T.sub.o in a Taylor series. Assume that ##EQU5## V.sub.beo = V.sub.be (T = T.sub.o) and I.sub.c is temperature independent; expression (4) when neglecting components with a temperature dependence of a higher order than T.sup.2 may be written as: ##EQU6## At increasing temperature it is found that the base-emitter voltage of transistor T.sub.1 decreases, so that the current I.sub.1, which flows through the output terminal A', decreases. For I.sub.1 as a function of temperature the following equation applies, using the expressions (1) and (5): ##EQU7## in which a and b are positive constants. The current I.sub.1 which flows through the output terminal A' consequently has a negative temperature coefficient.

FIG. 2 shows a known current source, which provides a current with a positive temperature coefficient. The circuit arrangement includes a current mirror with identical transistors, in the shown example of the npn-type, which current mirror circuit has three terminals, namely a sum terminal C and two terminals D and D'. The sum terminal C is connected to the emitters of the transistors T.sub.3 and T.sub.4, while the base of transistor T.sub.3 is connected to the base of transistor T.sub.4. The transistor T.sub.4 operates as a diode in that the base and the collector are interconnected. The collector of transistor T.sub.3 is connected to the terminal D so that the emitter-collector path of transistor T.sub.3 constitutes a first current path between the terminals C and D. Similarly, the collector-emitter path of the transistor T.sub.4 constitutes a second current path between the terminals C and D'.

The current source further includes a second circuit which has three terminals, viz. the terminals E and E' and a sum terminal C'. The terminals E and E' are connected to the terminals D and D' of the current mirror circuit respectively. The second circuit comprises identical transistors of a conductivity type which is opposite to that of the transistors of the current mirror circuit. The collector-emitter path of a transistor T.sub.5 connects the terminals E and C', the emitter of transistor T.sub.5 being connected to the terminal C'. The transistor T.sub.5 is connected as a diode by means of the collector-base connection. The terminal E' is connected to the sum terminal C' via the parallel-connected collector-emitter paths of a number of a transistors T.sub.6, n resistor R.sub.2 being included in the common emitter circuit. Said number of n transistors may be replaced by one transistor having an n-fold effective emitter area. The common base circuit of the transistors T.sub.6 is connected to the base of transistor T.sub.5.

When the base currents are initially neglected, the current which flows through each of the terminals D and D' will equal half the current I.sub.2 which flows through the sum terminal C because the base-emitter junctions of the transistors T.sub.3 and T.sub.4 are connected in parallel. The current 1/2I.sub.2 which flows through the collector-emitter path of transistor T.sub.5 causes a base-emitter voltage which equals: ##EQU8## The current 1/2I.sub.2, which flows between the terminals E' and C' , is equally distributed among the n identical transistors so that the base-emitter voltage of each of said transistors equals: ##EQU9## The current 1/2I.sub.2 moreover causes a voltage drop which equals 1/2I.sub.2 R.sub.2 across the resistor R.sub.2. The base-emitter voltage of transistor T.sub.5 should equal the sum of the base-emitter voltage of one of the n transistors T.sub.6 and the voltage drop across the resistor R.sub.2, so that some calculations will yield the current I.sub.2 : ##EQU10## Starting from the reference temperature T.sub.o, the following may be assumed in respect of the temperature dependence of I.sub.2 : ##EQU11## with ##EQU12## In expression (5) c is a positive constant so that I.sub.2 (T) has a positive temperature coefficient. By means of the current I.sub.2 the first order temperature dependence of the current I.sub.1 (T) of the current source of FIG. 1 can be compensated by equalizing the constant c and the constant a with the aid of the resistors R.sub.1 and R.sub.2. Then, only the constant current I.sub.c is to be provided yet. If the second-order dependence of I.sub.1 (T) is neglected, said current can be derived from the current I.sub.1 (T) + I.sub.2 (T), which is now constant, with the aid of a current mirror circuit.

FIG. 3 is a schematic representation of a circuit arrangement which, in a first-order approximation, provides a temperature independent current. The arrangement includes a current mirror circuit which consists of the identical transistors T.sub.7, T.sub.8 and T.sub.9, which in the shown example are of the pnp-type. The emitters of the three said transistors are connected to a sum terminal F, while the collector of transistor T.sub.7 is connected to an output terminal G and the collectors of the transistors T.sub.8 and T.sub.9 to an input terminal G'. The transistors T.sub.8 and T.sub.9 are again connected as diodes, the bases of the transistors T.sub.8 and T.sub.9 being connected to the base of transistor T.sub.7. The arrangement further comprises the current sources of FIG. 1 and FIG. 2, whose terminals are designated correspondingly. The terminal A of the first current source circuit is connected to the terminal G, while the terminal A' is connected to the terminal G'. The terminal C of the second current source circuit is connected to the terminal G', while the terminal C' is connected to the terminal B.

The current mirror circuit in the present example provides a current I.sub.c which equals 1/2(I.sub.1 +I.sub.2). The ratio 1:2 has been selected for the current mirror so as to enable a current I.sub.1 of the same order of magnitude as the current I.sub.c to be realized. As the base-emitter junctions of the transistors T.sub.7, T.sub.8 and T.sub.9 are connected in parallel, the currents through the collector circuits of the transistors T.sub.7, T.sub.8 and T.sub.9 will be equal. As the transistors T.sub.8 and T.sub.9 have a common collector circuit, the current which flows through the terminal G equals half the current which flows through the terminal G'. Said last-mentioned current divides into the currents I.sub.1 and I.sub.2, the current which flows through the terminal G being equal to I.sub.c. The currents I.sub.1 and I.sub.2 are determined by the expressions (6) and (8) respectively. The sum of the currents I.sub.1 and I.sub.2 in a first-order approximation is temperature independent if a = c. The expressions (6) and (8) yield the condition: ##EQU13## In this case the sum of the currents I.sub.1 (T) and I.sub.2 (T) is: ##EQU14## Substitution of (9) in (19) yields: ##EQU15##

When condition (9) is satisfied the sum of the currents I.sub.1 (T) and I.sub.2 (T), which sum flows through the terminal G', appears to be temperature independent in a first-order approximation. Adjustment of the circuit arrangement of FIG. 3 is simple and is effected as follows:

With the aid of expression (11) the value of the resistor R.sub.1 is determined for the desired value of the sum current I.sub.1 (T) + I.sub.2 (T). The resistor R.sub.2 dictates the value of the current I.sub.2 (T) and thus the value of the sum current. When R.sub.2 is subsequently adjusted until the sum current has reached the desired value, condition (9) is automatically satisfied, since condition (9) has resulted in the equation (11), which equation determined the value of the resistor R.sub.1.

To compensate for the second-order temperature dependence of I.sub.1 (T), use can be made of the circuit arrangement of FIG. 4.

FIG. 4 shows a squaring circuit, which consists of four identical transistors T.sub.10, T.sub.11, T.sub.12 and T.sub.13, which in the present example are of the npn-type. The circuit has three terminals H, K and J, which are connected to the collectors of the transistors T.sub.10, T.sub.11 and T.sub.12 respectively. A terminal K' is connected to the emitter of transistor T.sub.11 and a terminal L is connected to the emitters of the transistors T.sub.10 and T.sub.13. The transistors are arranged so that the base-emitter junctions of the transistors are connected in series and in series-opposition respectively to form a closed loop. The base of transistor T.sub.10 is connected to the emitter of transistor T.sub.11, the base of transistor T.sub.11 is connected to the base of transistor T.sub.12, which transistor is connected as a diode, and the emitter of transistor T.sub.12 is connected to the base of transistor T.sub.13 which also is connected as a diode.

From the circuit arrangement of FIG. 4 it can be inferred that the sum of the emitter-base voltages of the transistors T.sub.11 and T.sub.12 should equal the sum of the base emitter voltages of the transistors T.sub.12 and T.sub.13. As is indicated in the Figure, it is assumed that in the collector circuit of transistor T.sub.10 a current I.sub.3 flows, in the collector circuit of transistor T.sub.1 a current I.sub.4, and in the collector circuit of transistor T.sub.12 a current I.sub.5. Using the known expression for the base-emitter voltage of a transistor, it follows that: ##EQU16## from which it follows for I.sub.3 that ##EQU17## The current I.sub.3 is given the desired dependence on the square of the temperature by selecting I.sub.5 proportional to I.sub.2 (T) and I.sub.4 proportional to the constant current I.sub.c, as is indicated in FIG. 5.

FIG. 5 shows a schematic representation of a circuit arrangement which realizes current which is temperature independent both in the first and in the second order. The arrangement consists of a first current source I in accordance with FIG. 1, a second current source II in accordance with FIG. 2, a squaring circuit III in accordance with FIG. 4, a first current mirror circuit IV, a second current mirror circuit V, and a third current mirror circuit VI. The terminals of the circuits I through IV are designated in accordance with FIGS. 1, 2 and 4. The output terminal G of current mirror circuit IV is connected to the input terminal A of current source circuit I and the input terminal G' to the output terminal A' of the current source circuit I, to the output terminal H of the squaring circuit III and to the terminal O of the current mirror circuit VI. Between the output terminal N of the current mirror circuit V and the common terminal B of the current circuit I at least the collector-emitter path of a transistor is included whose base-emitter junction is by-passed by the base-emitter junction of the transistor T.sub.1 of the first current source circuit, so that at the output terminal N a current appears which is proportional to the input current I.sub.c of the first current source circuit and which current is assumed to equal 1/p I.sub.c. The output terminal N is connected to the terminal K' of the squaring circuit, the terminal k being connected to the input terminal A of the current source circuit I. The current mirror circuit VI comprises two terminals P and P', which are respectively connected to the input terminal J of the squaring circuit III and the sum terminal C of the current source II. The common terminal B of the current source I is connected to the sum terminal C' of the current source II and the terminal L of the squaring circuit III.

The current mirror circuit V realizes a current I.sub.4, which bears a fixed ratio of 1:p to the current I.sub.c, and the current mirror circuit VI realizes in known manner two currents I.sub.5 and I.sub.2 in a ratio of 1:r. The currents I.sub.c, I.sub.4, I.sub.5 and I.sub.2, as well as the currents I.sub.1 and I.sub.3 correspond to the relevant currents in FIGS. 1 through 4. Substitution of I.sub.4 = 1/p I.sub.c and I.sub.5 = 1/r I.sub.2 in expression (13) yields the output current I.sub.3 of the squaring circuit: ##EQU18## When the expression (8) for the current I.sub.2 is substituted therein, it follows for the temperature dependent current I.sub.3 (T) that: ##EQU19## With ##EQU20## it follows that: ##EQU21## When the current mirror circuit IV realizes two equal currents, the total current I, which flows between terminals F and F', will be: ##EQU22## If said current is required to be temperature independent, the following should be valid (using expressions (6), (8) and (16)): ##EQU23## and ##EQU24## Substitution of (19) and (18) reduces this to: ##EQU25## The following then applies to the current I: ##EQU26## By adjustment of the resistors R.sub.1 and R.sub.2 and by a suitable choice of the values of p and r the equations (20), (21) and (22) can be satisfied. Since there are various modifications to the basic principle of FIG. 5, the solution of the equations (20), (21) and (22) can best be explained with reference to a detailed drawing of an embodiment of the arrangement according to FIG. 5.

FIG. 6 shows an embodiment of an arrangement according to the invention. The various circuits are designated in accordance with FIG. 5. The circuit arrangement moreover includes the circuits VII through IX. The input terminal F is connected to a current mirror circuit IV, which has an input terminal G' and an output terminal G. The circuit consists of four transistors T.sub.14, T.sub.15, T.sub.16 and T.sub.17, of which transistors T.sub.15 and T.sub.16 are connected as diodes. As the base-emitter junctions of T.sub.14 and T.sub.15 are connected in parallel, the circuit provides two equal currents between the terminals F and G' and between the terminals F and G. When the current which flows through the terminal F equals I, the currents flowing through the terminals G' and G will equal 1/2I. The circuit IV compensates for the base currents i.sub.b, as will appear from the Figure. The terminal G' is connected to the output terminal A' of the first current source I, the sum terminal C of the second current source II and the terminal H of the squaring circuit III, all via the collector-emitter path of a transistor T.sub.19 which forms part of the Darlington pair consisting of the transistors T.sub.18 and T.sub.19. Via an isolating circuit VIII and via the collector-emitter path of transistor T.sub.21, which forms part of a starting circuit IX, the terminal G is connected to the input terminal A of the first current source I. Between the output terminal A' and the common terminal B of the first current source circuit I is the series connection including the collector-emitter junctions of the transistors T.sub.26 and T.sub.28 and the resistor R.sub.1. Between the input terminal A and the common terminal B the series connection including the collector-emitter path of the transistor T.sub.27, the collector-emitter path of the transistor T.sub.29 which is connected as a diode, and the parallel-connected collector-emitter paths of the transistors T.sub.30 and T.sub.31. The resistor R.sub.1 by-passes the parallel-connected base-emitter junctions of the transistors T.sub.30 and T.sub.31. The transistors T.sub.30 and T.sub.31 together with the transistor T.sub.32 constitute the current mirror circuit V. The base-emitter junction of transistor T.sub.32 is connected in parallel with the base-emitter junction of the transistor T.sub.31. The collector of transistor T.sub.32 is connected to the output terminal N of the current mirror circuit V, which terminal N is connected to the terminal K' of the squaring circuit III, which is identical to the circuit of FIG. 4. The terminal K of the squaring circuit III is connected to the emitter of transistor T.sub.27. The input terminal J of the squaring circuit III is connected to the output terminal P of the current mirror circuit VI. The current mirror circuit VI is combined with the current mirror circuit which is associated with the second current source II, and is based on the same principle as the current mirror circuit VI. The current mirror circuit VI supplies four identical currents, each being a quarter of the current I.sub.2 which flows through the sum terminal C of current source circuit II. The starting circuit IX consists of a current mirror circuit which consists of the parallel-connected base-emitter junctions of the transistors T.sub.22, T.sub.24 and T.sub.25. The collector-emitter path of transistor T.sub.22 supplies the base current which flows into the base of transistor T.sub.21. The collector-emitter path of transistor T.sub.21 is included in the current path which connects the terminals G and A. The base of transistor T.sub.22 is connected to the emitter of transistor T.sub.21 via the transistor T.sub.23 which is connected as a diode. The emitters of the transistors T.sub.22, T.sub.24 and T.sub.25 are connected to the collector of transistor T.sub.21. The collector of transistor T.sub.24 is connected to the common base circuit of the transistors of the first stage of the current mirror circuit VI and the collector of transistor T.sub.25 is connected to the base of transistor T.sub.44. The isolating circuit VIII consists of the series-connected collector-emitter paths of the transistors T.sub.46 and T.sub.47 which are included in the current path between the terminal G and the starting circuit IX, the base-emitter junction of transistor T.sub.46 being by-passed by the transistor T.sub.45 which is connected as a diode. The collector-emitter path of transistor T.sub.46 is by-passed by the series-connected emitter-base paths of the transistors T.sub.48 and T.sub.49, the transistor T.sub.48 being connected as a diode and the collector of transistor T.sub.49 being connected to the base of transistor T.sub.47. The base of transistor T.sub.46 is connected to the emitter of the transistor T20 which is connected as a diode and which is included in the current path between the terminal G' and the Darlington circuit VII. The collector-emitter junctions of the transistors T.sub.18 and T.sub.49 are by-passed by the diodes D.sub.1 and D.sub.3, which are connected in the reverse direction in order to prevent oscillations. Similarly, a diode D.sub.2 is included between the collector of T.sub.17 and the base of T.sub.20. The second current source circuit II is a modified version of the current source circuit of FIG. 2, with the proviso that the current mirror circuit consists of two stages and that the current path between the sum terminal C and the resistor R is duplicated. The transistors T.sub.42 and T.sub.43 are provided in n-fold, i.e. each of the transistors T.sub.42 and T.sub.43 consists of a number of n identical transistors whose emitters, collectors and bases are interconnected. The transistors T.sub.42 and T.sub.43 may alternatively consist of single transistors with n-fold effective emitter areas.

The current mirror circuit IV divides the desired current I which flows through the terminal F into two equal currents 1/2I, which flow through the terminals G and G'. The current 1/2I, which flows between the terminals G' and A', is divided into the currents I.sub.1, I.sub.2 and I.sub.3, which currents are respectively applied to the terminal A' of the current source I, the terminal C of the current source II, and the terminal H of the squaring circuit III. Hence, the first equation is:

the current 1/2I, which flows between the terminals G and A, is equally distributed among the collector-emitter paths of the transistors T.sub.30, T.sub.31 and T.sub.32 of the current mirror circuit V. As a result, the current through the input terminal K of the squaring circuit III is 1/6 I. The current through the collector-emitter path of transistor T.sub.30 is also 1/6 I. The current I.sub.1 flows through the resistor R.sub.1. As the resistor R.sub.1 by-passes the base-emitter junction of transistor T.sub.30, the following will apply to I.sub.1 : ##EQU27## Expressions (4) and (5) are valid for V.sub.be, with I.sub.c = 1/6 I. The current I.sub.2 is divided into four equal parts by the current mirror circuit VI, so that a current 1/4I.sub.2 will flow through the input terminal J of the multiplying circuit III. In a similar way as for expression (13) it follows for I.sub.3 : ##EQU28## As the transistors T.sub.42 and T.sub.43 of current source II are provided in n-fold, a current of 1/4.sub.n - I.sub.2 will flow through the collector-emitter path of each of the transistors T.sub.42 and T.sub.43. A current of 1/2I.sub.2 will then flow through the resistor R.sub.2. In a similar way as expression (7) has been derived, it follows for I.sub.2 : ##EQU29## in which in the present embodiment n = 3. Similarly to the expressions (6), (8) and (16) the temperature dependence of I.sub.1, I.sub.2 and I.sub.3 may be represented by the following equations: ##EQU30## with ##EQU31## and ##EQU32## For temperature compensation the following must apply:

or: ##EQU33## Substitution of (31) in (30) yields the system: ##EQU34## Under said condition (with expression (23)) the sum of the currents I.sub.1 + I.sub.2 + I.sub.3 becomes: ##EQU35## From expression (33) the value of the resistor R.sub.1 can be determined as a function of the desired current I: ##EQU36## Measurements conducted on transistors as employed in the previously discussed circuit arrangement have revealed that V.sub.go = 1.180 and .eta. = 3.125. For T.sub.o 293.degree. K is selected. Insertion of the various values in expression (34) yields: ##EQU37## To compensate for the first-order temperature dependence expression (32) must be satisfied. Expression (31) (second-order compensation) may be re-written as: ##EQU38## When the value of R.sub.1 (expression (34)) has been adjusted, expression (33) may be substituted in expression (36): ##EQU39## Expression (32) may be re-written as: ##EQU40## Combination of expressions (37) and (38) yields as the condition for second-order compensation: ##EQU41## Substitution of the values of V.sub.go, .eta. and V.sub.beo which apply for the transistors of this circuit arrangement, and substitution of kT.sub.o /q results in the value 0.38 for the right-hand term of equation (39). This is substantially equal to 6/16 so that the circuit arrangement of FIG. 6 provides compensation for second-order temperature errors.

Adjustment now proceeds very simply. Starting from the required current I the value of resistor R.sub.1 is determined with the aid of expression (35) and this resistor is adjusted accordingly. As the resistor R.sub.2 has not yet the desired value, the current which flows through the terminal F will not equal the desired current. The resistor R.sub.2 should now be adjusted so that the said current has the desired value. At that instant both condition (31) and condition (32) is satisfied. When varying R.sub.2 a point is reached at which condition (30) is satisfied. At said point condition (31) is also satisfied and the sum of the currents equals the desired value I.

The circuits VII and VIII serve to make the current I less dependent on the voltage which is applied between terminals F and F'. Between the terminals F' and R a voltage is available which equals the sum of the base-emitter voltages of the transistors T.sub.30, T.sub.28, T.sub.27, T.sub.26, T.sub.23 and T.sub.22, which sum voltage approximately equals 6V.sub.beo, and which voltage is constant at a constant I. Between the terminals F' and A' there is a voltage which is equal to the sum of the base-emitter voltages of said transistors minus the base-emitter voltages of the transistors T.sub.18 and T.sub.19. Between the terminals F and R' a voltage is available which equals the sum of the base-emitter voltages of the transistors T.sub.15, T.sub.17 and T.sub.20. Between the terminals F and G a voltage exists which equals the sum of the base-emitter voltages of the transistors T.sub.15, T.sub.17, T.sub.20 and T.sub.45 minus the base-emitter voltages of the transistors T.sub.48 and T.sub.49. At a constant current I the variations of the voltage between the terminals F and F' are imparted to the voltage between terminals R' and A' and the voltage between the terminals G and R. Since the circuits VII and VIII have a high impedance for voltage variations, the currents which flow through said circuits are hardly affected by the voltage variations of the supply voltage. The circuit VII consists of the known Darlington arrangement, while the circuit VIII comprises the series-connection of the transistors T.sub.46 and T.sub.47. The base current for the transistor T.sub.47 is supplied by the transistor T.sub.49. The impedance raising properties of such a circuit arrangement are known. Transistor T.sub.48 which is connected as a diode produces a voltage difference V.sub.be between the base of transistor T.sub.49 and the emitter of transistor T.sub.46. As the circuit VII has two stable states, namely the conducting and the non-conducting state, the transistor T.sub.45 which is connected as a diode by-passes the base-emitter junction of transistor T.sub.46 so as to force the transistor T.sub.46 into the conductive state. The transistor T.sub.20 which is connected as a diode by-passes the base-collector junction of transistor T.sub.46. The base-collector voltage of transistor T.sub.46 equals the sum of the base-emitter voltages of the transistors T.sub.48 and T.sub.49 minus the base-emitter voltage of transistor T.sub.46. The starting circuit IX realizes a current in the collector circuits of the transistors T.sub.24 and T.sub.25 which current equals the base current of transistor T.sub.21. The second current source circuit II also has the non-conductive state as the stable state. The starting circuit IX assumes the conductive state in that said circuit impresses the collector currents of the transistors T.sub.24 and T.sub.25 on the current source circuit II at the instant that the supply voltage is applied causing transistor T.sub.21 to conduct and draw a base current.

The circuit of FIG. 6 is compensated for the various base currents, as will be evident when the base currents in FIG. 6 are considered. The base current of transistor T.sub.14 is compensated by the base current of transistor T.sub.17. The base current of transistor T.sub.46 is compensated by one of the collector currents of the transistors T.sub.24 and T.sub.25. The base current of transistor T.sub.18, which forms part of the Darlington arrangement, in negligible. The current 1/2I is divided into two currents I.sub.1 and I.sub.2 at terminal A', which are of the same order of magnitude. More in particular, the current which flows through the terminal A' approximately equals half the current which flows through the terminal A. The base current of transistor T.sub.27 is thus compensated by the base currents of the transistors T.sub.26 and T.sub.28.

The sum of the currents which flow through the collector-emitter paths of the transistors T.sub.30, T.sub.31 and T.sub.32 equals the current which flows through the transistor T.sub.21. The sum of the base currents of the transistors T.sub.30, T.sub.31 and T.sub.32 is consequently compensated by one of the collector currents of the transistors T.sub.24 and T.sub.25. The sum of the base currents which flow between the current path which is formed between the terminals F, G', R', A' and F', and the current path which is formed between the terminals F, G, R, A and F' is consequently zero.

The extrapolation of V.sub.go in expression (3) applies to silicon transistors. For germanium transistors an expression can be derived which is similar to equation 6 in its general form, so that the invention is not limited to silicon transistors.

The circuit arrangement of FIG. 6, except for the resistors R.sub.1 and R.sub.2, consists of semiconductor elements so that the arrangement is highly suited to take the form of a monolithic integrated circuit.

The scope of the invention is not limited to the example of FIG. 6. Numerous modifications are possible in respect of the location and embodiment of the current mirror circuits and the impedance raising elements. For the described current source circuits and the squaring circuit, different types may be selected. For example, the transistor T.sub.1 of the first current source circuit may be connected as a diode. Furthermore, the current mirror circuits V or VI may be dispensed with if a different type of squaring circuit is employed. Moreover, all transistors may be replaced by transistors of an opposite conductivity type, the directions of the currents then being reversed.