Dot Matrix Panel Display Control

1. Field of the Invention

The present invention relates to a dot matrix display panel system and, more particularly, to a display control system which displays any desired portion of the image with increased magnification.

2. Description of the Prior Art

In a television video signal display panel or an electronic viewfinder, it is convenient when a desired image portion is displayed with increased magnification. Such a display system generally includes a dot matrix display panel having a plurality of picture elements aligned in a matrix fashion. The resolution, which determines the picture quality of the dot matrix display panel and the size of decipherable characters, depends on the number of the picture elements included in the dot matrix display panel.

When an image signal is constructed to be applied to a matrix display panel having 500 (H).times.240 (V) picture elements, one character is generally displayed by 8 (V).times.6 (H) dots (picture elements). If a small matrix display panel having 250 (H).times.120 (V) picture elements is employed to display the image signal, the scanning lines are thinned so that one character is displayed by 4 (V).times.3 (H) dots (picture elements). In this case some characters become indecipherable. Thus, it is preferable that a desired image portion is displayed with increased magnification so that one character included in the selected image portion is displayed by 8 (V).times.6 (H) dots as if the matrix display panel had 500 (H).times.240 (V) picture elements.

An image enlarging system in an electronic viewfinder having a dot matrix display panel is disclosed in copending U.S. patent application, "ELECTRONIC VIEWFINDER", Ser. No. 530,468, filed on Sept. 8, 1983 by Yasuo Torimaru and Masahiro Yoshimura, now U.S. Pat. No. 4,589,029 and assigned to the same assignee as the present application, wherein the shift signal for shifting the video signal has a pulse width corresponding to the degree of magnification, and synchronizing signals are delayed in accordance with the image portion to be magnified.

The display control system disclosed in the above-mentioned patent is effective to display a desired portion in an enlarged size. However, an external control signal must be applied to X and Y delay circuits to select the portion to be enlarged.

Accordingly, an object of the present invention is to provide a dot matrix display panel drive system which displays a desired portion of the image with increased magnification.

Another object of the present invention is to provide a dot matrix display panel drive system which displays a desired image portion with increased magnification, wherein the enlarged image portion is automatically shifted in a predetermined direction.

Other objects and further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

To achieve the above objects, pursuant to an embodiment of the present invention, an X delay period setting circuit and a Y delay period setting circuit are provided for automatically determining the X delay period and Y delay period which determine the image portion to be displayed with increased magnification. In a preferred form, the enlarged image portion is automatically shifted along the sentence displayed on the dot matrix display panel.

The present invention will be better understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein:

FIG. 1 is an equivalent circuit diagram of a matrix image display panel associated with an embodiment of a display control system of the present invention; and

FIG. 2 is a block diagram of an embodiment of a display control system of the present invention.

FIG. 1 is an equivalent circuit diagram of a dot matrix image display panel having picture elements arranged in a matrix of m rows and n columns. In FIG. 1, reference characters DX.sub.1 through DX.sub.m designate row scanning X shift registers, DY.sub.1 through DY.sub.n designate column scanning Y shift registers, S.sub.1 through S.sub.m designate X line selecting transistors, X.sub.1 through X.sub.m designate X lines, Y.sub.1 through Y.sub.n designate Y lines, and P.sub.11 through P.sub.mn designate picture elements in the matrix form. The picture elements P.sub.ij can be so-called "switch matrix type picture elements" having an active switch, or can be so-called "ordinary matrix type picture elements" having no active element. The display element can be an EL (Electroluminescent) element, a liquid crystal element, or a fluorescent display element.

The operation of the circuit of FIG. 1 will be described for the case of displaying a television image. When the Y.sub.1 line is selected by a Y shift signal synchronous with a vertical synchronizing signal, and the X.sub.1 line selecting transistor S.sub.1 is turned on by an X shift signal synchronous with a horizontal synchronizing signal, the picture element P.sub.11 is selected to emit light in accordance with the amplitude of a video signal. When one X shift clock pulse is applied to the row scanning X shift registers DX.sub.1 through DX.sub.m, the X.sub.2 line selecting transistor S.sub.2 is turned on so that the picture element P.sub.21 emits light in accordance with the video signal at that time. Similarly, the remaining X line selecting transistors S.sub.3 through S.sub.m are scanned. Thus, the image data is written into the picture elements P.sub.11 through P.sub.ml connected to the Y.sub.1 line. When one Y shift clock pulse is applied to the column scanning Y shift registers DY.sub.1 through DY.sub.n and the X shift signal is supplied again, the picture element P.sub.12 is selected. All the picture elements are scanned in this manner so that one image field is written into the matrix image display panel.

FIG. 2 is a block diagram of a display control system connected to the matrix image display panel of FIG. 1. For convenience, the display control system of FIG. 2 will be described for the case where an NTSC video signal is used to display an image without interlaced scanning. Furthermore, it will be assumed that in the matrix image display panel of FIG. 1, m (X lines)=96, and n (Y lines)=60.

The display control system of FIG. 2 includes a synchronizing separator circuit 11 for obtaining a horizontal synchronizing signal, a vertical synchronizing signal and a video signal from an NTSC video composite signal. A Y delay circuit 12 delays the vertical synchronizing signal for a predetermined period of time, and an X delay circuit 13 delays the horizontal synchronizing signal for a predetermined period of time. The display control system further includes four 1/2 frequency dividers 14, 15, 16 and 17, and a high frequency oscillator 18 oscillating in synchronization with the horizontal synchronizing signal. A Y delay period setting circuit 20 determines the delay period which is applied to the Y delay circuit 12. An X delay period setting circuit 21 determines the delay period which is applied to the X delay circuit 13. A pair of selection switches 22 and 23 are provided so as to supply the shift clock pulse of a desired frequency suited for the selected magnification to a matrix image display panel 19.

As is well known in the display art, a horizontal period of 63.5 .mu.s has an effective image data period of 53.3 .mu.s. In displaying an image having the standard size, the video signal should be sampled equally for the number (96) of the rows. Therefore, the X shift clock frequency f.sub.X is as follows: ##EQU1## On the other hand, the Y shift clock pulse should switch the selection of the sixty (60) Y lines with respect to 240 effective scanning lines (which are available when no interlaced scanning is carried out) so that the Y shift clock pulse selects one Y line per four effective scanning lines. Therefore, the Y shift clock frequency f.sub.Y is as follows: ##EQU2## As shown in FIG. 2, the oscillating signal of 7.2 MHz frequency developed from the high frequency oscillator 18 which oscillates in synchronization with the horizontal synchronizing signal, is frequency-divided by the two 1/2 frequency dividers 16 and 17 so as to obtain the X shift clock pulse having the frequency of 1.8 MHz. The Y shift clock pulse with a frequency 3.94 KHz can be obtained by directly frequency-dividing the 15.75 KHz horizontal synchronizing signal using the two 1/2 frequency dividers 14 and 15. When a portion of an image is to be displayed with a magnification of .times.2, both the X shift clock pulse and the Y shift clock pulse should have frequencies which are two times as high as the frequencies of the shift clock pulses used to display the standard size image. These doubled frequencies are obtained at the outputs of the 1/2 frequency dividers 14 and 16, respectively. In this case, if the X and Y shift signals are applied, without delay, based on the synchronizing signals, the upper left-hand portion of the image will be displayed on the matrix image display panel 19 with the magnification of .times.2.

The portion to be displayed with the desired magnification is selected by setting desired delay periods in the Y delay circuit 12 and the X delay circuit 13, respectively. In accordance with the present invention, the delay periods are automatically increased or decreased by the Y delay period setting circuit 20 and the X delay period setting circuit 21, respectively, so that the enlarged display portion is automatically shifted. That is, the Y delay period setting circuit 20 and the X delay period setting circuit 21 store the information which determines the portion to be displayed with the increased magnification and the velocity at which the displayed portion is shifted. The Y delay period setting circuit 20 and the X delay period setting circuit 21 calculate the desired delay periods in accordance with the stored information and the portion now displayed on the matrix image display panel 19. The thus obtained delay periods are applied from the Y delay period setting circuit 20 and the X delay period setting circuit 21 to the Y delay circuit 12 and the X delay circuit 13, respectively.

An operational mode of the display control system of FIG. 2 will be described when the character information received on the NTSC video signal is displayed on the matrix image display panel 19 without interlaced scanning. Now assume that the matrix image display panel 19 has the construction of m=96, and n=60, the display is conducted with .times.2 magnification so as to enhance the visibility of characters, and the enlarged display portion is automatically shifted along the sentence. The character pitch on the matrix image display panel 19 is eight scanning lines in the vertical direction, and 53.3/L (.mu.s) (L: the number of characters in one row) on the time axis of the video signal in the horizontal direction.

Now assume that a period of t (sec.) is required for the ordinary person to read one character. The Y delay period and the X delay period are first set to zero (0) so that the upper left-hand portion of the sentence is first displayed on the matrix image display panel 19. Then, in order to smoothly shift the image rightward, the X delay period setting circuit 21 calculates the X delay period which increases 53.3/2L (.mu.s) at each t (sec.). The thus obtained increasing X delay period is applied to the X delay circuit 13 so as to control the display region. When the right end of the enlarged image reaches the right end of the matrix image display panel 19, the Y delay period setting circuit 20 develops a control signal to increase the delay period determined by the Y delay circuit 12 by a period corresponding to eight (8) scanning lines. The X delay period is reset to zero (0), and , thereafter, the X delay period is gradually increased by the control signal developed from the X delay period setting circuit 21. These operations are repeated to sequentially provide the enlarge display along the sentence to be displayed.

When limit values are set to the delay periods determined by the Y delay period setting circuit 20 and the X delay period setting circuit 21, a preselected portion of the image is sequentially displayed with increased magnification. The shift velocity of the enlarged image is controlled by changing the increasing rate of the delay periods determined by the Y delay period setting circuit 20 and the X delay period setting circuit 21.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.