Apparatus for Forming a Character by a Matrix Pattern of Picture Elements

This invention relates to an apparatus for forming a character, such as a letter, a numeral, a symbol or the like by forming picture elements in the shape of a matrix. More particularly, it is concerned with an apparatus for forming a character in any desired magnification while the figure essentially meant by the character is maintained.

In general, in case of forming a letter, a numeral or a symbol by a dot matrix, if the formed character is of a size within a certain range, reading of the character is seldom impeded; however, when the character is enlarged to a certain size beyond such range, it becomes, in some cases, difficult to read the character. For example, in the case of letters composed of only horizontal and vertical lines such as "E" and "F", their clearness does not greatly lower even after they were similarly enlarged. In contrast, in the case of letters including oblique lines such as "R" and "X", reading of these letters when enlarged becomes very difficult. FIG. 1 shows an example of an enlarged "R", that is, it shows the case where the original dot pattern shown in FIG. 2 has been enlarged twice in a longitudinal direction and also twice in a lateral direction. In this example, however, it is difficult to read the enlarged "R" in an immediate manner.

In such a character formed by dots, the clearness of oblique lines has heretofore been raised by forming a dot for compensation between enlarged dots. In such prior art, however, the size of a character is standardized and compensation in vertical and horizontal directions is not made.

The present invention overcomes the above-mentioned difficulties and provides a newly improved apparatus for forming a character from a pattern of separate display picture elements.

The present invention is characterized in that, in a character formed by a matrix pattern which is composed of plural picture elements, the magnifications in a longitudinal and a lateral directions of the said pattern is set to any desired value to form a character with a desired enlargement or reduction, whereby characters in various forms having suitable sizes can be formed, and also in that upon enlargement of a character, interpolation is performed in accordance with a certain rule to maintain the figure meant by the character, whereby no matter how the character is enlarged, it is easy to read the character.

It is the first object of the invention to form a character of a desired size by enlarging or reducing a character formed by a pattern of picture elements in any desired magnification in both a longitudinal and a lateral direction.

It is the second object of the invention to subject an enlarged character formed by a pattern of picture elements to interpolation in accordance with a certain rule, whereby no matter of what extent the enlargement of the character may be, the figure meant by the character is maintained to have the character recognized clearly.

It is the third object of the invention to provide a single, small-size apparatus without using an apparatus of a separate system such as a computer.

The nature of the present invention as well as other objects and advantages thereof will become more apparent from consideration of the following detailed description and the accompanying drawing in which:

FIG. 1 is an enlarged view of the letter "R" formed by a dot matrix, the letter "R" having been enlarged according to the prior art;

FIG. 2 is a view showing the original letter pattern of the enlarged letter of FIG. 1;

FIG. 3 is an enlarged view of the letter "R" for illustration of an embodiment of the invention;

FIGS. 4 A-H and 5 A-D are views of dot arrangement illustrating the methods of interpolation according to the invention;

FIGS. 6 and 7 A-D are explanatory views showing an example of interpolation methods;

FIGS. 8 through 19 are logical circuit diagrams showing an embodiment of the invention;

FIG. 20 is a view in which the dot pattern of FIG. 2 has been expressed using bit pattern;

FIGS. 21 and 22 are views of bit content illustrating a storage condition of registers M.sub.1 through M.sub.9 ;

FIG. 23 is an enlarged dot view of the letter "R" formed according to an embodiment of the invention;

FIG. 24 is a table showing an example of interpolation methods using bit pattern; and

FIGS. 25 A-H and 26 A-D are views illustrating part of the interpolation method of the invention using bit pattern.

Before illustrating embodiments of the present invention, an explanation is given below on the term "interpolation" as herein used. By the term "interpolation" we mean that, when a matrix pattern formed by plural dots cannot clearly express the object, a dot is formed between adjacent dots.

The interpolation method according to the present invention is explained below. FIG. 2 shows the letter "R" constructed by a dot matrix of seven rows and five columns. In FIG. 3, such letter "R" has been enlarged twice in row and three times in column. To the portions which have become obscure as a result of such enlargement, a first interpolation method is performed in a manner explained below. The dotted and the undotted portions in the original dot pattern of FIG. 2 are divided into domains of seven rows and five columns as shown with dotted lines. Then, attention is paid to one domain [n, m] (n and m mean the number of row and column respectively), and a small matrix of three rows and three columns including such domain [n, m] is formed. In this case, however, the small matrix is not an optional small matrix, but it is picked out from the domain of FIG. 2 so that, if the domain [n, m] picked out from FIG. 2 is in the position [p, q] in the number of row and column set in the small matrix, the sum of p and q becomes an odd number. In case, in such small matrix, the domain pattern takes the constructions shown in FIGS. 4A through 4H, interpolation is performed to a portion, d, of the undotted domain a.sub.n,m between the dotted domains b.sub.1 and b.sub.2. If this is applied to FIG. 2, the corresponding domain is the domain [5, 2]. Since this corresponds to the enlarged domain [9, 6] of FIG. 3, a dot d.sub.0 is formed in the same domain.

In this way, attention is paid to any one domain and a matrix of three rows and three columns is assumed, then decision is made whether interpolation is needed or not.

The clearness of a character is somewhat raised by application of the foregoing first interpolation method. If a second interpolation method as will be referred to below is further applied, then a character such as a letter, a numeral, a symbol or the like can be reappeared satisfactorily into the figure which the character essentially means. Therefore, an explanation is given below on such second interpolation method. In FIG. 2, attention is paid to any one undotted domain [p, q] and a small matrix of two rows and two columns including such undotted domain [p, q] is assumed. Such any one undotted domain is taken to be a.sub.n,m (n and m mean the number of row and column respectively) and the matrix two rows by two columns is taken to be ##EQU1## In such matrix, in case the domain a.sub.n-1, m+1 corresponding to the undotted domain a.sub.n, m is undotted and the domains a.sub.n-1, m and a.sub.n, m+1 are dotted, interpolation is performed to part of the undotted domain a.sub.n, m, and in case the above-mentioned conditions are not satisfied, interpolation is not performed.

FIGS. 5A through 5D show all the positional relationships between undotted domains C.sub.1 through C.sub.4 and dotted domains b.sub.1 and b.sub.2, and also show interpolation in each case. If the second interpolation method is applied to FIG. 2, interpolation is performed to [1, 5] [2, 4] [3, 4] [4, 5] [5, 4] [6, 3] [7, 4] and [6, 5] of FIG. 2. In this way, domains to be interpolated are decided in the original character.

Now, an explanation is given below on the rule for forming dots in the domains to be interpolated when the original character is enlarged. FIG. 6 shows the case in which the original pattern illustrated in FIG. 5C has been enlarged S times in column and T times in row. In FIG. 6, the range to be interpolated is the portion H. FIG. 7D shows the case in which the interpolation portion H alone has been picked up. In the same way, with respect to the original patterns illustrated in FIGS. 5A through 5C, the domains requiring interpolation have been enlarged, and the results are as shown in FIGS. 7A through 7C. In FIG. 7, the reference marks "0" to "x" inclusive represent the number of column in each domain, while the reference marks "0" to "y" inclusive indicate the number of row. The position and number of dots for performing interpolation is decided so as to satisfy the following expressions:

In FIG. 7A,

in FIG. 7B,

in FIG. 7C,

In FIG. 7D,

The above inqualities indicate the number of dots to be formed in the domains requiring interpolation, and they have been derived in an experimental manner with respect to the case in which the character undergoing interpolation does not lose naturality.

Next, in reference to an apparatus for enlarging and interpolating a character, an explanation is given below on the basis of FIGS. 8 through 17. In FIG. 8, a keyboard K is composed of keyswitches each indicating letters, numerals, symbols or the like, and various data inputed through these keys are transferred to registers R.sub.1 and R.sub.2 by means of a data multiplexer. The registers R.sub.1 and R.sub.2 are for storing the magnification of a letter, etc. and they store the magnification of column and row respectively. A register R.sub.3 stores data such as a letter, a numeral, etc., of which one word is read out and written in a storage latch R.sub.4. An arithmetic unit AD shown in FIG. 10 performs addition and subtraction between various counting contents and storage contents. And a specific operational output of the arithmetic unit AD is stored in a storage latch R.sub.5. A storage latch R.sub.6 shown in FIG. 11 temporarily stores the output of a counter C.sub.4. A shift register R.sub.7 shown in FIG. 17, which has a capacity of 7 bits, stores dot data for recording. A character generator CG shown in FIG. 12 effects a code conversion of the output data of the storage latch R.sub.4 shown in FIG. 8. This output is stored by shift registers M.sub.1 through M.sub.9 shown in FIG. 12, the shift registers M.sub.1 through M.sub.9 having a function of shifting in both a longitudinal and a lateral directions on the drawing. An interpolation detecting circuit U is a circuit for detecting whether interpolation is required or not on the basis of the bit pattern of the original character, and its details are illustrated in FIG. 16. This circuit is adapted to take out each output of the bit pattern stored in the registers M.sub.1 through M.sub.9 and logically detect the first and the second interpolations. A storage latch R.sub.8 shown in FIG. 15 stores specific operational outputs b.sub.1 through b.sub.4 of the arithmetic unit AD illustrated in FIG. 10.

In FIG. 11, the block C.sub.1 is a heptal counter and the block C.sub.2 is a preset counter in which "7" is set. The block P.sub.1 is a coincidence circuit, the blocks C.sub.3 and C.sub.4 are binary counters and block P.sub.2 is a comparison circuit. The block C.sub.5 in FIG. 12 is a pental timing counter and it produces a timing pulse in terminals d.sub.1 through d.sub.5. In a preset counter C.sub.7 shown in FIG. 13, "5" is set; and when a counter C.sub.6 counts "5", an output is produced from a coincidence circuit P.sub.3. A counter C.sub.8 shown in FIG. 14 has a decimal counting function; in a preset counter C.sub.9 is set "9", and upon coincidence with the output of the counter C.sub.8, an output is produced from a coincidence circuit P.sub.4. A decoder DC shown in FIG. 15 produces an output when the magnification of a character is "1", "7", "14" . . . . The block P.sub.5 represents a coincidence circuit. Monostable multivibrators N.sub.1 through N.sub.10 (hereinafter referred to simply as "Mono Multi") shown in FIGS. 9 and 12 through 15 are used for providing an output timing and also for waveform shaping.

The block DL shown in FIG. 11 represents a delay circuit and the blocks F.sub.1 and F.sub.2 shown in FIG. 14 are R-S flip-flop circuits. The block DR shown in FIG. 17 represents a driving device for operating a wire dot printer; in this embodiment there is shown the case in which a dot is formed while seven pins are moved in a lateral direction. In FIG. 17, the blocks AC.sub.1 through AC.sub.3 are multipliers, blocks B.sub.1 through B.sub.4 are adders and blocks P.sub.6 through P.sub.9 are coincidence circuits. In FIGS. 8 through 17, the blocks G.sub.1 through G.sub.137 and G.sub.197, G.sub.198 are gate circuits.

With respect to the interpolation detecting circuit U shown in FIG. 16, a further detailed explanation is given below. The theoretical values in storage positions (1A to 1E inclusive) through (9A to 9E inclusive) of the registers M.sub.1 through M.sub.9 shown in FIG. 12 are fed to the input terminals of the gates which are indicated with the same reference marks in FIG. 16. FIG. 16 illustrates the first and the second interpolation methods which have been logically assembled, and its detailed explanation is given below.

First, in the first interpolation method, if the matrix of three rows and three columns is ##EQU2## and attention bit is bp+1,q, and when the relationship ##EQU3## is satisfied, the bit Bp+1,q is converted to "1". If attention bit is Bp,q+1, when the relationship ##EQU4## is satisfied, and if attention bit is Bp+1,q+2 when the relationship ##EQU5## is satisfied, and if attention bit is Bp+2,q+1, when the relationship ##EQU6## is satisfied, those attention bits are conveted to "1".

If the matrix two rows by two columns is ##EQU7## and attention bit is A.sub.p+1,q or A.sub.p,q+1, and when the relationship

is satisfied, the bit A.sub.p+1,q or A.sub.p,q+1 is converted to "1". If attention bit is A.sub.p,q or A.sub.p+1,q+1, and when the relationship

is satisfied, the attention bit is converted to "1". Consequently, when attention bit is "0" and when the relationship ##EQU8## is satisfied, the attention bit is converted to "1". FIG. 16 shows the case where attention bit was taken to be in storage position 3C of the register M.sub.3 shown in FIG. 12 and the logical relationship of the aforementioned (5) through (9) was summarized.

Next, an explanation on operation is given below; to be more specific, an explanation is made on the operation of the case where the original pattern of the letter "R" used in FIG. 2 is enlarged twice in row and three times in column as is shown in FIG. 3 and interpolation is performed. In FIG. 8, the magnifications "2" and "3" respectively of row and column of the letter as well as the character data for one line for printing are inputed from the keyboard K and are written in the magnification registers R.sub.1 and R.sub.2 and the data register R.sub.3 respectively through the data multiplexer D. By a printing instruction PSo given from the keyboard side, the letter "R" is read from the register R.sub.3 and is transcribed in the storage latch R.sub.4 for one word. This output Do is fed to the input of the character generator CG shown in FIG. 12, where it is converted to the bit pattern illustrated in FIG. 20 in which the dots and the undotted portions shown in FIG. 2 have been converted to "1" and "0" respectively. At the same time, the output PSo triggers the Mono Multi N.sub.3 through the gate circuit G.sub.65 shown in FIG. 12 and goes to an output PS.sub.1, which feeds a logical value (11) to the two inputs of the arithmetic unit AD through the gate circuits G.sub.13 through G.sub.15 shown in FIG. 10. The other two inputs of the arithmetic unit AD, that is, the outputs of the gate circuits G.sub.16 and G.sub.17, are in a state of (00), so that in one input of the arithmetic unit AD is fed (0011), that is, a decimal "3". Further, the output PS.sub.1 opens the gate circuits G.sub.26 through G.sub.29 shown in FIG. 10 and (0000) of the outputs a.sub.1 through a.sub.4 of the already-cleared counter C.sub.6 shown in FIG. 13 is fed to the arithmetic unit AD. Consequently, "3" is produced in the output of the arithmetic unit AD, and the output PS.sub.1 of the Mono Multi N.sub.3 shown in FIG. 12 which has been triggered by the output PSo goes to PS.sub.2 through the gate circuit G.sub.66, whereby the said "3" is written in the storage latch R.sub.5 shown in FIG. 10. The outputs e.sub.1 through e.sub.3 of the storage latch R.sub.5 designate the third column of the character generator CG shown in FIG. 12. Consequently, the data of the third column in the bit pattern shown in FIG. 20 is put out. The reason why the third column of the bit pattern of the letter "R" is first read, is as follows. In the foregoing first and second interpolation methods, attention is paid to any one undotted domain and when the presence and absence of surrounding dots are in a certain relationship, interpolation is performed to the noticed, undotted domain. In this example, in which the presence and absence of dot dorrespond to logical "1" and "0" respectively, the attention bit shifts to a certain storage position in register and decision is made by the interpolation detecting circuit U as to whether the bit in such storage position is "1" or "0" and, when it is "0", as to whether the surrounding bit pattern requires the first or the second interpolation method. FIGS. 25 and 26 show the case in which the foregoing dot patterns for interpolation have been converted to bit patterns of "1" and "0" and in which the bit b.sub.0 indicates attention bit. The data bits of each column of the bit pattern read from the character generator CG are stored in the registers M.sub.3 through M.sub.9. In this example, attention bit is shifted to the storage position 3C of the register M.sub.3 and, with this bit as the center, correlation thereof with surrounding bits is studied.

Now returning to the foregoing explanation, the third column of the bit pattern of FIG. 20 stored in the character generator CG is designated by the outputs e.sub.1 through e.sub.3 of the storage latch shown in FIG. 10 and the data bits of the third column (1001100) are fed to the registers M.sub.3 to M.sub.9 inclusive through the gate circuits G.sub.56 to G.sub.62 inclusive shown in FIG. 12. On the other hand, the counter C.sub.5 is advanced by "1" by the foregoing output PS.sub.2, thus producing an output in its terminal d.sub.1, whereby the contents of the registers M.sub.1 through M.sub.9 are shifted by one bit to the right through the gate circuits G.sub.68 and G.sub.67. As a result, the data bits of the third column mentioned above are transcribed in the storage positions 3A through 9A of the registers M.sub.3 through M.sub.9. The reason why the registers M.sub.1 and M.sub.2 have been provided is that at most two bits in the two rows above the attention bit are required as the object of detection. Mono Multi N.sub.4 is triggered by the output of the foregoing terminal d.sub.1 and its output PS.sub.3 is fed to one input of the arithmetic unit AD through the gate circuit G.sub.13 to G.sub.17 inclusive shown in FIG. 10. On the other hand, the output PS.sub.3 opens the gate circuit G.sub.30 through G.sub.33 and feeds (0011) of outputs e.sub.1 through e.sub.4, that is, decimal "3", to the other input of the arithmetic unit AD, so that (0010), that is, decimal "2", is produced at the output of the arithmetic unit AD and it is written in the storage latch R.sub.5 by the fall of the output PS.sub.2. The data bits of the second column in the bit pattern of "R" shown in FIG. 20 are designated by the outputs e.sub.1 through e.sub.4 of the storage latch R.sub.5 and are fed to the registers M.sub.3 through M.sub.9. The counter C.sub.5 shown in FIG. 12 is advanced by "1" by the foregoing output PS.sub.2 and counts "2". By the output of its terminal d.sub.2 the contents of the registers M.sub.3 through M.sub.9 are shifted by one bit to the right and the data bits of the third column are transcribed to the storage positions 3B through 9B and the data bits of the second column to the storage positions 3A through 9A. In the same way, the data bits of the first column are transcribed to the storage positions 3A through 9A of the registers M.sub.3 through M.sub.9. The subsequent outputs e.sub.2 through e.sub.4 close the gate circuits G.sub.56 to G.sub.62 inclusive through the gate circuits G.sub.63 and G.sub.64 and feed "0" to the inputs of the registers M.sub.3 through M.sub.9. Consequently, after a total of five shifts, the storage contents of the registers M.sub.3 through M.sub.9 become the bit pattern illustrated in FIG. 21.

When attention is paid to the content of the storage position 3C of the register M.sub.3 shown in FIG. 12, that is [M.sub.3, C] shown in FIG. 21, its bit is "1" and therefore this does not become the object of interpolation. The output "1" of the storage position 3C of the register M.sub.3 shown in FIG. 12 closes the gate circuit G.sub.18 shown in FIG. 9 and at the same time opens the gate circuit G.sub.19. At this moment, in the other input of the gate circuit G.sub.19 is fed through the gate circuit G.sub.20 the output PS.sub.4 of Mono Multi N.sub.5 which has been triggered by the output of the last terminal d.sub.5 of the counter C.sub.5. This output triggers Mono Multi N.sub.1, the output of which PS.sub.5 is fed to the gate circuit G.sub.69 shown in FIG. 17. The content of the shift register R.sub.7 is shifted by one bit and in the storage position X.sub.1 is written "1" which is fed to the input through the gate circuit G.sub.197. On the other hand, the foregoing output PS.sub.5 advances the content of the counter C.sub.4 by "1" through the gate circuit G.sub.54 shown in FIG. 11. The counter C.sub.4 is for counting the magnification of row of an enlarged dot pattern. The outputs h.sub.1 through h.sub.4 of the counter C.sub.4 which has counted the above-mentioned "1" are fed to the gate circuits G.sub.48 through G.sub.51. In this case, since the gate circuits G.sub.48 through G.sub.51 are opened by the output PS.sub.6 of Mono Multi N.sub.2 shown in FIG. 9 which has been triggered by the output PS.sub.5, the output h.sub.1 through h.sub.4 pass through the gate circuits G.sub.48 to G.sub.51 inclusive and are fed to one inputs `q` of the comparison circuit P.sub.2 through the gate circuits G.sub.40 to G.sub.43 inclusive. The row magnification "2" stored in the register R.sub.1 shown in FIG. 8 passes through the gate circuits G.sub.5 to G.sub.8 inclusive since the latter circuits are opened by the output PS.sub.6 and is fed to the other inputs `p` of the comparison circuit P.sub.2 through the gate circuits G.sub.36 to G.sub.39 inclusive. The set magnification is "2" and the value of the counter C.sub.4 is "1" and thus coincidence is not obtained; therefore, the coincidence output p=q of the comparison circuit P.sub.2 does not change. On the other hand, the foregoing output PS.sub.5 advances the content of the counter C.sub.1 by "1" through the gate circuit G.sub.54. The counter C.sub.1 is for counting the number of bits stored in the register R.sub.7 shown in FIG. 17.

Further, the output PS.sub.5 is fed through the gate circuit G.sub.34, Mono Multi N.sub.2, gate circuit G.sub.35 and gate circuit G.sub.20 to the gate circuit G.sub.19 as is shown in FIG. 9. Since the gate circuit G.sub.19 is opened by the output "1" of the storage position 3C of the register M.sub.3, the output of the gate circuit G.sub.20 passes through the gate circuit G.sub.19 and triggers Mono Multi N.sub.1, thus again producing the output PS.sub.5. This output PS.sub.5 shifts the register R.sub.7 by one bit through the gate circuit G.sub.69 shown in FIG. 17, whereby the output "1" of the storage position 3C is written in the storage position X.sub.1 of the register R.sub.7. Consequently, "1" is stored in both storage positions X.sub.1 and X.sub.2 of the register R.sub.7. On the other hand, the output PS.sub.5 advances by "1" the content of the counter C.sub.1 shown in FIG. 11, so that its counting content becomes "2". Further, the output PS.sub.5 makes the content of the counter C.sub.4 into "2". This counting outputs h.sub.1 through h.sub.4 are fed to one inputs `q` of the comparison circuit P.sub.2 in the same way as hereinbefore described, where they are compared with the row magnification "2". Since both objects of comparison are "2", there is produced "1" at the output p=q of the comparison circuit P.sub.2. As a result, from the gate circuit G.sub.78 shown in FIG. 14 there is produced an output W, which resets the counter C.sub.4 through the gate circuit G.sub.56 shown in FIG. 11. On the other hand, the output W triggers Mono Multi N.sub.6 shown in FIG. 14, thus causing an output PS.sub.7 to be produced, which goes to PS.sub.8 through the gate circuit G.sub.77, whereby the content of the counter C.sub.8 is advanced by "1".

The output PS.sub.8 is applied as a shift pulse in a longitudinal direction of the registers M.sub.1 through M.sub.9 shown in FIG. 12, whereby the contents of lower rank registers of the registers M.sub.1 through M.sub.9 are transcribed to higher rank registers, and the resulting content is as shown in FIG. 22. Consequently, in the storage position 3C of the register M.sub.3 is stored the bit corresponding to the two rows and one column of the matrix in the bit pattern of FIG. 20, and this bit becomes attention bit. The output PS.sub.7 of Mono Multi N.sub.6 shown in FIG. 14 triggers Mono Multi N.sub.7 and produces an output PS.sub.9, which is fed to the gate circuit G.sub.19 through the gate circuit G.sub.20 shown in FIG. 9.

Thereafter, in an identical manner as hereinbefore described, "1" and "1" are stored in the register R.sub.7 shown in FIG. 17. When in this way seven bits, that is, the bits corresponding to the dots of the number of the row and the column of the matrix [z, 1] (z being an integer from 1 to 7) shown in FIG. 3, have been stored in the register R.sub.7, an output of "7" is produced from the counter C.sub.1 shown in FIG. 11. Since this output coincides with the "7" stored in the preset counter C.sub.2, a coincidence output PS.sub.10 is produced in the coincidence circuit P.sub.1 and the content of the counter C.sub.3 is advanced by "1". At the same time, the coincidence output PS.sub.10 actuates the wire driving circuit DR shown in FIG. 17 so that each wire is driven correspondingly to the storage content of the register R.sub.7. The wire head continues moving. As the contents of the register R.sub.7 are all "1", all the wires PN are driven to form the seven dots of the first column shown in FIG. 3. On the other hand, after the output PS.sub.10 has been fed to the wire driving device DR, an output PS.sub.11 is produced from this wire driving device DR. By the output PS.sub.11 the gate circuits G.sub.44 through G.sub.47 shown in FIG. 11 are opened and the output "1" of the counter C.sub.3 is fed to one inputs `q` of the comparison circuit P.sub.2 through the gate circuits G.sub.40 to G.sub.43 inclusive.

On the other hand, the column magnification "3" stored in the register R.sub.2 is fed to the other inputs `p` of the comparison circuit P.sub.2 through the gate circuits G.sub.1 through G.sub.4 shown in FIG. 8 and G.sub.36 through G.sub.39 shown in FIG. 11. Since both values for comparison are different, the output p=q of the comparison circuit P.sub.2 does not change. Consequently, the gate circuit G.sub.72 shown in FIG. 14 produces an output to set the flip-flop circuit F.sub.1, whose output opens the gate circuit G.sub.73, so that the output of the clock pulse generator CL is fed to the counter C.sub.8 through the gate circuits G.sub.73, G.sub.76 and G.sub.77. As the counter C.sub.8 has already counted shift pulses three times, its content is "3". If, in addition, six pulses of the foregoing clock pulse are fed, the value on the counter C.sub.8 becomes "9", and coincidence thereof with the preset value "9" of the counter C.sub.9 is obtained in the coincidence circuit P.sub.4. While this coincidence output S.sub.1 resets the counter C.sub.8 through the gate circuit G.sub.75, it resets the flip-flop circuit F.sub.1 to close the gate circuit G.sub.73, thus causing the provision of the clock pulse to the counter C.sub.8 to be stopped. The aforementioned six pulses through the gate circuit G.sub.77 are fed as a longitudinal shift pulse for the registers M.sub.1 through M.sub.9 shown in FIG. 12 and, therefore, the contents of the registers are shifted six times successively from lower rank to higher tank registers. This is for returning the storage contents of registers M.sub.1 through M.sub.9 to the bit pattern in the initial state shown in FIG. 21. That is, the initial storage content has been re-obtained by shifting nine times from the initial state. Then, the dots of the second column, that is, the dots of the number of the row and the column of the matrix [Y, 2] (Y being an integer from 1 to 7), are formed in the same way as hereinbefore described. At the end of such dot formation, the counter C.sub.6 shown in FIG. 11 counts "2" and this counting output is compared with the magnification "3" by the comparison circuit P.sub.2. Since the two values do not coincide with each other, the output p=q of the comparison circuit P.sub.2 does not change and the same operation as hereinbefore described is repeated.

When the dots as far as the third column in FIG. 3 have been formed in this way, the value on the counter C.sub.3 shown in FIG. 11 becomes "3". Coincidence of this value with the column magnification "3" produces a logical value "1" in the output p=q of the comparison circuit P.sub.2 shown in FIG. 11. As a result, an output is produced from the gate circuit G.sub.55 and this delay output PS.sub.12 resets the counter C.sub.3. Also, the output PS.sub.12 advances by "1" the content of the counter C.sub.6 shown in FIG. 13. Further, the output PS.sub.12 triggers Mono Multi N.sub.8, the output of which is fed to the gate circuit G.sub.70. In this condition, the output of the coincidence circuit P.sub.3 is "0" and so the gate circuit G.sub.70 is kept open, which causes an output PS.sub.21 to be produced from Mono Multi N.sub.8. The output PS.sub.21 advances the value on the counter C.sub.5 by "1" through the gate circuit G.sub.65, Mono Multi N.sub.3 and gate circuit G.sub.66. On the other hand, with the output PS.sub.2, the output of the arithmetic unit AD shown in FIG. 10 is transcribed in the memory latch R.sub.5, the output of which designates a column in the character generator CG shown in FIG. 12. Consequently, the second column shown in FIG. 20 is read from the character generator CG so that it is stored in the storage positions 3C through 9C of the registers M.sub.3 through M.sub.9.

Thereafter, dots are formed in the same manner as hereinbefore described. In case "0" has been stored in the storage position 3C of the register M.sub.3 shown in FIG. 12 though this does not accord with the interpolation methods of the present invention, for example, in the case of non-dot as is shown by the domain of the number of the row and the column of the matrix [5, 4] in FIG. 3 operation is different from that hereinbefore described.

Since the content of the storage position 3C is "0", the gate circuit G.sub.18 shown in FIG. 9 is opened and the output of the gate circuit G.sub.20 goes to an output So through the gate circuit G.sub.18. The output So triggers Mono Multi N.sub.11 shown in FIG. 17, the output of which opens the gate circuit G.sub.136. Since this example does not accord with the interpolation method of the invention, the outputs U.sub.1 through U.sub.4 of the interpolation detecting circuit shown in FIG. 16 are "0". Consequently, the output of the gate circuit G.sub.135 shown in FIG. 17 is "0" and also the output of the gate circuit G.sub.136 is kept "0", so that the flip-flop circuit F.sub.3 is not set and assumes a reset state. As a result, the output of the gate circuit G.sub.137 becomes "0", the output of Mono Multi N.sub.12 shifts the register R.sub.7 by one bit and the output "0" of the gate circuit G.sub.137 is written in the register R.sub.7. Thereafter, the flip-flop circuit F.sub.3 is reset by the output of Mono Multi N.sub.13.

Assuming that the dots up to the ninth column in the dot pattern shown in FIG. 3 have been formed in the same way, the counter shown in FIG. 13 now counts "3".

Accordingly, the range of from the 10th to 15th columns and from the 1st to 4th rows in FIG. 3 accords the interpolation method as has been explained hereinbefore in connection with FIGS. 6 and 7. The interpolation range from the 10th to 12th columns and from the 3rd to 4th rows corresponds to FIG. 7D. When a non-dot "0" in such an interpolation range has been stored in the storage position 3C shown in FIG. 12, the output U.sub.4 of the interpolation detecting circuit shown in FIG. 16 becomes "1" and the outputs U.sub.1 through U.sub.3 become "0". Whether or not dots should be formed in the interpolation range is decided by the circuit shown in FIG. 17. First, a study is made below on the domain of the number of the row and the column of the matrix [3, 10]. The outputs f.sub.1 through f.sub.4 (hereinafter referred to generically as "F") of the counter C.sub.3 shown in FIG. 11 are "0", the outputs h.sub.1 through h.sub.4 (hereinafter referred to generically as "H") of the counter C.sub.4 also shown in FIG. 11 are "0", the set row magnification S is "2" and column magnification T is "3", and these are all put in the circuit shown in FIG. 17. Consequently, the output of the multiplier AC.sub.1 and that of AC.sub.3 become "0" and the output of the adder B.sub.3 becomes "3". As a result, the input relationship of the comparator P.sub.8 becomes l.sub.3 > l.sub.4 and its output becomes "0" and consequently the output of the gate circuit G.sub.133 goes to "0". Since the other outputs V.sub.1 through V.sub.3 are "0", the output of the gate circuit G.sub.135 becomes "0" and it is stored in the register R.sub.7 in the same manner as hereinbefore described.

As an example, with respect to the number of the row and the column of the matrix [3, 12] shown in FIG. 3, whether or not interpolation is performed below. In this domain, the output F of the counter C.sub.3 shown in FIG. 11 is "2" and the output H of the counter C.sub.4 is "0" and consequently, in FIG. 17, the output of the multiplier AC.sub.1 is "4", that is l.sub.4 = 4. Further the output of the multiplier AC.sub.3 is "0" and that of the adder B.sub.3 becomes "3", so that the input of the comparator P.sub.8 is l.sub.4 > l.sub.3 and at the output thereof "1" is produced. As set forth hereinbefore, the input U.sub.4 of the gate circuit G.sub.133 is "1" and so it is produced at the output of the gate circuit G.sub.133 ; consequently, "1" is produced at the output of the gate circuit G.sub.135. The gate circuit G.sub.136 is kept open by the output of the Mono Multi N.sub.11 shown in FIG. 17 which has been triggered by the output So of the gate circuit G.sub.18 shown in FIG. 9. Therefore, the resulting output sets the flip-flop circuit F.sub.3 and gives " 1" at one input of the gate circuit G.sub.137. Pulse from Mono Multi N.sub.12 produces "1" at the output of the gate circuit G.sub.137 and the register R.sub.7 is shifted by one bit through the gate circuit G.sub.69, and the above-mentioned output "1" is written in the register R.sub.7. This becomes a dot for interpolation.

Next, in the case of the number of the row and column of the matrix [4, 12] in FIG. 3, the output F of the counter C.sub.3 is "2" and the output H of the counter C.sub.4 is "1". Consequently, the output l.sub.4 of the multiplier AC.sub.1 is "4" and that of the multiplier AC.sub.3 is "3" and, therefore, the output l.sub.3 of the adder B.sub.3 becomes "6". The input relationship of the comparator P.sub.8 becomes l.sub.4 > l.sub.3 and the output thereof becomes "0", so that the output of the gate circuit G.sub.133 becomes "0" and in the register R.sub.7 is written "0" in the same manner as hereinbefore described. This means that interpolation is not performed.

Thus, in the undotted domain of a bit pattern, whether or not it corresponds with the interpolation method of the present invention is detected by the interpolation detecting circuit, and whether or not a dot should be formed in the undotted domain is detected by the upper half circuit of FIG. 17 and interpolation is made.

FIG. 18 shows another example of FIG. 17. The reference marks G.sub.138 through G.sub.196 are gate circuits, the reference marks N.sub.14 through N.sub.17 are monostable multivibrators (hereinafter referred to simply as "Mono Multi"), the reference mark AC.sub.4 is a multiplier, B.sub.5 is an adder, P.sub.10 is a comparator, R.sub.9 through R.sub.12 are registers, and TM.sub.1 and TM.sub.2 are timing pulse generators.

In the construction mentioned above, and explanation is given below on the same concrete example as the operation which has been explained in connection with FIG. 17. As already mentioned, the domain of the number of the row and the column of the matrix [3, 12] shown in FIG. 3 requires interpolation and the output U.sub.4 of the interpolation detecting circuit is "1". Further, at the time of detection of the said domain, the output F of the counter C.sub.3 shown in FIG. 11 is "2" and the output H of the counter C.sub.4 is "0". The row magnification S is "2" and the column magnification T is "3". The output So produced from the gate circuit G.sub.18 shown in FIG. 9 causes timing pulses to be generated successively at the outputs V.sub.1 through V.sub.4 of the timing pulse generator TM.sub.1 shown in FIG. 18. Upon generation of pulse at the output V.sub.1, the row magnification S=2 is fed to one input of the multiplier AC.sub.4 through the gate circuits G.sub.138 and G.sub.144, and the gate circit G.sub.143 is opened by the said pulse, whereby the output F=2 of the counter C.sub.3 is fed to the other input of the multiplier AC.sub.4. Consequently, a multiplication of "2" by "2" is done in the multiplier AC.sub.4 to produce "4" at the output, and this "4" is written in the register R.sub.9 by the above-mentioned pulse. Next, upon generation of pulse from the output V.sub.2 of the timing pulse generator TM.sub.1, the gate circuit G.sub.139 is opened and the column magnification T=3 is fed to one input of the multiplier AC.sub.4, and also the gate circuit G.sub.146 is opened and the output H=0 of the counter C.sub.4 is fed to the other input of the multiplier AC.sub.4. Consequently, "0" is produced at the output of the multiplier AC.sub.4 and it is written in the register R.sub.10 by the pulse of the output V.sub.2 through the gate circuit G.sub.148 which is opened by the said pulse. Further, by the pulse from the output V.sub.3 of the timing pulse generator TM.sub.1, the gate circuits G.sub.140 and G.sub.141 are opened and the row magnification "2" and the column magnification "3" are fed to the multiplier AC.sub.4 to produce "6" at the output, which is written in the register R.sub.11 by the pulse from the output V.sub.3. Further, upon generation of pulse from the output V.sub.4 of the timing pulse generator TM.sub.1, the gate circuit G.sub.150 is opened, but its output is "0" since the output U.sub.3 of the interpolation detecting circuit is "0", and consequently the output of the gate circuit G.sub.157 also becomes "0". As a result, "0" is written in the register R.sub.12 by the pulse of output V.sub.4. On the other hand, the gate circuit G.sub.189 shown in FIG. 19 is opened by the pulse of the output V.sub.4 and a logical inversion value U.sub. 3 = "1" of the output U.sub.3 = 0 of the interpolation detecting circuit opens the gate circuits G.sub.193 and G.sub.194 through the gate circuit G.sub.191. With the output U.sub.4 = 1 of the interpolation detecting circuit, a pulse is generated at the output V.sub.6 of the gate circuit G.sub.194, whereby Mono Multi N.sub.17 is triggered to produce a pulse of the output V.sub.7. First the gate circuits G.sub.154 and G.sub.158 are opened by the pulse of the output V.sub.6 and the output "0" stored in the register R.sub.10 and the column magnification T = 3 are added together by the adder B.sub.5 to produce an output "3", which is written in the register R.sub.12 by the pulse of the output V.sub.6. Next, the gate circuits G.sub.180 and G.sub.184 are opened by the pulse of the output V.sub.7 of Mono Multi N.sub.17 shown in FIG. 19 and in one input `a` of the comparator P.sub.10 is fed "3", while in the other input `b` is fed "4" which has been stored in the register R.sub.9. Therefore the input relationship becomes a > b and "1" is produced at the output a > b of the comparator P.sub.10. Since the output a > b is "0", the gate circuits G.sub.174 through G.sub.176 are opened. To the gate circuit G.sub.174 is fed an output V.sub.7 and so the gate circuit G.sub.178 produces an output, which triggers Mono Multi N.sub.16 through the gate circuit G.sub.196 to produce an output pulse PS.sub.15. Subsequent operations are completely the same as those which have been explained in connection with the preceding example.

Next, a study is made below on the domain of the number of the row and the column of the matrix [4, 12] shown in FIG. 3. The output U.sub.4 of the interpolation detecting circuit is "1", the output F of the counter C.sub.3 is "2" and the output H of the counter C.sub.4 is "1". Production of the output So shown in FIG. 9 is followed by issuance of timing pulses successively as the outputs V.sub.1, V.sub.2, V.sub.3 and V.sub.4 of the timing pulse generator TM.sub.1, and multiplication is done successively by the multiplier AC.sub.4 in the same manner as hereinbefore described and in the registers R.sub.9, R.sub.10 and R.sub.11 are stored "4", "3" and "6" respectively. Next, upon generation of a pulse from the output V.sub.4 of the timing pulse generator, a pulse of the output V.sub.6 is produced from the gate circuit G.sub.194 through the gate circuits G.sub.189 and G.sub.191 shown in FIG. 19 and a pulse of the output V.sub.7 produced from Mono Multi N.sub.17. With the pulse of the output V.sub.6 produced, the gate circuits G.sub.154 and G.sub.158 shown in FIG. 18 are opened, and the output "3" of the register R.sub.10 and the column magnification T = "3" are added together by the adder B.sub.5 to produce an output "6", which is stored in the register R.sub.12. Next, with the pulse of the output V.sub.7 produced, the gate circuits G.sub.180 and G.sub.184 shown in FIG. 19 are opened and to the inputs `a` and `b` of the comparator P.sub.10 are fed "6" and "4" respectively, which gives an input relationship of a > b and causes "1" to be produced at the output a > b of the comparator P.sub.10. Consequently, an output V.sub.8 is produced from the gate circuit G.sub.195 through the gate circuit G.sub.192 which is kept open by the pulse of the output V.sub.7. The pulse of the output V.sub.8 causes an output to be produced from the gate circuit G.sub.168 and consequently outputs produced from the gate circuits G.sub.169, G.sub.171 and G.sub.173. The output of the gate circuit G.sub.173 triggers Mono Multi N.sub.16 through the gate circuit G.sub.196 to produce an output PS.sub.15. Subsequent operations are the same as those which have previously been explained.

In the manner mentioned above, dots and interpolation dots are formed. When the dots of the 15th column shown in FIG. 3 have been formed, the counter C.sub.6 shown in FIG. 13 counts "5" and coincidence thereof with "5" on the preset counter C.sub.7 causes an output to be produced from the coincidence circuit P.sub.3 and the output is fed to the gate circuit G.sub.71. Since the gate circuit G.sub.71 is kept open by the output of Mono Multi N.sub.8 which has been triggered by the circuit G.sub.71 and resets the counter C.sub.6 and further it becomes a signal for moving the wire head to a predetermined position so as to provide spacing for a character to be printed next. This technique is commonly used in ordinary wire dot printers and other head driving type printers and so its details are omitted here.

After a part of a character has been formed, a predetermined space is taken and a portion corresponding to 5 .times. 7 dots of the following letter, numeral or symbol is formed. In this way, when recording by a single scanning of the head has been completed, the paper is carried ahead to effect line feed.

An explanation is given below on the case where the latter half dots in the dot pattern of FIG. 3 are to be formed. Upon completion of dot recording by a single scanning as mentioned above, a carriage return signal is produced from the side of the wire driving device DR by a conventional means as is shown in FIG. 17 and the wire head returns to the recording start position. These operations are commonly performed in ordinary wire dot printers and other devices of this sort, and the present invention is not characterized in this point; therefore, details are omitted here.

During the period between the issuance of the foregoing carriage return signal and the return of the wire head to the recording start position, the following preparations are made. When printing by a single head scanning has been completed, that is, after the dots of the last column of the last character have been formed, preparations for the following operation are made by an output PS.sub.17 which is produced from the gate circuit G.sub.71 shown in FIG. 13. When printing corresponding to a single scanning has been completed, the counter C.sub.4 shown in FIG. 11 counts "1" and the counter C.sub.8 shown in FIG. 14 stores the number of longitudinal shifts of the registers M.sub.1 through M.sub.9. Therefore, it is necessary to transcribe these contents to latch circuits. First, an explanation is given below on the operation for transcribing the content of counter C.sub.4. The aforementioned output PS.sub.17 causes an output to be produced from the gate circuit G.sub.89 shown in FIG. 15 to trigger Mono Multi N.sub.10 and by the resulting output PS.sub. 18 the value "1" on the counter C.sub.4 shown in FIG. 11 is written in the storage latch R.sub.6.

Transcription of the counter C.sub.8 shown in FIG. 14 is made in the following manner. The gate circuits G.sub.79 through G.sub.82 shown in FIG. 15 are opened to allow the storage output from the register R.sub.8 to go to outputs K.sub.1 through K.sub.4 through the gate circuits G.sub.79 to G.sub.82 inclusive and the outputs K.sub.1 through K.sub.4 are fed to one inputs of the arithmetic unit AD shown in FIG. 10. The content of the storage latch R.sub.8 is kept "0" while the dots of the initial seven rows of a character are formed; consequently, to the foregoing one inputs of the arithmetic unit AD are fed (0 0 0 0). Further, the above-mentioned output PS.sub.18 opens the gate circuits G.sub.9 through G.sub.12 shown in FIG. 10 to allow the counting output "3" of the counter C.sub.8 shown in FIG. 14 to be fed to the other inputs of the arithmetic unit AD. Consequently, "3" is produced at the output of the arithmetic unit AD and it is written in the storage latch register R.sub.8 shown in FIG. 15 by the fall of the foregoing output PS.sub.18 and thus the content of the counter C.sub.8 shown in FIG. 14 is held. That the content of the counter C.sub.8 is not directly transcribed to the register R.sub.8 is for the following reason. In case recording of a character is completed only by twice scannings of wire head as in the present example, there is no problem. In the case of several scannings, however, it is necessary that, on the basis of how many times up to the last time the storage contents of the registers M.sub.1 through M.sub.9 have been shifted in a longitudinal direction, it should be known at the time of the following scanning from which row of the bit pattern in the same character of last time which has newly been written from the character generator CG recording must be made; consequently, the newly written bit pattern must be longitudinally shifted by the corresponding number of times.

Upon arrival of the wire head at the start position, the carriage return signal ES shown in FIG. 17 is fed from the wire driving device DR to the counter C.sub.5 through the gate circuit G.sub.65, Mono Multi N.sub.3 and gate circuit G.sub.66 which are shown in FIG. 12, which causes lateral shift pulses of the registers M.sub.1 through M.sub.9 to be produced successively at the output of the counter C.sub.5, so that the bit pattern corresponding to the dot and non-dot of each domain is again transcribed from the character generator CG to the registers M.sub.1 through M.sub.9. The operation at this time is completely the same as that which has been explained in connection with the first operation. Now, the bit pattern stored in the registers M.sub.1 through M.sub.9 corresponds to the dot pattern up to the 7th row in FIG. 3. Therefore, in order to form the dots from the 8th to 14th rows, the storage contents of the registers M.sub.1 through M.sub.9 are shifted three times in a longitudinal direction, then the content in the storage position of register M.sub.3 becomes a bit "1" which corresponds to the dot of the number of the row and the column of the matrix [4, 1] in FIG. 2. Then, by the last output of the counter C.sub.5 shown in FIG. 12, part of the dot pattern corresponding to the 1st, 2nd and 3rd columns of the dot pattern of FIG. 2 is written in the registers M.sub.3 through M.sub.9. Thereafter, the output PS.sub.4 of Mono Multi N.sub.5 which has been triggered by the terminal d.sub.5 of the counter C.sub.5 sets the flip-flop circuit F.sub.2 shown in FIG. 14, the output of which opens the gate circuit G.sub.74 to allow pulses to be produced from the clock pulse generator CL and fed to the counter C.sub.8 through the gate circuit G.sub.76 and further the gate circuit G.sub.77, and at the same time the registers M.sub.1 through M.sub.9 are longitudinally shifted. When three pulses have been counted by the counter C.sub.8, the content "3" of the storage latch R.sub.8 is fed to the coincidence circuit P.sub.5 through the gate circuits G.sub.83 through G.sub.86 shown in FIG. 15. The resulting output PS.sub.19 resets the flip-flop circuit F.sub.2 shown in FIG. 14.

Accordingly, by the aforementioned three pulses through the gate circuit G.sub.77, the contents of the registers M.sub.1 through M.sub.9 have been shifted three times in a longitudinal direction. Further, the content of the storage latch R.sub.6 is set to the counter C.sub.4 by the output PS.sub.19.

In the subsequent operations, printing is made in the same manner as initially stated and the dots of the 8th and the following rows of FIG. 3 are formed, and thus there is formed a clear letter "R" which has been subjected to interpolation with hatching as is shown in FIG. 23.

In the above-mentioned example, the number of wires was seven and the row magnification of a character was "2". In case the magnification is integer multiples of the number of wires such as 1, 7, 14 and 21, printing is made in the following manner; that is, after the wire head had completed the scanning for magnified bits corresponding to one bit in the original pattern and when it has shifted to the following scanning, printing is made from the first of the magnified bits of the bits of the following row in the original pattern. An explanation on this operation is given below.

In the case of the row magnification being "14", the counters C.sub.4 and C.sub.3 shown in FIG. 11 must be changed to tetradecimal counters. Assuming that by twice scannings of the wire head, recording corresponding to 14 dots has been made and thus magnification of one dot in the original pattern has been completed, the counter C.sub.4 now counts "0" and the counter C.sub.3 also counts "0". Since the decoder DC shown in FIG. 15 is so designed as to produce an output when magnification is 1, 7, 14, 21, . . . , the gate circuit G.sub.90 shown in FIG. 15 is kept open. Therefore, when the output of the comparison circuit P.sub.2 shown in FIG. 11 becomes P = Q, an output is produced from the gate circuit G.sub.90 and causes the gate circuit G.sub.88 to be opened. On the other hand, a signal which indicates the last character for a single scanning is programmed in data in advance, so that, after the output of the last character has been produced, the indication signal DC triggers Mono Multi N.sub.9 through the gate circuit G.sub.88 to produce an output PS.sub.20. The output PS.sub.20 resets the counter C.sub.4 through the gate circuit G.sub.52 shown in FIG. 11 and also adds "1" to the counter C.sub.8 shown in FIG. 14. Subsequent operations are the same as those previously explained.

The monostable multivibrators have been used in the foregoing example, but this is for clearly showing the relationship between outputs. Provision of such a circuit does not constitute an essential condition of the present invention; in practice, a timing pulse may be produced on the basis of the reference clock pulse.

In the present example, explanations were made on the case of wire dot printers, but the present invention is not limited thereto; that is, the present invention may also be applied to the case of electronic printers such as electrosensitive printers. What is important is that characters such as letters, numerals and symbols are recorded in the form of a dot matrix. Further, the number of dot-forming wires in the foregoing example was seven, but this constitutes no limitation and a suitable number of such wires may be used provided, of course, that a change in the number of such wires is accompanied by a partial change of the construction in the present example. The row and column magnification in the present example were set to two and three respectively; therefore, as shown in FIG. 23, the number of interpolation dot was one in each made of interpolation. However, increase in magnification is accompanied by an increase in the number of dots for interpolation. This is exemplified by FIG. 20, in which interpolation dots have been shown with a bit pattern of "1" and "0" under the condition of row magnification S = 2 and column magnification T = 3 and the mode shown in FIG. 7B being taken. In FIG. 20, "1" indicates an interpolation dot and "0" indicates an undotted portion.

In the present example, for determining the number of dots for interpolation, dots were experimentally formed and for those giving a high character clearaness, empirical formulae were obtained. However, with respect to the number and position of dots formed, not only in the present example but also in other examples, various cases are considered according to the way of recognizing the character concerned. In the present example, an interpolation dot was included in one range out of two ranges defined by a diagonal line. For example, however, even if an interpolation dot is formed so that it is included also in the other range beyond the diagonal line, the clearness of the character concerned will not greatly lower. In order to form dots in such a manner, the corresponding formulae are prepared and in accordance with these formulae an operational circuit is made, then, in place of the outputs of the operational circuit which are fed to the gate circuits G.sub.131 through G.sub.134 shown in FIG. 17, the outputs of the operational circuit based on the newly prepared formulae are fed to the gate circuits G.sub.131 through G.sub.134.

In another example, the number and position of interpolation dots formed as well as the magnification of a character are programmed in a memory and, with these and also with the outputs U.sub.1 through U.sub.4 of the interpolation detecting circuit U, dots may be formed in the interpolation ranges according to the program.

The point is that the number and position of dots to be formed in the range requiring interpolation may be suitably set as necessary.

As set forth hereinbefore, the present invention forms a dot character such as a dot letter, numeral or symbol which has been enlarged with suitable magnifications in both row and column directions, whereby there can be obtained various shapes of enlarged dot characters having suitable widths in both row and column directions. Furthermore, application of the interpolation methods of the present invention keeps the clearness of the figure of the interpolated characters; that is, even if a character is magnified to a suitable size, the clearness of the character will never be lost.