Current Source Arrangement for Three-Level Emitter-Coupled Logic and Four-Level Current Mode Logic

1. Field of the Invention

This invention relates to an arrangement for an emitter-coupled logic (ECL) gate or for a current mode logic (CML) gate which permits the series gating of several levels of binary logic and, more particularly, relates to a current source arrangement which requires a low voltage drop thereby allowing a sufficient voltage between V.sub.CC and ground to implement three-level ECL and four-level CML.

2. Discussion of Background and Prior Art

As the densities of integrated circuits have increased, the limits of physics, fabrication equipment and process technique are being reached. To further enhance the capability of integrated circuits to perform logic functions, a number of additional steps have been taken or are being considered. A first approach is to use logic schemes of higher order than binary. Thus ternary or quaternary logic has been used. For such higher order logic there are three or four discrete states, respectively, which are permissible on each output line. See, e.g., K. W. Current et al., "Implementing Parallel Counters with Four-Valued Threshold Logic", IEEE Transactions on Computers, v. C-28, No. 3, March 1979, p. 200; and K. W. Current, "High Density Integrated Computing Circuitry With Multiple Valued Logic", IEEE J. of Solid-State Circuits, v. SC-15, No. 1, February 1980, p. 127.

Another approach has been the use of input lines and output lines interchangeably, i.e., input and output lines have been multiplied, thereby reducing the number of pins required on packaged integrated circuits. This has also permitted the use of a generalized integrated circut such as a programmable read only memory (PROM) for a large number of different, specific applications.

A further approach to obtaining enhanced logic performance out of a given integrated circuit or a given amount of silicon has been the use of series gated devices or Cascode logic. Here, at least two levels of binary logic are stacked on each other. At times, three levels are possible. See, e.g., R. J. Scavuzzo, "EFL Logic Arrays", U.S. Pat. No. 4,378,508; and G. L. Baldwin et al., "Modular, High-Speed Serial Pipeline Multiplier for Digital Signal Processing", IEEE J. of Solid State Circuits, v. SC-13, no. 3, p. 400, June 1978. Two level ECL has been used for commercial bipolar integrated circuits such as the Advanced Micro Devices 2901 Bit Slice Microprocessor and the Advanced Micro Devices 29116 16 Bit Microprocessor. In such applications a significant increase in logic is obtained with no increase in production cost. The benefits are obtained because the peripheral devices such as output transistors and input transistors in a given device are shared for each level of logic. More logic functions are performed for a given amount of power consumption, less delay is experienced and less silicon area is required. Similar and additional advantages would accrue if three-level ECL could be accomplished. The barrier to obtaining three-level ECL, as described in detail subsequently, is that power supplies are specified at set voltage values and each level of logic consumes a certain voltage span and the conventional current source takes up so much voltage that only two levels of logic are possible. The voltage span between V.sub.CC and V.sub.EE, (V.sub.CC -V.sub.EE), is accounted for without allowing for an additional level of logic.

It is therefore desirable to provide gate arrangements, and particularly current sources for logic gate arrangements, which allow higher order series level gating to be accomplished.

For a more complete understanding of the circuit arrangement of the present invention, reference may be had to the accompanying drawings which are incorporated herein by reference and in which:

FIG. 1 is a circuit schematic of a dual level ECL gate of the prior art;

FIG. 2 is a partial circuit schematic of a three-level ECL gate which shows in phantom the voltage drop across each logic level;

FIGS. 3(a) and 3(b) are schematic diagrams illustrating voltage sources which can be used to drive the low drop current source arrangement of the present invention;

FIG. 4 is a circuit schematic of a three-level ECL gate employing a voltage source of the type of FIGS. 3(a) and 3(b) to drive a current source arrangement of the present invention;

FIGS. 5(a)-5(c) are schematic diagrams illustrating various ways in which the additional current available from the low drop current source arrangement of the present invention may be utilized; and

FIG. 6 is a schematic diagram of a four-level, series-gated current mode logic circuit.

Three-level ECL or four-level CML are feasible when a low drop current source is incorporated in the series-gated scheme. In a preferred embodiment a low reference voltage is generated and applied to the base of a current source trnsistor. A greater portion of the voltage span between V.sub.CC and ground, up to 4.0 volts, is thereby reserved for the three ECL levels or four CML levels of logic. Conventional power supplies are utilized yet the number of logic functions is increased.

A "gate" in the lexicon of semiconductor electronics is a circuit which performs a specified logical function and is based on an identified circuit principle. For example, the conventional ECL gate performs an OR/NOR logical operation and has a well known configuration. See, e.g, the Motorola MECL Data Book, FIG. 3, pp. 1-4 (1982). Each of the conventional bipolar logic families such as transistor/transistor logic, resistor/transistor logic and injection logic are based on unit circuits or gates which perform a logic function unique to the logic family. Each of these basic building blocks may be used to design integrated circuits that perform a variety of logical operations. Of these various families the one with the highest performance is emitter-coupled logic. With ECL the delay associated with the performance of the logical operation is lower than any other logic family. To enhance performance above this inherent level, however, it is necessary to resort to one of the techniques set out in the Background section.

To optimize the design of circuitry in any given logic family, it is necessary to consider the constraints that exist for devices employing the gates of the logic family. For ECL or CML (see subsequent discussion of distinctions between CML and ECL), the supply voltage V.sub.CC level is specified by convention to have a minimum allowable value of 4.3 volts. This convention is based upon the nominal specification of ECL circuits as operating at 5 volts with a tolerance of .+-.10%. The worst case low voltage from the power supply is thus 5 volts minus 0.1.times.5 volts or 4.5 volts. With large scale integration, however, there may be an on-chip voltage drop of 200 mv between the input power pin and the most remote circuit. Thus, the very worst power condition for the most remote circuit is 4.5 minus 200 mv or 4.3 volts. Thus, a user could provide a power supply which at some time during operation, e.g., under the least favorable operating conditions, supplies a voltage as low as 4.5 volts and for design purposes the most remote circuit would be considered to have 4.3 volts available as V.sub.CC. In addition, ECL or CML parts would typically be specified to operate within the full military temperature range, i.e., from -55.degree. C. to +155.degree. C. The worst case occurs at the low end of the temperature range, since all transistors in the circuit will have high base to emitter voltages, V.sub.BE, on the order of 900 mv. Even at this low temperature a sufficient supply voltage must be provided to allow each transistor to function properly. Thus, as described in detail subsequently, since each level of logic in a series gated or Cascode ECL structure requires that there be at least one V.sub.BE drop, the number of levels is limited by the total voltage span available between V.sub.CC and V.sub.EE after a current source is generated. Finally, in conventional ECL circuits a bandgap reference voltage source is employed which provides a voltage of about 1.6 volts at 25.degree. C. This bandgap reference voltage, typically designated V.sub.CS, is applied to the base of a transistor which serves as the current source. The high level on the base of this transistor results in a current source which requires too high a voltage drop to prevent saturation thereby using an unacceptably high portion of the voltage between V.sub.CC and ground.

To make an ECL gate useful in an integrated circuit it is required that the output have a voltage swing of a minimum magnitude. Thus, this voltage swing or voltage change between the level signifying a logic 1 and the level signifying a logic 0 must be greater than or equal to 750 mv. This requirement stems from the fact that adequate noise immunity is obtained when the signal voltage is plus or minus 375 mv about the reference voltage. This voltage swing for the output is provided by the change in voltage across the resistor connected between the base of the emitter follower and the voltage supply line V.sub.CC, for example resistor 19 in FIG. 1. Thus, even with the optimum design this resistor must be allocated a voltage drop of 750 mv.

As described in the Background section, series gating is a circuit configuration for ECL which permits the stacking of binary logic functions; peripheral devices are shared, device area is conserved and performance is enhanced. A conventional two-level ECL gate in a series gating configuration is shown in FIG. 1. This is commonly called a Cascode arrangement, and has a first level of binary logic implemented by input transistors 10 and 12 which have as their respective inputs the signals A and B and reference transistors 11 and 13 which have as their respective inputs a first reference voltage V.sub.BB1. The second level of binary logic is implemented by at least a first input transistor 14 which has its base connected to signal C and a reference transistor 15 having its base connected to a second reference voltage V.sub.BB2. The emitter follower 16, load transistor 17, current source transistor 18 and resistors 19, 20 and 21 are shared by both binary levels of logic. The outputs of the separate levels are to be taken on either side of diode 21, i.e., one level is taken on line 22 and the output of the other level is taken on line 23. Each output has information in a binary format, i.e., for each output a passband of voltages signifies a digital "1" while another passband of voltages signifies a digital "0". The boundaries for the two passbands for each level will be different so that the information in one level is distinguishable from the information in the other level.

As discussed above, for any 5-volt system there is a minimum voltage span available between V.sub.CC and V.sub.EE which typically is at ground potential. Thus, in the two-level ECL circuit of FIG. 1 there will be at most 4.3 volts available for the first level of binary logic, the second level of binary logic, the voltage swing on the output (resistor 19) and the current source (transistor 18, resistor 21). The bandgap reference voltage V.sub.CS is approximately equal to 1.6 volts because at 25.degree. C. one V.sub.BE plus V.sub.S is approximately 1.6 volts. Therefore, the voltage drop across the current source transistor 18, herein designated V.sub.CSD and shown by the dotted line to be measured between the collector and ground, is as high as 1 volt, thereby leaving only 3.3 volts for the half voltage swing and the levels of logic in a series-gated scheme. This leaves approximately 2.9 volts for the several levels of logic. Since each level has one V.sub.BE drop each requires at least 900 mv, worst case; consequently, only two levels of logic are possible. The voltage swing is a fixed requirement because it is dictated by the voltages required by external circuitry. Therefore, in order to have three levels of logic it is essential to have a low drop current source to leave sufficient voltage for the third level of logic. Or, for CML the low drop current source will permit four levels of logic, as described subsequently with respect to FIG. 6. The circuit arrangement of the present invention provides and utilizes such a low voltage current source. Preferred low voltage references for producing the low drop current sources for the arrangement of the present invention are shown in FIGS. 3(a) and 3(b). Other low voltage references may also be used to drive the arrangement of the present invention. For example, the low voltage bias generator described in the copending patent application of H. Varadarajan, "Bias Circuit For Dynamically Switchable Low Drop Current Source", Ser. No. 550,529, filed on Nov. 9, 1983, may be used to drive a current source in the series-gated scheme.

The circuit arrangement for a conventional three-level ECL gate is shown in FIG. 2. Here, the first level has a reference transistor 28 with a voltage source V.sub.BB1 connected to its base and at least one input transistor 31 whose base is connected to the signal A provided on the emitter of transistor 25 of the previous gate shown to the left of the dotted line; the second level has a reference transistor 29 having a reference voltage V.sub.BB2 connected to its base and at least one input transistor 32 whose base is connected to the signal B provided by the output of a previous gate (not shown); and the third level has a reference transistor 30 having a reference voltage V.sub.BB3 connected to its base and at least one input transistor 33 whose base is connected to the signal C provided by the output of a previous gate (not shown). Each level may have additional input transistors whose bases are connected to other input signals. For maximum utilization of the voltage span, i.e., to allocate the minimum acceptable voltage to each gate, the reference bias voltages whose levels are indicated in phantom will be set as follows: ##EQU1##

As a result the voltage drop across the current source V.sub.CSD will be given by: ##EQU2## The worst condition is experienced at the low end of the military temperature range when V.sub.BE is a maximum, i.e., 900 mv, and V.sub.CC is minimum, i.e., 4.3 volts. V.sub.S is set at 750 mv. Thus, for this condition V.sub.BB1 =3.025 v, V.sub.BB2 =2.125 v, V.sub.BB3 =1.225 v, V.sub.CSD =0.325 v. In order to produce these voltages it is necessary to provide a low drop current source which utilizes 0.325 volts or less. The arrangement of the present invention provides such a low drop current source.

The current source arrangement of the present invention provides the low drop current source by first supplying a low reference voltage V.sub.CSL in place of the conventional bandgap reference voltage V.sub.CS. The low reference voltage V.sub.CSL, shown on the bases of transistors 68, 69 and 70 in FIG. 4, is generated by various means. Preferably it is provided locally so as to not have to distribute it through a network and thereby incur voltage drops in the distribution lines. FIGS. 3(a) and 3(b) illustrate a preferred means to generate a voltage V.sub.CSO which is used to produce the low reference voltage V.sub.CSL which drives the low drop current source. V.sub.CSO is generated by tapping a conventional bandgap reference voltage generator at a nonconventional point. Bandgap reference voltage generators are available on all ECL integrated circuits. See, e.g., A. H. Seidman, Integrated Circuits Applications Handbook, p. 498 (Wiley 1983). They are used to provide a reference voltage V.sub.CS, shown for example on output line 59 in FIG. 3(a), which normally regulates the base voltage of the current source transistor as well as V.sub.BB1 and V.sub.BB2, the signal reference voltages. V.sub.CS is set at 1.6 volts at 25.degree. C. and varies between 1.3 and 1.75 volts over the military temperature range because it is designed to be a few mv over a V.sub.BE plus V.sub.S so as to generate a voltage swing, V.sub.S, across the load resistor which closely matches the current source emitter resistor. It is not possible to produce a low drop current source with such a driving voltage because this voltage is too high to make V.sub.CSD equal to 0.325 volts. However, if a new reference voltage, shown as V.sub.CSO, in FIGS. 3(a) and 3(b) is generated which is one base-to-emitter voltage, V.sub.BE, above V.sub.CS, then a low drop current source can be fabricated which is suitable for producing three-level series-gated ECL or four-level series-gated CML. As described in detail with respect to FIG. 4, V.sub.CSO is one V.sub.BE above V.sub.CS but is stepped down by the component string of transistor 74, resistor 82, diode-connected transistor 69 and resistor 80 so that a low reference voltage V.sub.CSL may be applied to drive the base of current source transistor 68. As shown, V.sub.CSO is available on the emitter of transistor 49 and can be taken on output line 58. In a preferred embodiment, shown in FIG. 3(b), V.sub.CSO is not taken from the bandgap reference voltage generator in a manner that could interfere with the generation of V.sub.CS which may still be required for use in other parts of the integrated circuit. Instead, an additional transistor 60 and resistor 62 are provided as shown between the V.sub.CC line and ground. The base of transistor 60 is connected to node a (the node whose potential is also applied to the base of transistor 49) and since the values of resistors 62 and 54 are chosen to be equal, the current through transistor 60 will mirror the current through transistor 49. Thus, V.sub.CSO may be taken from output line 61 and will be one V.sub.BE above V.sub.CS which is still taken on output line 59. Another approach to generate a low bias to drive a low drop current source is described in the copending H. Varadarajan application referenced above. Typically, a single means for generating V.sub.CSO can fan out to drive a number of means to generate a low reference voltage of the type described subsequently.

In a conventional ECL gate or series-gated structure, the bandgap reference voltage, V.sub.CS, is applied to the base of the current source transistor, e.g., transistor 68 in FIG. 4. However, in the low drop current source shown with the circuit arrangement of the present invention, V.sub.CSO is stepped down so that a low reference voltage V.sub.CSL is applied to the base of current source transistor 68 thereby producing a low drop current source. Basically, the current i.sub.CSO through diode-connected transistor 69 is mirrored in current source transistor 68. As shown in FIG. 4, V.sub.CSO is applied to the base of transistor 74 thereby bringing the voltage level down to that of V.sub.CS as it appears on resistor 82. As with conventional current sources the current through resistor 82 and diode-connected transistor 69 will be well defined because V.sub.CSO is one V.sub.BE above V.sub.CS and was dropped by transistor 74 before going through the resistor and V.sub.BE combination. The current through transistor 69 is mirrored in transistors 68 and 70. Exact mirroring occurs if the transistors are chosen to have emitter areas of the same size. In an alternative embodiment, the emitter area of transistor 69 is a fraction m/n of the emitter area of transistors 68 and 70 so that a unit of current in transistor 69 produces n/m times the current in transistors 68 and 70. Choosing m/n to be less than one, preferably 1/2 or less, conserves the current used (in transistors 69, 74 and resistors 82 and 80) to generate the low voltage drop current source (transistor 68, resistor 79). Since the voltage V.sub.CSL on the base of transistor 68 is controllably low, the voltage drop can be low across transistor 68 and resistor 79. Thus, the voltage drop across the current source (transistor 68, resistor 79) can be designed to be less than 0.325 volts so that adequate voltage is left for three levels of logic to be stacked above transistor 68. Resistors 79 and 81 are not required but ensure better tracking of the mirror current through diode-connected transistor 69, transistors 68 and 70, countering V.sub.BE differences and ground drops. No more than 50-100 mv has to be allocated to resistors 79 and 81 to enhance the tracking of the mirror current, since it is important not to saturate transistors 68 and 70.

Since the low drop current source (transistors 68, resistor 79 in FIG. 4) requires the use of a separate string of components between V.sub.CC and ground (transistor 74, resistor 82, transistor 69 and resistor 80 in FIG. 4), a current i.sub.CSO, through the string is available. The magnitude of i.sub.CSO is determined by V.sub.CSO which is impressed on the base of transistor 74 and influences the current through transistor 74 and resistors 80 and 82. The i.sub.CSO current may be usefully applied. Several uses are shown in FIGS. 5(a) to 5(c). In each case, the component string shown for producing V.sub.CSO (transistor 74, resistor 82, transistor 69 and resistor 80) is connected to additional circuitry which accomplishes a useful function. For example, as shown in FIG. 5(a), V.sub.BB1 and V.sub.BB2 are generated adjacent to the gate in which they are used, thereby eliminating the distribution of these reference voltages which saves the area normally dedicated to distribution lines and avoids distribution line drops. The value of resistor 85 and the sizes of each of the diode-connected transistors 84 and 83 is chosen so that the voltages on their respective emitters is at the appropriate levels for V.sub.BB1 and V.sub.BB2. A second use of i.sub.CSO is shown in FIG. 5(b), where it is used as the load current source for one of the output emitter followers 90 of an adjacent ECL gate having a reference transistor 91 and a voltage swing determining resistor 94. And, in FIG. 5(c) a third use is shown which allows the construction of another level of logic which would be superimposed on the logic performed by the three-level series-gating scheme. Here, the output of the three-level gate is fed to the additional gate which has its own current source and resistor, thus adding more functions to the circuit of FIG. 4.

Current mode logic is a closely related logic form to emitter-coupled logic. It is often confused with emitter coupled logic, with the nomenclature ECL and CML often being used interchangeably. Properly defined, CML is an ECL gate without emitter followers. A four-level CML gate is shown in FIG. 6. Essentially a fourth level of logic has been added to the three levels of FIG. 3. The fourth level consists of input transistor 110 and reference transistor 111 but has no emitter follower. Instead, the output 112 is taken directly from the collector of reference transistor 111. CML is not as widely used as ECL because of saturation problems at high temperatures. Four levels of logic are possible with a CML gate implemented with the low drop current source of the present invention since the output can also be taken from the top collector load resistor and directly fed to the input of the next stage as shown in FIG. 6. The lower levels are, of course, fed from emitter followers and translation diodes. The voltage swing is necessarily restricted to 400-450 mv to prevent saturation of the input transistor. A fourth level would alternately be stacked on input transistors 33, 32 or 31. The four-level gate can produce any Boolean function of four inputs or their combinations by wired AND functions. The key is that current source 113 be a low drop current source which consumes less than 0.1 of the voltage span between V.sub.CC and ground.

The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many variations are possible for the means to generate the low drop current source or for the ways to utilize the current I.sub.CSO. The three-level ECL series-gated embodiment was chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. The principles apply to four-level CML as well. It is intended that the scope of the invention be defined by the claims appended hereto.