Current Source Circuit

The present invention relates to a current source circuit, and more particularly to a current source circuit for producing a plurality of currents with their own weights for use in a digital to analog (D/A) converter, for example.

A D/A converter using R-2R ladder resistors has been fabricated by the IC technology. The D/A converter is based on a principle that a plurality of currents shunted by the R-2R ladder resistors are weighted in accordance with bits, respectively. Since a converting accuracy of the D/A converter using the ladder resistors depends on ratios of resistances of the resistors, it is necessary, for the IC fabrication of the D/A converter, to minimize errors of the shunting resistance ratios by widening the widths of patterns of the shunting resistors. This is undesirable because areas occupied by the shunting resistors on a semiconductor chip are large.

Accordingly, the present invention has an object to provide a current source circuit with a simple construction and of small size well adaptable for the D/A converter, for example, with an arrangement of a plurality of transistors that a plurality of currents with their proper weights are produced from a plurality of current output terminals, respectively.

According to the present invention, there is provided a current source circuit comprising, a first transistor (Q.sub.01) of which the collector is connected to a first power source through a current source; first group transistors of (N-1) (Q.sub.02, Q.sub.03, . . . , Q.sub.0K. . . , Q.sub.0N) of which collector-emitter paths are connected between the emitter of the first transistor and a second power source, successively from the first transistor in series, and of which collectors and bases are connected together, respectively; second group transistors of N (Q.sub.11, Q.sub.21, . . . , Q.sub.K1, . . . , Q.sub.N1) of which the bases are connected with the base of the first transistor commonly, and the respective collectors are connected to the corresponding output terminals (O.sub.1, O.sub.2, . . . , O.sub.K, . . . , O.sub.N), the second group transistors successively corresponding to the first transistor and the first group transistors; means for connecting the emitters of the first order transistor (Q.sub.11) of the second group transistors and the first transistor; and third group transistors of (K-1) of which the collector-emitter paths are connected between emitters of the second group transistor Q.sub.K1 (K=2, 3, . . . , N) and the first group transistors Q.sub.0K (K=2, 3, . . . , N) corresponding to the second group transistor Q.sub.K1.

By setting the emitter areas of the transistors in such a current source circuit to predetermined values, currents with different weights may be produced from the current output terminals, O.sub.1, O.sub.2, . . . , O.sub.K, . . . , O.sub.N, respectively.

FIG. 1 shows a circuit diagram of a current source circuit for producing output currents of 4 bits which is a first embodiment of the present invention;

FIG. 2 is a circuit diagram of a current source circuit with a transistor for correcting a current amplification factor which is a second embodiment of present invention;

FIG. 3 is a circuit diagram of a current source circuit for computer-simulating the second embodiment shown in FIG. 2;

FIG. 4 is a graphical representation of output current characteristics as the results of the computer-simulation of the current source circuit shown in FIG. 3;

FIG. 5 is a graphical representation of output current error characteristics as the results of the computer-simulation of the FIG. 3 current source circuit;

FIG. 6 is a circuit diagram of a third embodiment of a current source circuit for producing output currents of N bits according to the present invention; and

FIG. 7 is a circuit diagram of a fourth embodiment of a current source circuit for producing 4-bit output currents according to present invention .

Refering now to FIG. 1, there is shown an arrangement of a current source circuit for producing a plurality of output currents with weights 1:2:4:8 which is used in a D/A converter of 4 bits. As shown, the current source circuit is comprised of NPN transistors. Transistors of which the collectors are connected to the bases, serving as diodes, that is, a first transistor Q.sub.01 and first group transistors Q.sub.02 to Q.sub.04, are so arranged that the collector-emitter paths of those transistors are connected in a series fashion. The collector of the first transistor Q.sub.01 is connected through a current source I to a positive power source (+E) as a first power source. The emitter of the transistor Q.sub.04 is connected to a negative power source (-E) as a second power source. Those transistors Q.sub.01 to Q.sub.04 cooperatively make up a main current path for the current source circuit. Four second group transistors Q.sub.11, Q.sub.21, Q.sub.31 and Q.sub.41 are connected together at the bases to the base of the first transistor Q.sub.01. The collectors of the transistors Q.sub.11, Q.sub.21, Q.sub.31 and Q.sub.41 are respectively connected to current output terminals O.sub.1 to O.sub.4. The emitter of the transistor Q.sub.11 is connected to the emitter of the first transistor Q.sub.01. As to third group transistors Q.sub.22 ; Q.sub.32 and Q.sub.33 ; and Q.sub.42 to Q.sub.44 ; the bases of the third group transistors are connected to the collectors thereof, respectively. A collector-emitter path of the transistor Q.sub.22 is inserted between the emitters of the transistors Q.sub.21 and Q.sub.02. The collector-emitter paths of the transistors Q.sub.32 and Q.sub.33 are inserted in a series fashion between the emitters of the transistors Q.sub.31 and Q.sub.03. Similarly, the collector-emitter paths of the transistors Q.sub.42 to Q.sub.44 are arranged in a series fashion between the emitters of the transistors Q.sub.41 and Q.sub.04. The transistors Q.sub.22, Q.sub.32 and Q.sub.42 are multi-emitter transistors with two emitters; the transistors Q.sub.33 and Q.sub.43 are multi-emitter transistors with four emitters and the transistor Q.sub.44 is a multi-emitter transistor with eight emitters. In the figure, numerals attached to the emitters represent the numbers of the emitters. When emitter areas of the first transistor Q.sub.01, the first group transistors Q.sub.02 to Q.sub.04 and the second group transistors Q.sub.11, Q.sub.21, Q.sub.31 and Q.sub.41 are each represented by `1`, the emitter areas of the third group transistors Q.sub.22, Q.sub.32 and Q.sub.42 are each represented by `2`, the emitter areas of the transistors Q.sub.33 and Q.sub.43 are represented by `4`, and the emitter area of the transistor Q.sub.44 is represented by `8`.

The operation of the current source circuit shown in FIG. 1 will be described. Let a current supplied from the power source I to this power source circuit be I.sub.0, and current values obtained at voltage output terminals O.sub.1, O.sub.2, O.sub.3 and O.sub.4 be I.sub.1, I.sub.2, I.sub.3 and I.sub.4 respectively. I.sub.1, I.sub.2, I.sub.3 and I.sub.4 are given by an equation (1) ##EQU1##

The equation (1) can be obtained in the following manner. Assume that all the transistors operate in an active region. Then, a voltage V.sub.BE between the base and emitter and a collector current Ic is given by an equation (2)

where V.sub.T is a thermionic voltage, I.sub.s is a reverse saturation current, A is a junction area between the base and emitter, and n is an area ratio of the emitter.

A base-emitter voltage of the first transistor Q.sub.01 is equal to that of the second group transistor Q.sub.11. That is to say, V.sub.BE (Q.sub.01)=V.sub.BE (Q.sub.11). Substituting the equation (2) into this equation and expressing n and I.sub.c by those values of the corresponding transistors ##EQU2## and hence

The sum of the base-emitter voltages of the first transistor Q.sub.01 and the first group transistor Q.sub.02 are equal to the sum of the base-emitter voltages of the second group transistor Q.sub.21 and the third group transistor Q.sub.22. Accordingly, the following equation holds

As in the above case, substituting the euqation (2) into the above equation and expressing n and I.sub.c by those values of the corresponding transistors, we have ##EQU3## and by substituting the relation of I.sub.1 =I.sub.0 of the equation (4) into the equation (5), we obtain

Arranging the above equation with respect to I.sub.2, we have

Further, the sum of the base-emitter voltage V.sub.BE of the transistors Q.sub.01, Q.sub.02 and Q.sub.03 are equal to that of the base-emitter voltages of the transistors Q.sub.31, Q.sub.32 and Q.sub.33. That is, the following equation holds.

Hence, we have ##EQU4## When substituting the equations (4) and (6) into the equation (7), we obtain ##EQU5## Hence, we have

Similarly, the sum of the base-emitter voltages V.sub.BE of the transistors Q.sub.01, Q.sub.02, Q.sub.03 and Q.sub.04 is equal to that of the base-emitter voltages V.sub.BE of the transistors Q.sub.41, Q.sub.42, Q.sub.43 and Q.sub.44. Therefore, the following equation holds

substituting the equation (2) into the above equation and expressing it in terms of the values n and I.sub.c of the corresponding transistors, we obtain ##EQU6## Substituting the equations (4), (6) and (8) into the equation (9), we obtain ##EQU7## Then, arranging the above equation with respect to I.sub.4, we have

As seen from the equations (4), (6), (8) and (10), output currents weighted 1, 2, 4 and 8 can be produced out of the current output terminals O.sub.1 to O.sub.4 respectively when the transistors are arranged as shown in FIG. 1 and the emitter areas of these transistors are selectively set as mentioned above. Since a D/A converter requires a plurality of currents weighted in a geometrical series, for example, the currents I.sub.1, I.sub.2, I.sub.3 and I.sub.4, it is evident that the current source circuit shown in FIG. 1 can be used for the D/A converter. Since the arrangement of this current source circuit is simple and an area on a semiconductor chip occupied by the current source circuit is small, it can be arranged small enough to be used in an IC circuit.

A current source in which errors of the output terminal currents I.sub.1, I.sub.2, I.sub.3 and I.sub.4 shown in FIG. 1 are compensated for will be described referring to FIG. 2. In FIG. 2, like symbols are used for designating like portions in FIG. 1, with omission of the explanation thereof for simplicity. In FIG. 1, the bases of the first transistor Q.sub.01 and the transistors Q.sub.11 to Q.sub.41 of the second group are connected together one another. Therefore, the true collector current I.sub.c (Q.sub.01) of the first transistor of Q.sub.01 shown in FIG. 1 is a current obtained by subtracting the sum of the base currents of the transistors Q.sub.01, Q.sub.11, Q.sub.21, Q.sub.31 and Q.sub.41 from the constant current I.sub.0 flowing through the current source I, and the current I.sub.c (Q.sub.01) is expressed by the following equation (11) ##EQU8## where, .beta. is a common emitter current gain of the first transistor and the second group transistors (NPN type). Assume that the current amplifying factor is "100". Then, it is apparent from the equation (11) that the true collector current I.sub.c (Q.sub.01) of the first transistor Q.sub.01 is 16% smaller than the constant current I.sub.0 of the current source. As mentioned above, since the collector current of the first transistor Q.sub.01 decreases due to the base currents of the transistors Q.sub.01 to Q.sub.41, the base-emitter voltages V.sub.BE of the transistor Q.sub.01 to Q.sub.41 on which the calculation for the currents I.sub.1, I.sub.2, I.sub.3 and I.sub.4 is based, is influenced. Therefore, there occur errors in the output terminal currents I.sub.1 to I.sub.4. In FIG. 2, a second transistor Q.sub.100 is provided in order to remove the errors of the output terminal currents I.sub.1 to I.sub.4. The collector, base and emitter of the second transistor Q.sub.100 are connected to a positive power source (+E) (a first power source), the collector of the first transistor Q.sub.01 and the base of the first transistor Q.sub.01, respectively. As a result, a true collector current I.sub.c '(Q.sub.01) of the first transistor Q.sub.01 in the current source circuit shown in FIG. 2 is obtained by subtracting from the constant current I.sub.0 the quotient when the sum of the output terminal voltages I.sub.1, I.sub.2, I.sub.3 and I.sub.4 is divided by .beta..sup.2, and is given by an equation (12) ##EQU9##

As seen from the equation (12), the error of the collector current of the first transistor Q.sub.01 is no more than 0.16%.

The inventor of the present patent application executed a computer simulation of the current source circuit shown in FIG. 3 by using the known SPICE program in order to check the errors of the output terminal currents I.sub.1 to I.sub.4 ascribed to the above-mentioned current amplifying factor .beta.. In FIG. 3, the transistors Q.sub.11, Q.sub.21, Q.sub.31 and Q.sub.41 were each supplied with voltage of 3.5 V at the current output terminals O.sub.1, O.sub.2, O.sub.3 and O.sub.4, respectively, and the constant current I.sub.0 of the current source I was varied. The results of the simulation of the collector currents I.sub.1, I.sub.2, I.sub.3 and I.sub.4 of the transistors Q.sub.11, Q.sub.21, Q.sub.31 and Q.sub.41 in the simulation are shown in the table 1. Further, relationships between a current source current I.sub.0 (A) obtained from the table 1 and the collector currents I.sub.1, I.sub.2, I.sub.3 and I.sub.4 (A) are illustrated in FIG. 4.

From table 1, the errors of the collector currents of the transistors Q.sub.11, Q.sub.21, Q.sub.31 and Q.sub.41, i.e. the output currents I.sub.1, I.sub.2, I.sub.3 and I.sub.4, can respectively be obtained in accordance with the following equations ##EQU10##

Relations of current source currents I.sub.0 and the errors .epsilon.(I.sub.1), .epsilon.(I.sub.2), .epsilon.(I.sub.3) and .epsilon.(I.sub.4) obtained in accordance with the above equations are tabulated in table 2.

The relationships shown in Table 2, when plotted in a graphical form, are as shown in FIG. 5.

As seen from Table 2, errors of the output currents I.sub.1, I.sub.2, I.sub.3 and I.sub.4 within a practical range of the input current I.sub.0 in the circuit shown in FIG. 2 are of the order of 1% and hence the circuit of FIG. 2 is well adaptable for the D/A converter. When the current source circuit of the present invention is applied for the D/A converter, accuracies of the output currents I.sub.1, I.sub.2, I.sub.3 and I.sub.4, that is, the errors shown in Table 2, change with the number of bits. When the accuracies of the output currents I.sub.1 to I.sub.4 necessary for the D/A converter are defined with 1/2 of the weight of an LSB (least significant bit), those are tabulated in Table 3.

As the number of bits of a D/A converter becomes larger, the accuracies required for the output currents I.sub.1 to I.sub.4 are necessarily more strict, as shown in Table 3. Assume now that the input current I.sub.0 is 100 .mu.A. Since an error of the output current I.sub.1 is 0.69% as shown in Table 2, a D/A converter of 6 bits may be realized by using the current source circuit of the present invention.

Following the explanation of the 4-bit current source circuit referring to FIGS. 1 and 2, a current source circuit of N bits will now be given referring to FIG. 6. In FIG. 6, all of the transistors used are of NPN type. The collector of the first transistor Q.sub.01 is connected through a positive current source I to a positive power source (+E) (a first power source). Inserted between the emitter of the first transistor Q.sub.01 and a negative power source (-E) are a series of collector emitter paths of the first group transistors Q.sub.02, Q.sub.03, . . . , Q.sub.0K, . . . , Q.sub.0N (K=2, 3, . . . , N) of N-1 of which the collectors and the bases are connected together in this order. The transistors Q.sub.01, Q.sub.02, . . . , Q.sub.0K, . . . , Q.sub.0N make up a main current path of the current source circuit. Second group transistors Q.sub.11, Q.sub.21, . . . , Q.sub.K1 , . . . , Q.sub.N1 (K=1, 2, . . . , N) are so arranged that the bases of the second group transistors are commonly connected to the base of the first transistor Q.sub.01, and the collectors thereof are connected to the current output terminals O.sub.1, O.sub.2, . . . , O.sub.K, . . . , O.sub.N, respectively. The emitter of the second group transistor Q.sub.11 is connected to the emitter of the first transistor Q.sub.01. The third group transistors Q.sub.22 ; Q.sub.32 and Q.sub.33 ; Q.sub.K2, Q.sub.K3, . . . , Q.sub.KK and Q.sub.N2, Q.sub.N3, . . . , Q.sub.NN are so arranged that those transistors are connected together at the collector and the base. The emitter-collector path of the third group transistor Q.sub.22 is connected between the emitters of the second group transistor Q.sub.21 and the first group transistor Q.sub.02. The emitter-collector paths of the third group transistors Q.sub.32 and Q.sub.33 are connected in series between the emitters of the second group transistor Q.sub.31 and the first group transistor Q.sub.03. The collector emitter-paths of the third group transistors Q.sub.K2, Q.sub.K3, . . . , Q.sub.KK are connected in series between the emitters of the second group transistor Q.sub.K1 and the first group transistor Q.sub.0K. The emitter-collector paths of the third group transistor Q.sub.N2, Q.sub.N3, . . . , Q.sub.NN are connected in series between the emitters of the second group transistor Q.sub.N1 and the first group transistor Q.sub.0N. The third group transistors Q.sub.22, Q.sub.32, . . . , Q.sub.K2, . . . , Q.sub.N2 are multi-emitter transistors having emitters of 2.sup.1. The third group transistors Q.sub.33, . . . , Q.sub.K3, . . . , Q.sub.N3 are multi-emitter transistors having emitters of 2.sup.2. The third group transistor Q.sub.KK is a multi-emitter transistor having emitters of 2.sup.K-1. The transistor Q.sub.NN is a multi-emitter transistor having emitters of 2.sup.N-1. In other words, when the emitter areas of the first transistor Q.sub.01, the first group transistors Q.sub.02 to Q.sub.0N, and the second group transistors Q.sub.11 to Q.sub.N1 are expressed each by "1", the emitter areas of the transistors having the emitters of 2.sup.1, 2.sup.2, . . . , 2.sup.K-1, . . . , 2.sup.N-1 are 2.sup.1, 2.sup.2, . . . , 2.sup.K-1, . . . , 2.sup.N-1, respectively. To further describe the third group transistors, when K is 2, 3, . . . , N, the number of the transistors of which the collector-emitter paths are connected in series between the emitters of the second group transistor Q.sub.K1 and the first group transistor Q.sub.0K is K-1 (Q.sub.K2, Q.sub.K3, . . . , Q.sub.KK), and the number of emitters are 2.sup.1, 2.sup.2, . . . , 2.sup.K-1, respectively. Since K may take any one of those numerals 2, 3, . . . , N, the total number of the third group transistors is expressed by ##EQU11## The circuit shown in FIG. 6 contains the second transistor Q.sub.100 for correcting the output current already described referring to FIG. 3, and a third transistor Q.sub.101 for the same purpose. The collector, base and emitter of the second transistor Q.sub.100 are connected to the first power source, the emitter of the third transistor Q.sub.101 and the base of the first transistor Q.sub.01, respectively. The collector and base of the third transistor Q.sub.101 are connected to the collector of the second transistor Q.sub.100 and the collector of the first transistor Q.sub.01, respectively. The operation of the current source circuit shown in FIG. 6 will easily be understood by skilled persons in the art when carefully reading the explanation of FIG. 1. The current values derived from the output terminals O.sub.1, O.sub.2, O.sub.3, . . . , O.sub.K, . . . , O.sub.N are expressed by I.sub.0 .times.2.sup.0, I.sub.0 .times.2.sup.1, I.sub.0 .times.2.sup.2, . . . , I.sub.0 .times.2.sup.K- 1, . . . , I.sub.0 .times.2.sup.N-1 in geometrical progression, for the current value I.sub.0 of the current source I.

Another embodiment of a current source circuit according to the present invention will be described referring to FIG. 7. Differences of the embodiment shown in FIG. 7 from that in FIG. 1 is that the second group transistor Q.sub.31 and the third group transistor Q.sub.33 have each two emitters, the second group transistor Q.sub.41 has two emitters, and the third group transistor Q.sub.44 has four emitters. The operation and effects of the embodiment shown in FIG. 7 are exactly the same as those of the FIG. 1 embodiment. The reason why those are equal to each other will be described referring to Table 4.

As seen from Table 4, the emitter area product of the circuit Q.sub.31 -Q.sub.32 -Q.sub.33 is 1.times.2.times.4 in FIG. 1 and 2.times.2.times.2=8 in FIG. 7. That is, the product of areas of those circuits are equal to each other. The product of areas of the circuit Q.sub.41 -Q.sub.42 -Q.sub.43 -Q.sub.44 is 1.times.2.times.4.times.8=64 in FIG. 1 and 2.times.2.times.4.times.4=64 in FIG. 2 and those are equal to each other. Therefore, the relations I.sub.1 =I.sub.0 ; I.sub.2 =2I.sub.0 ; I.sub.3 =4I.sub.0 ; and I.sub.4 =8I.sub.0 are obtained in accordance with the equations shown in Table 4. According to the current source circuit of the present embodiment, the manufacturing process of the transistors is simple. In the embodiment shown in FIG. 6, the number of the emitters of the second and third group transistors can be controlled through the calculation in accordance with Table 4.