Digital Differential Phase Shift Keyed Demodulator

This invention relates to an apparatus and method for demodulating a differential phase shift keyed signal.

Phase shift keying (PSK) is a form of modulation where the phase of a carrier is changed by binary data, and demodulation is accomplished by comparing the received signal to a fixed reference. In binary phase shift keying (BPSK), the modulator output has two phases. It is either in-phase or 180.degree. out-of-phase, with the local oscillator, depending on whether the input is a logic one or zero. To demodulate a BPSK signal it is necessary for the demodulator to establish a reference phase angle. This reference is compared to the phase angle of the received signal to determine whether the received signal represents a one or a zero.

An alternative to PSK is differential phase shift keying (DPSK). In a DPSK signal the information is contained in the differential phase between consecutive bit intervals. With this technique, the received signal is demodulated by comparing the carrier signal phase in each bit interval with the phase during the immediately preceding bit interval, the latter serving as a reference. Binary DPSK, which is the most popular form of DPSK, uses two phase angles to represent the data. Although DPSK is easier to implement than PSK, DPSK requires a greater signal-to-noise ratio to achieve the same error rate as PSK.

Quadrature DPSK modulation (the use of eight phase angles to represent data) is discussed in U.S. Pat. No. 3,368,036, entitled "Demultiplexing and Detecting System for Predicted Wave Phase-Pulsed Data Transmission System" issued to R. C. Carter et al. The patented invention permits two bits of binary data to be transmitted and received per bit interval because with quadrature DPSK the carrier signal in a given bit interval can assume any one of four different phases with respect to the immediately preceding bit interval.

FIG. 1 illustrates a prior art DPSK demodulator that uses a delay element (.DELTA.t) at the intermediate frequency. The delay element must be equal to one bit period and must represent a whole number of carrier cycles. The output of the delay element is multiplied or mixed with the undelayed intermediate frequency signal to synchronously demodulate the signal. In mathemathical terms the intermediate frequency signal will be +sin .omega..sub.c t or -sin .omega..sub.c t. Since the mixer in FIG. 1 produces the product of two successive values of the intermediate frequency input signal, the output signal thereof will be sin.sup.2 .omega..sub.c t=(1/2)(1-cos 2.omega..sub.c t) when two consecutive phases are the same, or -sin.sup.2 .omega..sub.c t=-(1/2)(1-cos 2.omega..sub.c t) when two consecutive phases are different. The low-pass filter elminates the double-frequency component, yielding either a positive or negative dc value. The dc value is then one-bit-quantized by a zero crossing detector or comparator. This detection scheme offers simplicity in concept but is extremely difficult to implement because the delay element must have a very accurate delay, no more than .+-.10 degrees of phase shift at the intermediate frequency.

FIG. 2 illustrates another prior art DPSK detector wherein the intermediate frequency signal is reduced to quadrature baseband components, labeled I and Q; the baseband components are then converted to a phase angle via an arc-tangent function. The result from the arc-tangent function is delayed and compared to determine the phase difference, which represents the desired data. The analog/digital interfaces are shown in FIG. 2 as occurring after baseband conversion and filtering so that the arc-tangent function can be done in a primarily digital circuit.

Another prior art DPSK detector is illustrated in FIG. 3. In the FIG. 3 detector the arc-tangent function, which is quite difficult to implement, is eliminated in favor of a delay, multiply, and add circuit that provides simpler circuitry with substantially similar performance to the FIG. 2 embodiment. Both of the FIG. 2 and FIG. 3 embodiments can be characterized as amplitude-quantized in that they are sensitive to the amplitudes of the quadrature baseband components. Thus for digital processing a pair of analog-to-digital converters are necessary to implement the circuits.

The DPSK demodulator of the present invention is distinguishable from the prior art discussed above in the manner in which the sampled estimates of signal phase are converted to digital form, and the relative simplicity of the digital circuitry required for the phase comparisons. Also, relative to the embodiments employing analog time delay circuits, the demodulator of the present invention can operate at variable data rates because the delay needed to enable the phase comparisons is attained using flip-flops rather than analog delay elements. Further, depending on the delay time desired, it may not be possible to implement analog delay lines on an integrated circuit, thus the present invention is capable of being embodied in one or more integrated circuits.

The detector or demodulator of the present invention mixes the incoming intermediate frequency signal to baseband with three local oscillator signals having 120.degree. phase differences. After low-pass filtering, the baseband signals are one-bit quantized via zero crossing detectors (or comparators) to produce three binary bits describing the carrier signal phase angle in 120.degree. increments. Each of these bits is then DPSK-detected through a delay and modulo-2 multiplication prior to the phase decision. Simple majority logic then determines whether the phase difference from bit to bit represents 0.degree. or 180.degree..

The present invention may be better understood, and the further advantages and uses thereof more readily apparent when considered in view of the following detailed description of exemplary embodiments, taken with the accompanying figures in which:

FIGS. 1 through 3 illustrate prior art DPSK demodulators;

FIG. 4 illustrates a DPSK demodulator constructed according to the teachings of the present invention;

FIGS. 5A and 5B illustrate the input and output signals for the matched filter of FIG. 4;

FIG. 6 is a phase diagram illustrating the various codes produced by the DPSK demodulator of FIG. 4 and the phase angles represented by those codes;

FIG. 7 is a schematic representation of the three-phase oscillator shown in FIG. 4; and

FIGS. 8A and 8B illustrate a synchronization circuit and an attendant truth table for the DPSK demodulator of FIG. 4.

FIG. 4 is a schematic representation of a DPSK demodulator 10 constructed according to the teachings of the present invention. The DPSK demodulator 10 is different from the prior art designs in the manner in which sampled estimates of the signal phase are converted to digital form and the relatively simple digital circuitry required for the phase comparison process. The demodulator is an improvement over the prior art DPSK demodulators that use analog delay elements or that digitize the input signal and use complex signal processing algorithms. The DPSK demodulator 10 can operate at variable data rates because the delay needed to enable phase comparisons at the beginning and end of a bit interval is accomplished by flip flops rather than analog delay elements.

FIG. 5A shows a representative noise-free DPSK signal waveform envelope at the input to a matched filter 12 of FIG. 4. The input signal consists of a sinusoid at a frequency f.sub.c whose phase has been inverted at periodic intervals to modulate the data (the information signal) onto the carrier signal. The phase reversals are indicated in FIG. 5A by the 0.degree. and 180.degree. indicators. In the signal of FIG. 5A the phase is inverted at the beginning of a data interval when the data bit for that interval is a one and the phase remains the same as in the previous interval when the data bit for that interval is a zero. If the opposite convention is used (phase inversion on a zero rather than a one), the DPSK demodulator 10 will still provide correct demodulation. The following discussion of the DPSK demodulator 10 assumes signal inversion when the data is a one, even though the DPSK demodulator 10 operates correctly with either convention, provided that the output information signal is selected from the appropriate output terminal.

FIG. 5B shows the corresponding noise-free output signal from the matched filter 12. When a phase reversal occurs in the input signal to the matched filter 12, the energy storage elements thereof cause the output amplitude to decay to zero and then return back to the peak amplitude, of the opposite phase. It is well known that the optimum method for demodulating a DPSK signal is to compare the phases of the matched filter output signal at the end of each bit interval. These points are designated in FIG. 5B as X.sub.0, X.sub.2, X.sub.4, X.sub.6, X.sub.8, X.sub.10, and X.sub.12. For example, if the phases at X.sub.2 and X.sub.4 are compared and the phase difference is greater than 90.degree., the data bit (or information signal) for the interval between X.sub.2 and X.sub.4 is a one. If the phase difference is less than 90.degree., the data bit is a zero. Noise disturbs the phase of the output signal from the matched filter 12 so that a statistical distribution of phase differences may be observed. The noise causes phase jitter that can disrupt the phase difference between X.sub.2 and X.sub.4, producing an erroneous data bit.

Returning to the DPSK demodulator 10 of FIG. 4, the output signal from the matched filter 12 is fed through a buffer amplifier 14 to three mixers 16, 18, and 20. The mixers 16, 18, and 20 are each responsive to a reference signal from a three-phase oscillator 22. As indicated on FIG. 4, the mixer 16 is responsive to a signal cos (.omega..sub.c t) from the three-phase oscillator 22; the mixer 18 is responsive to a signal cos(.omega..sub.c t+120.degree.) from the three-phase oscillator 22; the mixer 20 is responsive to a signal cos(.omega..sub.c t-120.degree.) from the three-phase oscillator 22. The three signals from the three-phase oscillator 22 have the same frequency, but different phase angles of 0.degree., +120.degree., and -120.degree.. The resultant signal from the mixer 16, which includes a dc term and a double-frequency term, is input to a low-pass filter 24. Similarly, the resultant signals from the mixers 18 and 20 are input respectively to low-pass filters 26 and 28. The low-pass filters 24, 26, and 28 reject signal components in the vicinity of twice the carrier frequency, leaving only the dc value.

The output signal from each of the low-pass filters 24, 26, and 28 is provided as an input to a non-inverting input terminal of a comparator (or a zero-crossing detector) 30, 32, and 34, respectively. The inverting input terminal of each comparator 30, 32, and 34 is connected to ground. Each comparator 30, 32, and 34 compares the dc value from the respective low-pass filter with zero. The output signal from the comparator 30 is high if the instantaneous phase of the signal from the matched filter 12 is between -90.degree. and +90.degree.. The output signal from the comparator 30 is low if the instantaneous phase of the input signal is between 90.degree. and 270.degree.. That is, the comparator 30 provides an indication that is high (a logical one) if the phase is to the right of the vertical line shown in the XY vector phase plane of FIG. 6. This result is illustrated by the following equations, where cos(.omega..sub.c t) is the reference signal and cos (.omega..sub.c t+45.degree.) is the signal from the matched filter 12. The mixer 16 produces an output signal ##EQU1## The double frequency terms in equation (1) are removed by the low pass filter 24, leaving a dc value of 0.353. This value is applied to the non-inverting input terminal of the comparator 30 to produce a high signal at the output terminal thereof.

For all phase angles between -90.degree. and +90.degree. (i.e., to the right of the vertical line in FIG. 6) the result of the computations shown above is between 1 and 0. Thus, when the phase angle is to the right of the vertical line in FIG. 6 the comparator 30 has a positive value at its non-inverting input terminal and produces a high output signal. When the signal phase is to the left of the vertical line in FIG. 6 the comparator 30 has a negative value at its non-inverting input terminal and produces a low output signal. If the phase should fall exactly on the vertical line of FIG. 6 the signal to the non-inverting input terminal of the comparator 30 is zero and the output signal is indeterminate. However, the probability of this occurance is essentially zero, so the impact on the error rate of the demodulator 10 can be neglected.

In a similar fashion, two other decision lines are created by the comparators 32 and 34. See FIG. 6. The comparator 32 produces a high output signal when the phase angle is above the decision line running from 30.degree. to 210.degree.. The comparator 34 produces a high output signal when the phase angle is below the decision line that runs from 330.degree. to 150.degree.. As a result, the output of the comparators 30, 32, and 34 is a three-bit code that indicates in which one of the six sectors the instantaneous phase is located. The sectors and the corresponding three-bit codes are shown in FIG. 6. The bits in the code from left to right correspond to the comparator outputs 30, 32, and 34.

The output signals from the comparators 30, 32, and 34 are input to flip-flops 38, 40, and 42, respectively. The flip-flops 38, 40, and 42 are clocked at twice the data rate as indicated. Therefore, the three-bits appearing at the outputs of the flip-flops 38, 40, and 42 represent the phase of the filtered DPSK signal at times X.sub.0, X.sub.1, X.sub.2, X.sub.3, etc. The output signals from the flip-flops 38, 40, and 42 are connected to the inputs of a second set of flip-flops designated 44, 46, and 48. The flip-flops 44, 46, and 48 are clocked at the data rate, as shown. The output signals from the flip-flops 44, 46, and 48 represent the phase of the filtered DPSK signal at X.sub.0, X.sub.2, X.sub.4, etc. The output signal from the flip-flop 38 is connected to a first input terminal of an exclusive OR gate 50; the output signal from the flip-flop 44 is connected to a second input terminal thereof. The output signal from the flip-flop 40 is connected to a first input terminal of an exclusive OR gate 52; the output signal from the flip-flop 46 is connected to a second input terminal thereof. The output signal from the flip-flop 42 is connected to a first input terminal of an exclusive OR gate 54; the output signal from the flip-flop 48 is connected to a second input terminal thereof.

The output terminals from the exclusive OR gates 50, 52, and 54 are connected to a majority logic gate 56. The majority logic gate 56 produces a high output signal if the three input bits contain two or three logical ones. The output signal from the majority logic gate 56 is zero if the three input bits contain a single logical one or no logical ones. Thus, the output signal from the majority logic gate 56 is a comparison of the filtered DPSK signal phase at two points in time and represents the information signal that modulated the carrier signal at the transmitter. As will be discussed further herein below, there is also sufficient information in the recovered data signal to synchronize the data clock.

In another embodiment where it is not desired to produce a clock synchronization signal in addition to demodulating the input signal, the flip-flops 38, 40, and 42 are unnecessary. To demodulate the input signal, it is only necessary that the bit decisions be made at the beginning and end of each bit interval. The flip-flops 44, 46, and 48 are sufficient to accomplish this.

As discussed above, the output signals from the comparators 30, 32, and 34 represent a three-bit code indicating the sector of FIG. 6 where the instantaneous phase of the filtered DPSK signal lies. The flip-flops 38, 40, and 42 are clocked at twice the data rate so that the output signal from each of these flip-flops is the coded phase angles at X.sub.0, X.sub.1, X.sub.2, X.sub.3, etc. in FIG. 5B. Because the flip-flops 44, 46, and 48 are clocked at the data rate, their outputs represent the instantaneous phases at times X.sub.0, X.sub.2, X.sub.4, etc. The time alignment of the output signals from the flip-flops 38, 40, 42, 44, 46 and 48 is shown in Table 1 below. The times in the first column of Table 1 denote half-bit time intervals, and refer to the instantaneous time designated by the subscripts of "X" in FIG. 5B.

In the preferred embodiment, data decisions (i.e., determination of the transmitted information based on phase reversals) is derived from comparison of the output signals from the flip-flops 38, 40, 42, 44, 46, and 48 during the even time intervals shown in Table 1. Clock synchronization is derived during odd intervals. For example, at time 4 signals representing the phase at X.sub.2 and X.sub.4 (see FIG. 5B) appear at the output terminals of the flip-flops 38, 40, 42, 44, 46, and 48. Referring to FIG. 5B, the phase of the filtered DPSK signal at X.sub.2 is 0.degree., so X.sub.2 is coded as 100 as shown in FIG. 6. Similarly, the phase for X.sub.4 is 180.degree., so X.sub.4 is represented by the code 011. During the time 4, X.sub.2 and X.sub.4 are input to the exclusive OR gates 50, 52, and 54. The output signal from the exclusive OR gates 50, 52, and 54 is 111, which is input to the majority logic gate 56. The majority logic gate 56 decodes this information and produces a one bit at the output terminal thereof. A one bit is the correct data bit for the interval between X.sub.2 and X.sub.4 as shown in FIG. 5B. The correct data bit is also obtained from the majority logic gate 56 when noise causes a single bit error (and also some multiple bit error patterns) in the phase at X.sub.2 or X.sub.4. This is indicated in Table 2 below where erroneous bits are underlined.

The first row of Table 2 shows the error-free case described above. The second row shows the results when the first bit of X.sub.2 is incorrect due to noise in the received signal. Noise can cause phase jitter that can change the ideal-case 180.degree. phase difference between times X.sub.2 and X.sub.4. There are many other possibilities where the phase of the filtered DPSK signal can fall into an erroneous sector that is separated by a single bit from the correct sector in FIG. 6. The correct data bit is obtained, however, provided that the noise is not large enough to cause certain multiple-bit error patterns in the phase codes shown in FIG. 6.

Returning to FIG. 4, note that the majority logic gate 56 includes AND gates 90, 92, and 94. The AND gate 90 is responsive to the output signals from the exclusive OR gates 50 and 52. The AND gate 92 is responsive to the output signals from the exclusive OR gates 52 and 54. The AND gate 94 is responsive to the output signals from the exclusive OR gates 50 and 54. An OR gate 96 is responsive to the output signal from the AND gate 90, the AND gate 94, and the AND gate 92. The data signal is produced at the output terminal of the OR gate 96. The output signal from the majority logic gate 56 represents the bit occurring most frequently in the three-bit sequence provided as a an input thereto.

A preferred embodiment for the three-phase oscillator 22 is shown in FIG. 7. The three-phase oscillator 22 comprises three identical subsections connected in a ring configuration, with each subsection consisting of an inverting amplifier and an RC phase shift circuit. The inverting amplifiers are identified by reference characters 72, 74, and 76; the RC phase shifts circuits are identified by reference characters 78, 80, and 82. The three-phase oscillator 22 oscillates at a frequency where the total phase shift around the ring is 360.degree., meaning that the phase shift for each subsection is 120.degree.. If the signal at the output of the inverting amplifier 72 is taken as the 0.degree. reference, then the signal at the output terminal of the second inverting amplifier 74 is plus 120.degree., and the signal at the output terminal of the inverting amplifier 76 is -120.degree.. These three output signals are amplified by, respectively, buffer amplifiers 84, 86, and 88 to produce the three output signals shown. A variable resistor 89 adjusts the frequency of the three-phase oscillator 22. As is well known by those skilled in the art, the reference signals shown in FIGS. 4 and 7 can also be derived using a local oscillator and phase shifting devices to provide the phase shifted signals.

A synchronization circuit 100, for synchronizing the data clock of the demodulator 10 is illustrated in FIG. 8A. An error signal is obtained in the synchronization circuit 100 by comparing the phase of the filtered DPSK signal at points midway between data decisions with the phase at the data decision points. Referring to FIG. 5B, when the data clock is properly timed the phase at X.sub.3 is indeterminate. However, when the clock is early the phase at X.sub.3 tends to agree with the phase at X.sub.2. When the clock is late, the phase at X.sub.3 tends to disagree with the phase at X.sub.2. Therefore, a timing error signal can be obtained by comparing the phase at X.sub.3 with the phase at X.sub.2.

Referring to Table 1, the output signal from the majority logic gate 56 during time 3 represents a comparison of the phase at X.sub.3 with the phase at X.sub.2. Thus, the output signal from the majority logic gate 56 tends to be high for this interval when the timing is late. Similarly, the output signal tends to be low when the timing is early. When no phase transition occurs in the input DPSK signal, the timing information is not available and this is indicated by the fact that the data bit is a 0.

Flip-flops 120, 122 and 124 (see FIG. 8A) operate to provide the appropriate timing signals for synchronizing the data clock. The flip-flops 120 and 122 are responsive to the output signal from the majority logic gate 56 (i.e., the data signal). The flip-flop 120 is clocked by the data clock so that the output signal at the Q output terminal thereof represents the information signal (i.e., the signal at times X.sub.0, X.sub.2, X.sub.4, etc.). The flip-flop 122 is clocked by an inverted data clock (via an inverter 126) so that the output signal at the Q terminal thereof represents the data signal at the mid-bit times (i.e., the signal at times X.sub.1, X.sub.3, X.sub.5, etc.). The flip-flop 124 is clocked at the data rate and is responsive to the output signal from the flip-flop 122 for delaying the signal input thereto. Thus, the flip-flops 122, 124, and 126 time-align the signals at times X.sub.0, X.sub.2, X.sub.4, etc. with the signals at times X.sub.1, X.sub.3, X.sub.5, etc.

A decision direction logic circuit 102 of the synchronization circuit 100 combines the data decision (at times X.sub.0, X.sub.2, X.sub.4, etc. from the flip-flop 120) at an A input terminal thereof with the mid-bit phase comparison decision (at times X.sub.1, X.sub.3, X.sub.5, etc. from the flip-flop 124) at a B input terminal thereof to produce two control signals for controlling a voltage-controlled oscillator 104. The control signals are designated C and D. As indicated in the truth table of FIG. 8B, when the A input terminal (data) is a 0, the C output terminal is 0 and the D output terminal is 1. The C and D output terminals offset one another so no speed-up or slow-down of the voltage controlled oscillator 104 occurs. This is necessary because when the data bit (at the A input terminal) is a 0, no phase transition of the DPSK signal has occurred and therefore, no timing information is available. When the A input terminal is a 1 and the B input terminal is a 0, the C and D output terminals are both zeros, tending to cause a slowdown of the voltage-controlled oscillator 104. This is appropriate because a mid-bit decision of zero indicates that the data clock timing is early. If the A and B input terminals are both 1, then the C and D output terminals are both 1, causing a speedup of the voltage-controlled oscillator 104. An RC network 106 connected between the output terminal of the decision directional logic circuit 102 and the voltage-controlled oscillator 104 forms a loop filter. The loop filter smooths the input signal to the voltage-controlled oscillator 104 so that the timing is not substantially affected by noise and maintains proper clock timing for short intervals when transitions are absent from the DPSK waveform, for example at time interval X.sub.5 illustrated in FIG. 5B.

The voltage controlled oscillator 104 operates at twice the data rate because in the embodiment of FIG. 4 the flip-flops 38, 40, and 42 require timing signals at twice the data rate. In one embodiment of the present invention, the voltage-controlled oscillator 104 operates over a range of desired data rates from 200 through 500 Mbit/sec. These data rates are accomplished by appropriate selection of the value for a resistor 108 or by providing an external control voltage to select the center frequency of the voltage-controlled oscillator 104 for different data rates. The external control is designated the data rate control input in FIG. 8A. The output signal from the voltage-controlled oscillator 104 is input to a divide-by-two circuit 110 to provide a data frequency clock signal. In one embodiment the divide-by-two circuit is implemented using a flip-flop.

While I have shown and described several embodiments in accordance with the present invention, it is understood that the same is not limited thereto but is susceptible of numerous changes and modifications as known to a person skilled in the art, and I therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.