Offset QPSK Demodulator and Receiver

This invention relates to a demodulator or receiver for digital data transmission. Specifically, the invention is an offset QPSK demodulator and digital receiver suitable for low cost implementation using digital integrated circuit techniques. Applications involve remote control, scrambled digitized speech and secure data transmission.

QPSK, or quadriphase shift keying, has been recognized as an efficient format for transmitting digital data, both in terms of reduced bandwidth and minimum transmitter power. The bandwidth requirements are less than for phase shift keyed (PSK) modulation, and are generally better than frequency shift keyed (FSK) modulation.

Offset QPSK in particular is equivalent to minimum frequency shift keying (MSK) which is an "optimal" format for FSK. See Mathwich et al., "The Effect of Tandem Band and Amplitude Limiting on the Eb/No Performance of Minimum (Frequency) Shift Keying (MSK), "IEEE Transactions on Communications, Vol. COM-22, No. 10, October 1974, pp. 1525-39. Offset QPSK has the advantage that, unlike conventional QPSK, filtered offset QPSK retains its band-limited spectrum after handlimiting. In other words, even though offset QPSK may be generated and demodulated using linear and synchronous techniques, it is fully compatible with Class C amplifiers and FM radio RF circuits. See Simon & Smith, "Offset Quadrature Communications with Decision Feedback Carrier Synchronization," IEEE Transactions on Communications, Vol. COM-22, No. 10, October 1974, pp. 1576-84.

There are two popular circuits for demodulating offset QPSK, characterized by the method used for obtaining a coherent phase reference corresponding to the suppressed carrier. These circuits are known as the times four/divide by four and the Costas or data estimation loop. In the times four/divide by four loop, a replica of the received QPSK signal is frequency multiplied by four and mixed with the coherent reference which is also multiplied by four. The mixer devices an output signal which is coupled through a low pass filter to control the frequency of the coherent reference. By frequency multiplying the coherent reference by four in a feedback loop, there is effectively a frequency division by four to the multiplier from the receiver. The divide by four circuit is usually a phase locked loop with a loop bandwidth of 0.1% to 1% of the data rate. See Rhodes, U.S. Pat. No. 4,313,205 (Jan. 26, 1982).

In the data estimation loop, a Costas loop is formed by supplying the output signals of the orthogonal channel low pass filters to separate hard limiters. The output signals of the hard limiters are cross multiplied with the output signals of the low pass filters to derive estimates of the transmitted data. The estimates are compared to derive an error signal that is coupled to a loop filter, which in turn controls the phase of the coherent reference. See Ryan et al. U.S. Pat. No. 4,085,378 issued Apr. 18, 1978, and Ryan U.S. Pat. No. 4,092,606 issued May 30, 1978.

Although the prior art circuits perform their intended function of demodulating offset QPSK, they require analog multipliers and associated circuits which do not lend themselves to low cost integrated circuit implementation. For the effective bandwidth of the times four/divide by four or the Costas loop to be relatively independent of received signal level, automatic gain control is also required.

The general aim of the present invention is to provide an offset QPSK demodulator and receiver suitable for low cost integrated circuit implementation.

Another object of the invention is to provide an offset QPSK demodulator which derives both carrier phase and data or symbol phase control signals from hard limited inphase and quadraphase channels so that automatic gain control is not required.

Still another object is to provide an MSK receiver which also may employ spread spectrum techniques so that the channel has increased immunity to continuous wave (CW) interference.

Yet another object of the invention is to provide an improved hybrid and balanced modulator circuit for deriving the inphase and quadraphase channels.

And still another object of the invention is to provide an economical method and system for transmitting in excess of 10 kilobits per second of remote control, paging, or scrambled digitized speech data within less than the 10 kilohertz bandwidth of conventional mobile or point-to-point FM communication channels, the method and system being compatible with existing class C FM transmitters.

The foregoing and other objects are achieved in accordance with the present invention by providing a digital demodulator which samples both the inphase and the quadraphase channels at the data rate. The "control" samples between the "data" samples are processed to derive both carrier phase and data or symbol phase control or error signals. If the "data" samples immediately preceding and immediately following a "control" sample differ in their logic state, (it being assumed that the "data" samples are hard limited to a logical 0 or a logical 1), a carrier phase control signal is generated from the "control" sample by conditionally reversing the sign or polarity of the "control" sample depending on the logic state of the "data" sample from the other channel sampled coincident with the "control" sample, and a data or symbol phase control signal is generated from the "control" sample by conditionally reversing the sign or polarity of the "control" sample depending on the direction of the transition between the "data" samples immediately preceding and immediately following the "control" sample. This demodulation method is operative even if the "control" samples are hard limited. In this case, although there is a high probability that for each "control" sample generating control signals, one of the control signals will be erroneous, the control signals will drive the carrier phase and data or symbol phase loops in a cooperative fashion so that both carrier phase and data or symbol phase are acquired.

In one preferred embodiment suitable for high speed data communication, D type flip-flops perform the sampling, exclusive-OR gates provide the conditional polarity or sign reversal, and tristate drivers are enabled to activate the phase control signal outputs only upon transitions of the "data" samples.

In another preferred embodiment for low data rate applications such as remote control, a microcomputer being interrupted at the data rate by a programmable timer or counter has sufficient time to perform the demodulation process. The programmable timer or counter provides a phase-controlled data clock, and a crystal oscillator pulled by a varactor driven by a "type-II" loop filter provides a phase-controlled local oscillator. The quadrature phase relation of the inphase and quadraphase channels is ensured by a hybrid and balanced modulator circuit using a center tapped or balanced RF or IF transformer and a ring of four switching elements such as MOS FETS; individual ones of the four switching elements are sequentially enabled by respective decoded outputs of a counter clocked at twice the frequency of the suppressed carrier. If a two-stage binary counter is used, an exclusive-OR gate may be inserted between the binary counter and the decoder so that a pseudorandom sequence can effectively modulate the suppressed carrier to permit the reception of spread spectrum offset QPSK.

Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 is a schematic diagram of one embodiment of the demodulator according to the present invention;

FIG. 2 is a timing diagram illustrating that the embodiment of FIG. 1 can simultaneously acquire carrier phase and data or symbol phase;

FIG. 3 is a schematic diagram of an embodiment of the invention using a microcomputer interrupted at the data rate by a programmable counter, and having an improved hybrid and balanced modulator circuit and having means for permitting the reception of spread spectrum transmissions.

While the invention is susceptible of various modifications and alternative constructions, certain preferred embodiments have been shown in the drawings and will be described below in considerable detail. It should be understood, however, that there is no intention to be limited to the specific forms described but, on the contrary, the intention is to cover all modifications, alternative constructions and equivalents falling within the spirit and scope of the claims.

Turning now to the drawings, there is shown in FIG. 1 a schematic diagram of one embodiment of an offset QPSK demodulator according to the present invention. The demodulator receives the QPSK signal S which is, for example, mathematically described as:

where w is the frequency of the suppressed carrier in radians per second. The I and Q signals are band-limited binary data signals. In order to detect the I and Q signals, the demodulator has the conventional local oscillator (10) receiving a variable frequency or phase control signal .phi..sub.C. The local oscillator (10) is shown having hybrid outputs Q and Q in phase quadrature, for example cosine and sine signals respectively. Conventional modulators (11), (12) effectively multiply the hybrid outputs Q and Q by the QPSK signal S, and the desired product terms are selected by respective conventional inphase and quadraphase channel low pass filters (13), (14). In the embodiment shown in FIG. 1, conventional limiters (15), (16) generate hard limited I and Q signals respectively designated I.sub.S and Q.sub.S. A data oscillator or clock (20) receiving a variable frequency or phase control signal .phi..sub.D generates a data clock signal CLOCK, shown in FIG. 2. (The signal CLOCK is the positive or Q output of the data clock 20.) Positive edge-triggered D type flip-flops (21), (22) sample the respective hard limited data signals I.sub.S, Q.sub.S at the proper times to regenerate respective binary data streams I DATA, Q DATA estimating the transmitted data. The inphase data stream I DATA is obtained by sampling I.sub.S upon the leading or positive transitions of the CLOCK signal, while the quadraphase data stream Q DATA is obtained by sampling Q.sub.S upon the falling or negative transitions of the CLOCK signal. Thus the inphase and quadraphase data are offset from each other.

The above-described offset QPSK demodulation process assumes that the local oscillator (10) is phase-locked to the suppressed carrier and that the data clock (20) is phase-locked to the sequence of data symbols encoded in the data signals I and Q. According to an important aspect of the present invention, the phase control signals .phi..sub.C, .phi..sub.D required for acquiring and maintaining carrier and data or symbol phase-lock are obtained by sampling both the I and Q signals at the data rate, rather than just half the total data rate. Note that the I and Q signals are each sampled at half the total data rate to obtain the "data" samples I DATA, Q DATA. The additional sampling is performed by D type filp-flops (23), (24), which sample the I signal I.sub.S and the Q signal Q.sub.S, respectively. The inphase "control" samples are sampled by the flip-flop (23) coincident with the negative transitions of the CLOCK signal, while the quadraphase "control" samples are sampled by the flop-flop (24) coincident with the positive transitions of the CLOCK signal. The D flip-flops (23), (24) function as one-bit digital samplers by analogy to analog-to-digital converters which function as multiple-bit digital samplers. Thus associated with each "control" sample is a coincident "data" sample from the other channel, and an immediately preceding "data" sample and an immediately following "data" sample from the same channel.

The applicant has discovered that when there is a logic transition between the "data" samples immediately preceding and immediately following a "control" sample, the value of the "control" sample is correlated with the "data" sample immediately preceding or immediately following the "control" sample to an extent generally proportional to the data or symbol phase error, and the value of the "control" sample is correlated with the "data" sample (from the other channel) coincident with the "control" sample to an extent generally proportional to the carrier phase error. The sign of the correlation indicating carrier phase error, however, is different depending on whether the "control" sample is an inphase or quadraphase sample, since a relatively small local oscillator phase lag effectively "counter-clockwise rotates" transmitted I partially into received Q but partially "rotates" transmitted Q into received -I. Even if the "control" samples are hard limited, there is sufficient correlation to estimate the carrier and data or symbol phase errors so that carrier phase and data or symbol phase may be acquired and phase-lock maintained.

According to an important aspect of the invention, if there is a logic transition between the "data" samples immediately preceding and immediately following a "control" sample, the carrier phase error or control signal is generated from the "control" sample by conditionally reversing the sign or polarity of the "control" sample depending on the logic state of the "data" sample (from the other channel) coincident with the "control" sample (with reversals occurring upon different data polarity depending on whether the "data" sample is from the inphase or quadraphase channel), and the data or symbol phase error or control signal is generated from the "control" sample by conditionally reversing the sign or polarity of the "control" sample depending on the direction of the transition between the "data" samples immediately preceding and immediately following the control sample (the direction being obtainable from the logic state of either the preceding or following "data" sample). In the embodiment shown in FIG. 1, for inphase "control" samples an exclusive-OR gate (25) conditionally reverses the sign or polarity of the "control" sample depending on the logic state of the complement Q of the coincident quadraphase "data" sample, while for the quadraphase "control" samples an exclusive-OR gate (26) conditionally reverses the sign or polarity of the "control" sample depending on the logic state of the coincident inphase "data" sample. An exclusive-OR gate (27) conditionally reverses the sign or polarity of inphase "control" samples depending on the direction of any inphase data transitions as detected from the logic state of the immediately preceding "data" sample, and similarly an exclusive-OR gate (28) conditionally reverses the sign or polarity of quadraphase "control" samples depending on the direction of any quadraphase data transitions as detected by the logic state of the immediately preceding "data" sample. The "control" samples with conditionally reversed sign or polarity are fed to the carrier phase .phi..sub.C and data or symbol phase .phi..sub.D error or control outputs through a set of four tristate drivers, charge pumps or transmission gates (29), (30), (31), (32) receiving the outputs of the exclusive-OR gates (25), (26), (27), (28), respectively. Note that the outputs of the tristate drivers (19) and (30) are combined in wired-OR fashion to generate the carrier phase error or control signal .phi..sub.C, and the outputs of tristate drivers (31) and (32) are also combined in wired-OR fashion to generate the data or symbol phase error or control signal .phi..sub.D.

The pairs of tristate drivers (29), (31) and (30), (32) are enabled to generate active phase error or control signals only upon the occurrence of transitions in the inphase data and quadraphase data, respectively. Inphase data transitions are detected by a D flip-flop (35) and an exclusive-OR gate (37), and quadraphase data transitions are also detected by a D flip-flop (36) and an exclusive-OR gate (38). Note that the D flip-flop (35) is clocked by the inverted data clock Q while the D flip-flop (36) is clocked by the noninverted data clock Q, in contrast to the respective preceding flip-flops (21) and (22) so that the D flip-flops (35), (36) provide an effective delay of one-half clock period. This one-half delay assures that there is no contention between the wired-OR tristate driver pairs (29), (30) and (31), (32).

FIG. 2 illustrates the data phase .phi..sub.D and carrier phase .phi..sub.C control signals generated by the demodulator of FIG. 1 for the case of transitions in the inphase data only and Q.sub.S being high or a logical 1 (Q.sub.S being low). Positive or "upward" tristate pulses in .phi..sub.D indicate that the phase of the data clock (20) is delayed and thus the data clock frequency should be temporarily increased. Positive tristate pulses in .phi..sub.C indicate that the phase of the local oscillator (10) is delayed and thus the frequency of the local oscillator should be temporarily increased. The tristate signals are shown as pulses since the area, eithr positive or negative, of the pulses is integrated by the loop filters in the local oscillator (10) and data clock (20) to specify their phase or frequency. The pulses, for example, may denote current sourced to or sinked from integrating capacitors across which frequency or phase control voltages are generated.

Turning now to FIG. 3, there is shown another embodiment of the invention using a microcomputer (40) executing a series of instructions in its memory to perform the offset QPSK demodulation method of the present invention. A programmable timer (41) shown as a presettable down counter functions as the data clock (20). A crystal-controlled oscillator (42) regenerates the suppressed carrier, which may be used as a high frequency reference for the "front end" of a digital radio receiver using the demodulator in FIG. 3. The oscillator output is divided by four in a two-stage binary counter (43) and the two binary state outputs Q.sub.1, Q.sub.0 are fed to a decoder (44). The decoded states 0, 1, 2, 3 sequentially enable respective individual switching elements generally designated (45) functioning as inphase and quadraphase balanced modulators. The switching elements are preferably MOS FETS or CMOS transmission gates. The switching elements (45) are wired in ring fashion, bridging the center-tapped secondary of a tuned IF transformer generally designated (46), the center tap being at signal ground. The IF transformer receives the QPSK signal S from the front-end or down converter of the digital radio receiver, or from another source such as a coaxial cable. Also bridging the ring of switching elements is a pair of capacitors (47), (48) shunting the inphase and quadraphase balanced modulator outputs to signal ground, thereby suppressing the higher order product signals by holding the values "sampled" by the switching elements. The inphase and quadraphase low pass filters (13), (14) serve as data symbol reconstruction filters and also provide the primary selectivity characteristic of the digital radio receiver. In a digital radio receiver, the low pass filters (13), (14) preferably have low noise, some gain coincident with their selectivity, and good power supply isolation. Active R-C filters employing FET or CMOS operational amplifiers are recommended. The limiters (15), (16) are shown in FIG. 3 as high gain inverting amplifiers. To achieve good limiter symmetry, the input threshold, for example a positive op-amp input, should be at the midpoint of the high and low saturated output levels. Then the DC blocking or AC coupling capacitors (49), (50) working in conjunction with the feedback biasing resistors (51), (52) assure that the duty cycle of the hardlimited I.sub.S and Q.sub.S signals is 50%. Good limiter symmetry and relatively equal phase delays through the I and Q channels are desired since the carrier phase and the data or symbol phase information in effect "resides" or is encoded in the time positions of the transitions in the I.sub.S and Q.sub.S signals.

The observed limiter symmetry is further improved by insuring that the DC values of the I and Q signals are zero by employing appropriate coding techiques at the transmitter. If the transmitted data is differentially encoded to avoid carrier phase lock-point ambiguity, then the DC components in the I and Q signals may be set to zero by the periodic insertion of data bits set to predeterminable, data dependent logical values for the sole purpose of eliminating DC components. The transmitted data D.sub.0, D.sub.1, D.sub.2 . . . may be encoded as inphase and quadraphase data according to:

The encoded data may be differentially decoded in the circuit of FIG. 1 by the transition detecting flip-flops (35), (36) and exclusive-OR gates (37), (38). The differentially decoded data (DIF. DEC. DATA) is obtained in a serial stream by combining the output of gate (37) (Idif.) with the output of gate (38) in an OR gate (39). If one data bit in 16 is selected as an inserted data bit to eliminate the DC values, the inserted bits are, for example, D.sub.30, D.sub.31, D.sub.62, D.sub.63, . . . , D.sub.n(32)-2, D.sub.n(32)-1, . . . Running sums of the DC values for I and Q are calculated as: ##EQU1## where VAL(logic high)=1 and VAL(logic low)=1. The next inserted data bits D.sub.n(32)-2 and D.sub.n(32)-1 are at first set to logic low and the partial sums ##EQU2## are calculated. If either of the partial sums has the same sign or polarity as the respective running sum, then the respective inserted data bit is set to logic high and the I and Q data are reencoded for transmission, or equivalently the following encoded I and Q bits are inverted, thereby preventing the magnitude of the next running sum from exceeding a value of 16. It is assumed, of course, that a memory buffer or shift register of approximately 32 bits is used to temporarily store the data bits or encoded bits until the partial sums can be evaluated. This encoding procedure, used to generate the I and Q data which modulate the suppressed inphase and quadraphase carriers at the transmitter, is easily performed by a microcomputer. An exemplary computer program for a Motorola MC6800 microprocessor is listed in Table I appended to the specification. The program assumes that a Motorola 6820 PIA has a control register at memory location FOOF and a data direction and input/output register at memory location FOOE. The computer program receives the data on the I/O port bit P7 upon interrupt, and the I and Q channel data are outputted on bits P0 and P1, respectively. A frame sync pulse may also be received on bit P6 in order that the inserted data bits are the last two data bits in the 32 bit frame.

Returning to FIG. 3, the outputs of the limiters (15), (16) are fed to the inputs P0, P1 of the microcomputer (40). The microcomputer as well as the programmable counter (41) are clocked at appropriate frequencies from a divider chain (55) excited by the oscillator (42), an initial division by four being performed by the two-stage binary counter (43). The microcomputer (40) is periodically interrupted at the data rate by the zero signal ("0") form the programmable counter (41). Coincident with the interrupt, the zero signal ("0") presets the programmable counter (41) via the jam input (J) to an initial state specified in part by a three-bit number (D.sub.2, D.sub.1, D.sub.0) assumed to be the least significant portion of the binary number specifying the value of the intital state. The programmable counter generates the desired data rate, for example, when the three-bit number has a value of 3. Then the microcomputer can modulate the frequency or phase of the programmable counter functioning as the data clock by the value of the three-bit number on its outputs P4, P3, P2. The number has a value of 3, for example, when the "tristate" data phase control signal is inactive, and a value of 4 to 2 for an active low or high, respectively, the higher number generating the lower data clock frequency. It is also desirable for the bandwidth of the data phase-locked loop to be relatively wide for acquiring the QPSK signal and relatively narrow for maintaining phase-lock. For this purpose values of 6 or 0 for an active low or high are specified by the microcomputer on the outputs P4, P3, P2 during acquisition, until phase-lock is detected. Phase-lock may be detected, for example, by the reception of a predetermined frame synchronization code in the received data, or alternatively by using error detecting coding and presuming that phase-lock has occurred when sufficiently low error rates are indicated.

The microcomputer (40) also has two tristate outputs P6, P5 used as carrier phase control outputs. Tristate outputs are available, for example, from a Motorola PIA part number 6820. Alternatively, a tristate output can be obtained from two logic outputs, one for asserting a logic high and the other for asserting a logic low, by combining the outputs through two diodes, the diodes both being back biased or "off" when the tristate output is inactive and neither logic state is asserted. Two tristate outputs P5, P6 are used so that the carrier phase-locked loop will have a relatively narrow bandwidth when one output is used, and a relatively wide bandwidth when the other or both outputs are used. The outputs can be used simultaneously, for example, for sweeping across a wide carrier frequency range. In the sweep mode for carrier acquisition, one output provides the phase control output .phi..sub.C, while the other is asserted high or low periodically or intermittently. The relative loop bandwidths for the outputs P5, P6 are set by the values of respective current limiting resistors (56), (57). The current through the resistors is in part integrated by a "type II" loop filter capacitor (58), the stability of the carrier acquisition loop being assured by a phase lead inducing resistor (59). The center frequency of the oscillator (42) is set by a crystal or resonator (60) and to some extent by capacitors (61), (62) connected to the crystal leads. A varactor (63) pulls the crystal frequency as a function of its bias voltage supplied through a resistor (64) from the loop filter components (56), (57), (58), (59).

The microcomputer (40) compares the received data to a predetermined frame synchronization code, and once frame sync is established the data following the frame sync code is available for display or control functions through a suitable input/output or I/O device (70) such as an alphanumeric display.

Since the digital receiver in FIG. 3 is a synchronous or linear receiver, it can be adapted to receive spread-spectrum transmissions by correlating the received singal S by a copy of the pseudorandom code used at the transmitter to spread the spectrum of the signal S. The predetermined code is clocked out of a pseudorandom sequence generator (71) when enabled by a gate (72) activated by the output P7 of the microcomputer (40). The pseudorandom sequence is encoded into the local inphase and quadraphase carriers via an exclusive-OR gate (74) which has the effect of phase shifting the carriers by 180 degrees.

It should be noted that the microcomputer (40) simulates the operation of the demodulator in FIG. 1 on a timed-interrupt basis. This frees the executive program or foreground routines for servicing the I/O device (70). An exemplary microcomputer program for a Motorola 6800 microprocessor is listed in Table II appended to the specification. The interrupt routine DECODE determines whether the current CLOCK transition in FIG. 2 is rising or falling, as indicated by a software switch POL, and performs the logical operations coincident with that polarity of transition. The computer program assumes that the I/O port P7, P6, . . . , P0 is a Motorola 6820 PIA having a control B register at address FOOF and a data direction and I/O register B at address FOOE. The tristate outputs P5, P6 are conditionally set inactive by setting bits 5 and 6 in the data direction register to zero, thereby designating P5 and P6 as inputs. The interrupt routine also differentially decodes the received data and correlates the decoded data with a 530F frame synchronization code. When the frame sync code is detected, a flag LOCK is set on and the decoded data is loaded into a 32-byte buffer at addresses 0000 to 0020. When the buffer is full a flag FULL is set. The flag LOCK is cleared if the frame sync code in not periodically received each time after the buffer is filled.

Although an external programmable counter or timer (41) is shown in FIG. 3, the programmable counter may be simulated by a fast interrupt procedure executed by the microcomputer (40) if the data rate is relatively slow compared to the execution speed of the microcomputer. An exemplary fast interrupt procedure CLOCK is included at the end of the listing in Table II appended to the specification. For each fast interrupt, a memory location COUNT representing the state of the programmable counter (41) is decremented. If the result is zero, the memory location COUNT is preset to the desired initial state and the data rate interrupt DECODE is executed. It should be noted that the data rate interrupt DECODE may itself be interrupted by subsequent fast interrupts.

In view of the foregoing, an offset QPSK demodulator and receiver providing differentially decoded data and clock and carrier phase control signals has been described that is suitable for low cost integrated circuit implementation. A low data rate embodiment using a microcomputer has also been described. Although the illustrative embodiments have been presented in the context of radio communications, it is evident that the present invention can be used to double the data rate wherever phase shift keying (PSK) is presently used, so that the invention is universal in applications involving data storage or transmission in other than baseband format. Thus the present invention is useful with alternative data storage or transmission mediums such as coaxial cable, microwave, infrared, fiber optic, ultrasonic, and magnetic or optical disc or tape.