US 4,574,254 AGrant
Phase-Lock Loop Circuit Providing Very Fast Acquisition Time
Issue Date:1986-03-04
•10 Claims
•3 Drawing Sheets
Abstract
The present invention relates to a very fast acquisition phase-lock loop arrangement comprising means for generating an error signal between an input signal to the loop and an output signal of a voltage controlled oscillator (VCO). The generated error signal, over its possible range of phase differences, is transformed by a transforming means into an output signal comprising a predetermined nonlinear response. The output signal from the transforming means is integrated in an integrating means to generate a control signal for appropriately changing the output signal of the VCO. Noise performance can be significantly improved by cascading two or more of the present phase-lock loop arrangements.
Metadata
Assignee
- AT&T Bell Laboratories
Inventor
- Bernard Glance
Application Information
Application Number:US 6482414
Filing Date:1984-09-07
Priority Date:1984-05-24
Art Unit:252
Classifications
IPC:
H03L 700
Field of Search:
3311 R;1 A;16;17;25
Patent Drawings (3 sheets)
Description
Technical Field
The present invention relates to a very fast acquisition phase-lock loop arrangement and, more particularly, to a very fast acquisition second-order phase-lock loop arrangement comprising means for providing an error signal between an input signal to the loop and a voltage controlled oscillator (VCO) output signal; a network arrangement, responsive to signals from the error signal means, including a pair of diodes in a parallel front-to-back arrangement shunted by a resistance of a predetermined value, which combination feeds an operational amplifier (OP-AMP); and an integrator for integrating the output signal from the OP-AMP of the network arrangement and delivering the resultant signal to the input of the VCO.
Description of the Prior Art
The acquisition time of a second-order phase-lock loop can be prohibitively long when the initial frequency offset is large compared to the loop's natural frequency. Different techniques have been proposed to accelerate the acquisition time of such phase-lock loops. One currently utilized technique uses a ramp-shaped waveform to sweep the frequency of a voltage-controlled oscillator (VCO) as disclosed in, for example, the book "Digital Communications by Satellite" by J. J. Spilker, Prentice Hall, 1977, in Chapter 12 at pages 359-362. Two other less frequently used methods are the combined discriminator-phase detector scheme as disclosed, for example, in the article "Frequency-Agile Millimeter-Wave Phase Lock System" by P. S. Henry in Review Scientific Instruments, Vol. 47, No. 9, September 1976 at pages 1020-1025, and the dual-time-constant switching technique as disclosed, for example, in the article "The DC Quadricorrelator: A Two-Mode Synchronization System" by D. Richman in Proceedings of the I.R.E., Vol. 42, No. 1, January 1954 at pages 288-299.
Other arrangements have been disclosed for providing fast acquisition for a phased-lock loop. One such arrangement is disclosed in U.S. Pat. No. 3,933,958 issued to G. A. Cutsogeorge on Nov. 23, 1976. There the phase-lock loop utilizes a plurality of R-C circuits, having different time constants, interconnected with diodes. Another arrangement is disclosed in U.S. Pat. No. 3,795,870 issued to S. N. Sanders on Mar. 5, 1974 where a frequency-phase detector operating in the frequency detector mode produces a high level dc control signal to a VCO to rapidly lock the loop. At loop lock, the frequency-phase detector switches to its phase detector mode for normal phase-lock loop operation. Still another arrangement is disclosed in U.S. Pat. No. 4,379,270 issued to M. P. Carter et al on Apr. 5, 1983 wherein a fixed oscillator feeds a reference frequency to a phase comparator via a fixed divider, while a VCO feeds its output frequency to the comparator via an adjustable divider. In response to a phase error, the comparator produces a control signal which is integrated to adjust the VCO frequency and has a value to change the VCO frequency to produce a temporary phase error in the opposite direction to the detected phase error.
The problem in the prior art is to provide a phase-lock loop arrangement which (a) has an acquisition time several orders of magnitude lower than achieved with conventional phase-lock loops, (b) uses much simpler circuitry, and (c) provides locking stability against faster frequency changes than those which can be sustained using conventional circuits.
Summary of the Invention
The foregoing problem has been solved in accordance with the present invention which relates to a very fast acquisition phase-lock loop arrangement and, more particularly, to a very fast acquisition second-order phase-lock loop arrangement comprising means for providing an error signal between an input signal to the loop and a voltage controlled oscillator (VCO) output signal; a network arrangement, responsive to signals from the error signal means, including a pair of diodes in a parallel front-to back arrangement shunted by a resistance of a predetermined value, which combination feeds an operational amplifier (OP-AMP); and an integrator for integrating the output signal from the OP-AMP of the network arrangement and delivering the resultant signal to the input of the VCO.
It is an aspect of the present invention to provide two appropriately tuned very fast acquisition phase-lock loop arrangements, in accordance with the present invention, in cascade for significantly improving noise performance of the overall phase-lock loop arrangement.
Other and further aspects of the present invention will become apparent during the course of the following description and by reference to the accompanying drawings.
Brief Description of the Drawings
Referring now to the drawings in which like numerals represent like parts in the several views:
FIG. 1 is a block diagram of a conventional second-order phase-lock loop arrangement;
FIG. 2 is a block diagram of the phase-lock loop arrangement in accordance with the present invention;
FIG. 3 illustrates a curve of the output signal of the network, in the arrangement of FIG. 1, in proportion to the phase error input signal;
FIG. 4 illustrates a curve of the variation of the phase error over time in accordance with the arrangement of FIG. 1; and
FIG. 5 illustrates a block diagram of two phase-lock loop arrangements in accordance with FIG. 2 in cascade.
Detailed Description
FIG. 1 shows a schematic of a conventional second-order phase-lock loop. In the arrangement of FIG. 1, a mixer 10 receives a first input signal to the loop at an angular frequency .omega..sub.1, and a second input signal which is the output signal at an angular frequency .omega..sub.2 from a voltage controlled oscillator (VCO) 11 and generates a resultant error signal therebetween which is designated by the term k.sub.d sin .phi.(t). The quantity k.sub.d depends on the amplitude of both signals and on the mixer 10 low frequency response with the value thereof expressed in volts per radian. The output from mixer 10 is integrated in integrating means 12, which is shown as using an operational amplifier (OP-AMP) but could comprise any other suitable integrating means, to generate the control signals V(.phi.) which tune the VCO according to the relation ##EQU1## The quantity k.sub.o defines the frequency-voltage relation of VCO 11 with its value expressed in rad/sec/volt. The quantity .omega..sub.2 -.omega..sub.1 is the initial frequency offset. The parameters k.sub.d and k.sub.o combined with the resistances 13 and 14 and the capacitance 15 of the OP-AMP define the natural loop frequency .omega..sub.n and the damping factor .xi. according to the relations ##EQU2##
Phase-locking is achieved when the charge accumulated by the capacitance 15 of the OP-AMP provides the dc voltage required to tune VCO 11 by .omega..sub.2 -.omega..sub.1, i.e., when ##EQU3## For large values of ##EQU4## the acquisition time t.sub.1 is given approximately by ##EQU5## For example, a loop having a 200 Hz natural frequency and a damping factor of unity takes about 36 seconds to phase-lock when ##EQU6## ps The long duration of the acquisition process can be simply explained by noting that capacitance 15 is charged by the quasi-periodic current k.sub.d /R.sub.1 sin .phi.(t), where R.sub.1 is the value of resistance 13, whose period increases very slowly with time when As a result, the net charge accumulated per cycle of .phi.(t) is very small and it takes many such cycles to charge capacitance 15 to obtain phase-locking. For example, it would take several thousand cycles in the previously cited example.
In accordance with the present invention, a reduction in acquisition time is obtained by changing the error signal to the integrating means 12 for values of .phi.(t) close to .+-..pi./2. FIG. 2 is a block diagram of the second-order phase-lock loop in accordance with the present invention which modifies the arrangement of FIG. 1 by adding a network 20 between mixer 10 and integrating means 12. The network 20 comprises a pair of diodes 21 and 22 in a parallel front-to-back arrangement shunted by a resistance 23 whose value is selected to be much lower than the combined diode resistance near zero bias. The resulting network 20 subsection comprising diodes 21 and 22 and resistance 23 feeds an operational amplifier 24, whose function it is to provide an output signal, V.sub.b, proportional to the network current, as illustrated in FIG. 3.
In operation, for small values of .phi.(t) network 20 provides the same error signal as the conventional phase-lock loop arrangement of FIG. 1, and therefore the same performance. By contrast, however, a phase error close to .+-..pi./2 greatly increases the magnitude of the error signal.
In this mode, the locking equation (1) can now be expressed as ##EQU7## The quantities V.sub.o and .alpha. are parameters characterizing the diode current variation versus input signal and the gain of OP-AMP 24. The value of k.sub.d is adjusted to insure that the diode pair 21-22 is driven into conduction for a phase error close to .+-..pi./2 as shown in FIG. 3. The gain of OP-AMP 24 is adjusted such that .alpha.k'.sub.d V.sub.o =k.sub.d, where k.sub.d is the value in equation (2) which yields the desired loop natural frequency. The variation of the phase error .phi.(t) can be approximated as follows. Initially, the phase error .phi.(t) increases almost linearly as (.omega..sub.2 -.omega..sub.1)t. Concurrently, the current flowing in the feedback loop of the integrating means increases as V.sub.o /R.sub.1 sin h(.alpha.k'.sub.d sin .phi.) until the voltage developed across the resistance 14 becomes equal to the voltage required to tune VCO 11 by .omega..sub.2 -.omega..sub.1, where R.sub.1 is the resistance of resistor 13. When this happens, ##EQU8## i.e., this happens for a value of .phi.=.phi..sub.o .ltoreq..pi./2 in the very short time interval ##EQU9## This duration is too short for any significant accumulation of charge into capacitor 15. At such point in time, d.phi./dt=0 and thus VCO 11 is frequency-locked. Thereafter, the phase error .phi.(t) decreases to zero while the current V.sub.o /R.sub.1 sin h(.alpha.k'.sub.d sin .phi.) charges the capacitance 15 to give the final dc voltage ##EQU10## required to keep VCO 11 frequency tuned at .omega..sub.1. This phase-locking period, following the frequency-locking time intervals .DELTA.t, lasts about 6.pi./.omega..sub.n seconds, almost independently of ##EQU11## The variation of .phi.(t) is illustrated in FIG. 4. The maximum range of frequency acquisition is limited by ##EQU12## and by the time delay of the loop.
It should be noted that phase-locking is now achieved for a phase error variation less than .pi./2 instead of the many cycles needed by the conventional loop. For a damping factor of unity, the process is speeded up by a factor ##EQU13## This gives, for ##EQU14## a reduction in acquisition time of about 2387. It should also be noted that for the previous loop parameters, the phase acquisition time is reduced from 36 seconds to about 15 msec, while frequency-locking is obtained in about 5 microseconds.
Once VCO 11 is phase-locked, the network 20 also provides, through the same effect, a much greater locking stability against fast frequency changes than do conventional circuits. The maximum frequency drift which can be sustained by the conventional phase-lock loop of FIG. 1 is given by ##EQU15## For the arrangement of FIG. 2, this quantity increases to ##EQU16## the ratio V.sub.sat /k.sub.d can be as large as 300.
In an experimental arrangement which permitted the selection of either one of the arrangements of FIGS. 1 and 2, an input signal was provided by a Hewlett Packard synthesizer generator Model 3335A, VCO 11 was provided with a Wavetek oscillator model 114 having a voltage coefficient of 200 kHz/volt around 1 MHz. Mixer 10 included a double balanced mixer giving an output of 100 mV peak to peak. The value of resistances 13 and 14 and capacitance 15 of integrating means 12 were selected to give f.sub.n approximately equal to 200 Hz and .xi.=1 for both methods of operation. In this arrangement, the acquisition time of the conventional mode arrangement was about 35 seconds for an initial frequency offset of .+-.60 kHz. In the present invention mode of operation, the acquisition time was reduced to approximately 20 msec. for the same frequency offset. Concurrently, the loop of the present invention stayed locked for frequency changes which were orders of magnitude faster than those that can be sustained for the conventional mode.
If it is desired to improve the noise performance of the phase-lock loop (PLL) arrangement of FIG. 2, two arrangements as shown in FIG. 2 can be placed in cascade as shown in FIG. 5. In FIG. 5, the first PLL arrangement comprises mixer 10.sub.1, VCO 11.sub.1, network 20.sub.1 and integrating means 12.sub.1. The second PLL arrangement, in cascade with the first PLL arrangement, comprises mixer 10.sub.2, VCO 11.sub.2, network 20.sub.2 and integrating means 12.sub.2. Each PLL functions as described for the PLL of FIG. 2, but noise performance of the cascade arrangement is improved over that found with the single PLL arrangement of FIG. 2. Therefore, depending on the desired noise performance, one can use either the arrangement of FIG. 1 or the arrangement of FIG. 2.
Claims
What is claimed is:
1. A phase-lock loop arrangement comprising: a voltage controlled oscillator (VCO) for providing a predetermined frequency output signal in response to a predetermined input control signal; means responsive to both an input signal to the loop and the predetermined frequency output signal from the VCO for generating an output error signal representative of the difference in phase between the two signals; means capable of directly transforming the output error signal from the generating means, over a range o predetermined phase differences, into an output signal comprising a predetermined nonlinear response wherein small values of the transforming means output signal are generated which increase linearly away from zero for a small range of values of the output error signal on either side of a zero output error signal and then increase exponentially for output error signals outside said small range of values; and means responsive to the output signal from the transforming means for integrating the transforming means output signal and generating the input control signal to the VCO which is representative of the resultant integrated signal.
2. A phase-lock loop arrangement according to claim 1 wherein the transforming means comprises: a network including a pair of diodes in a parallel front-to-back arrangement shunted by a resistance whose value is lower than the diode resistance near zero bias, the network being connected to the output of the generating means; and an operational amplifier (OP-AMP) connected to the output of the network for generating an output signal to the integrating means which is proportional to a current propagating in the network.
3. A phase-lock loop arrangement according to claim 2 wherein the integrating means comprises an operational amplifier.
4. A phase-lock loop arrangement according to claim 1 wherein the integrating means comprises an operational amplifier.
5. A phase-lock loop arrangement according to claim 1 wherein the nonlinear response of the output signal from the transforming means essentially follows an output voltage-to-input error signal characteristic curve which resembles a sine hyperbolic characteristic curve.
6. An overall phase-lock loop arrangement comprising: a plurality of phase-lock loops arranged in cascade between an input and an output of the overall arrangement, each phase-lock loop (PLL) comprising: an input terminal for receiving either (1) an input signal to the overall PLL arrangement if the associated PLL is a first PLL in the cascade arrangement, or (2) an output signal from the immediately prior PLL in the cascade arrangement if the PLL is not a first PLL in the cascade arrangement; an output terminal for delivering an output signal from the associated PLL to either (1) an output of the overall phase-lock loop arrangement if the associated PLL is the last PLL in the cascade arrangement, or (2) an input of a next subsequent PLL in the cascade arrangement if the PLL is not a last PLL in the cascade arrangement; a voltage controlled oscillator (VCO) for providing a predetermined frequency output signal to the output terminal of the associated PLL in response to a predetermined input control signal; means, responsive to both an input signal from the input terminal of the associated PLL, and the predetermined frequency output signal from the associated VCO, for generating an output error signal representative of the difference in phase between the PLL input signal and the VCO output signal; means capable of directly transforming the output error signal from the generating means, over a possible range of predetermined phase differences, into an output signal comprising a predetermined nonlinear response wherein small values of the transforming means output signal are generated which vary linearly away from zero for a small range of values of the output error signal on either side of a zero output error signal and then increase exponentially for output error signals outside said small range of values; and means responsive to the output signal from the transforming means for integrating the transforming means output signal and generating a control signal to the VCO representative of the resultant integrated signal.
7. A phase-lock arrangement according to claim 6 wherein the transforming means comprises: a network including a pair of diodes in a parallel front-to-back arrangement shunted by a resistance whose value is lower than the diode resistance near zero bias, the network being connected to the output of the generating means; and an operational amplifier (OP-AMP) connected to the output of the network for generating an output signal to the integrating means which is proportional to a current propagating in the network.
8. A phase-lock loop arrangement according to claim 7 wherein the integrating means comprises an operational amplifier.
9. A phase-lock loop arrangement according to claim 6 wherein the integrating means comprises an operational amplifier.
10. A phase-lock arrangement according to claim 6 wherein the nonlinear response of the output signal from the transforming means essentially follows an output voltage-to-input error signal characteristic curve which resembles a sine hyperbolic characteristic curve.
Patent Citations (12)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3699454 | 1972-10-01 | Hudspeth et al. | |
| US3795870 | 1974-03-01 | Sanders | |
| US3993958 | 1976-11-01 | Cutsogeorge | |
| US4099137 | 1978-07-01 | Alm, Jr. et al. | |
| US4103250 | 1978-07-01 | Jackson | |
| US4219783 | 1980-08-01 | Carter et al. | |
| US4297650 | 1981-10-01 | Shinmyo | |
| US4363004 | 1982-12-01 | Englund, Jr. et al. | |
| US4379270 | 1983-04-01 | Carter et al. | |
| US4387348 | 1983-06-01 | Fritze | |
| US4514705 | 1985-04-01 | Harzer | |
| GBX2084415 | 1982-04-01 |
Non-Patent Literature (3)
- D. Richman, "The DC Quadricorrelator: A Two-Mode Synchronization System", Proc. IRE, vol. 42, No. 1, Jan. 1954, pp. 288-299.
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