Combining and Filter Circuit for a Phase Locked Loop

Our invention relates to a combining and filter circuit for a phase locked loop, and particularly to such a circuit that combines phase detector and acquisition circuit signals, and filters those signals for application to a voltage controlled oscillator in a phase locked loop.

Phase locked loops using a reference oscillator and a voltage controlled oscillator usually include an acquisition circuit to provide signals that bring the voltage controlled oscillator frequency within the range of the phase detector circuit. After the voltage controlled oscillator frequency is within the range of the phase detector circuit, signals from the phase detector circuit can then control the frequency of the voltage controlled oscillator. Where an acquisition circuit is used in addition to a phase detector circuit, it is necessary to provide an arrangement that applies the signals from the two circuits to the voltage controlled oscillator.

Accordingly, a primary object of our invention is to provide a new and improved circuit that combines signals from an acquisition circuit and from a phase detector circuit for application to a voltage controlled oscillator in a phase locked loop.

A general object of our invention is to provide a new and improved signal combining circuit for use in a phase locked loop.

In phase locked loops, filtering is needed or desired to attenuate the reference frequency signals so that the voltage controlled oscillator does not produce spurs indicative of those reference frequencies. Low pass filtering is also needed or desired to provide relatively stable control signals for the voltage controlled oscillator.

Accordingly, another object of our invention is to provide a new and improved filter circuit for use in a phase locked loop.

A relatively specific object of our invention is to provide a new and improved filter circuit that attenuates the reference frequency signals in a phase locked loop, and that provides low pass filtering of signals applied to a voltage controlled oscillator.

Another object of our invention is to provide a new and improved circuit that combines signals from an acquisition circuit and from a phase detector circuit, and that filters these signals for application to a voltage controlled oscillator in a phase locked loop.

Another object of our invention is to provide a new and improved signal combining circuit that attenuates reference frequency signals and provides low pass filtering of the combined signals for application to the voltage controlled oscillator in a phase locked loop.

Briefly, these and other objects are achieved in accordance with our invention by a circuit having respective inputs for phase detector signals and acquisition circuit signals in a phase locked loop. The signals are combined and filtered for rejecting the reference frequencies. The filtered signals are applied through reverse poled diodes to output capacitors, one of which filters noise signals and one of which is charged and discharged through reverse poled diodes. The circuit thus combines the acquisition and phase detector signals, filters these signals, and provides a single output signal for application to a voltage controlled oscillator.

The subject matter which we regard as our invention is particularly pointed out and distinctly claimed in the claims. The structure and operation of our invention, together with further objects and advantages, may be better understood from the following description given in connection with the accompanying drawing, in which:

FIG. 1 shows a block diagram of a phase locked loop in which our circuit can be used; and

FIG. 2 shows a schematic diagram of a preferred embodiment of a combining and filter circuit in accordance with our invention for use in the phase locked loop of FIG. 1.

The phase locked loop of FIG. 1 is shown connected as a frequency synthesizer. However, persons skilled in the art will appreciate that the phase locked loop can be used for other purposes. In the phase locked loop of FIG. 1, a reference frequency source 10, typically a stable crystal controlled oscillator, whose frequency is divided down, has its output signals applied to respective first inputs of a phase detector 11 and to an acquisition circuit 12. The outputs from the phase detector 11 and acquisition circuit 12 are applied to a combining and filter circuit 13 which will be explained in connection with FIG. 2. The circuit 13 combines and filters the two signals from the phase detector 11 and acquisition circuit 12, and produces a single signal which is applied to a voltage controlled oscillator 14 to control the frequency of that oscillator 14. The output signal from the oscillator 14 may be utilized in any manner desired, such as a frequency synthesized signal. In addition, this output signal is applied to a frequency changer 15 whose output is applied to respective second inputs of the phase detector 11 and the acquisition circuit 12. Except for our combining and filter circuit 13, the phase locked loop of FIG. 1 is known in the art. This circuit causes the voltage controlled oscillator 14 to produce a selected frequency, depending upon the characteristics of the frequency changer 15. This selected frequency is relatively stable because of the stability of the reference frequency source 10.

As mentioned earlier, the acquisition circuit 12 is provided to insure that the oscillator 14 frequency of FIG. 1 can be brought within the range of operation of the phase detector 11. Once this acquisition is provided, the phase detector 11 provides the necessary signals to control the oscillator 14. Thus, there is a need to combine the signals from the phase detector 11 and the acquisition circuit 12, and to properly filter these signals to cause proper and desirable operation of the oscillator 14. A new and improved combining and filter circuit in accordance with our invention is shown in FIG. 2.

With reference to FIG. 2, signals from the phase detector 11 are applied through one T network filter comprised of resistors R2, R3 and a capacitor C3 to the base of an NPN transistor Q1. Signals from the acquisition circuit 12 are integrated by a circuit comprised of a resistor R1 and capacitor C1, and are applied to the base of the transistor Q1 through a second T network filter comprised of capacitors C2, C4 and a resistor R4. The two T network filters are connected as a twin-T filter which is preferably designed to filter or eliminate frequencies centered about the fundamental component of the reference frequency source 10.

The transistor Q1 is powered by a suitable direct current voltage B+ with respect to a ground or reference potential. The output from the transistor Q1 is derived at its emitter which is connected through a resistor R5 to ground. This output is applied to a second twin-T filter comprised of the resistors R6, R7 and a capacitor C6; and capacitors C5, C7 and a resistor R8. The second twin-T filter, comprised of the resistors R6, R7 and the capacitor C6; and the capacitors C5, C7 and the resistor R8, is preferably designed to filter or eliminate frequencies centered about the second harmonic component of the reference frequency source 10. The output of this second twin-T filter is applied to the base of a PNP type transistor Q2. The emitter of the transistor Q2 is connected to the voltage B+ through a resistor R9, and the collector of the transistor Q2 is connected to the ground or reference potential. The output from the transistor Q2 is provided to an output terminal 20 by a resistor R10. This resistor R10 is connected to a parallel connected capacitor C8 and resistor R11. The parallel capacitor C8 and resistor R11 are connected to a capacitor C9, which in turn is connected to ground. The resistors R10, R11 and the capacitors C8, C9 provide a filter for noise and phase correction.

In addition to the circuit described, we provide diodes connected as shown. Because of their low voltage drop in the forward direction, we prefer that certain of the diodes be the Schottky type, which are indicated by the legend SD followed by a numeral. Thus, we provide a Schottky diode SD1 poled in the forward direction from the emitter of the transistor Q1 to the output terminal 20. We provide an ordinary or silicon diode D2 poled in the forward direction from the output terminal to the emitter of the transistor Q2. Thus the diode SD1, D2 are reverse poled relative to the output terminal 20. And, we provide Schottky diodes SD3, SD4 each connected in parallel with the capacitor C8 in oppositely poled directions. The diode SD1 provides a higher charging voltage to the capacitors C8, C9, and the Schottky diodes SD3, SD4 provide reduced voltage drop paths for charging and discharging the capacitor C9.

The operation of the circuit of FIG. 2 will be described for an actual embodiment constructed with components and values as follows:

With this circuit connected to the phase locked loop of FIG. 1 and in a stable condition, the voltage at the base of the transistor Q1 is the same as the voltage at the output terminal 20 which is applied to the voltage controlled oscillator 14. However, when the voltage at the base of the transistor Q1 changes to reflect a new desired condition, it is desirable that this voltage be applied to the output terminal 20 and the oscillator 14 as quickly as possible. This voltage change can come from the acquisition circuit 12, which is preferably integrated by the resistor R1 and capacitor C1. Or, the voltage change can come from the phase detector 11, or from both circuits 11, 12. The voltage change at the base of the transistor Q1 can be as follows:

1. A relatively small increase.

2. A relatively large increase.

3. A relatively small decrease.

4. A relatively large decrease.

These conditions will be described in the order listed above. In each description, we have assumed that the initial voltage at the terminal 20 which is applied to the oscillator 14 is at 5.0 volts, and that the nominal base-emitter voltage of the transistors is 0.6 volt.

For the first condition, we have assumed that the voltage at the base of the transistor Q1 increases from 5.0 to less than 5.6 volts, for example 5.2 volts. This causes the emitter of the transistor Q1 to rise from 4.4 to 4.6 volts. This is still less than the 5.0 volts at the output terminal 20, so that the Schottky diode SD1 is reverse biased. However, the base of the transistor Q2 rises to 4.6 volts, which causes its emitter to rise from 5.0 to 5.2 volts. This increase in voltage charges the capacitor C8 directly and charges the capacitor C9 through the diode SD4 to raise the output voltage to 5.2 volts.

For the second condition, we have assumed that the voltage at the base of the transistor Q1 increases a large amount, for example 6.0 volts. This causes the emitter of the transistor Q1 to rise to 5.4 volts, which forward biases the diode SD1 and applies this 5.4 volts to the capacitor C8 and the diode SD4 to rapidly charge the capacitors C8, C9 to the new voltage of 5.4 volts. Thus, this large increase utilizes the Schottky diode SD1 which rapidly charges the capacitor C9. When the voltage at the terminal 20 reaches 5.4 volts, the diode SD1 stops conducting. However, the 5.4 volts at the emitter of the transistor Q1 appears at the base of the transistor Q2, so that the emitter of the transistor Q2 is 6.0 volts. This voltage charges the capacitors C8, C9 more slowly through the resistor R10 until the voltage at the terminal 20 reaches 6.0 volts. This prevents overshooting during charging.

In the third condition, we have assumed a small decrease in the voltage at the base of the transistor Q1, for example from 5.0 to 4.8 volts. This causes the emitter to drop to 4.2 volts, so that the diode SD1 is back biased. The emitter of the transistor Q2 drops to 4.8 volts, which is not sufficient to forward bias the diode D2. Hence, the capacitor C8 discharges slowly through the resistor R10, and the capacitor C9 discharges slowly through the Schottky diode SD3 and the resistor R10. This slowly brings the output voltage down to 4.8 volts. Thus the diode D2, which is the ordinary type diode which has a nominal voltage drop of 0.6 volt, prevents the capacitors C8, C9 from discharging too far, or overshooting.

For the fourth condition, we have assumed a large decrease in voltage at the base of the transistor Q1, for example 4.0 volts. This causes its emitter to drop to 3.4 volts, which again back biases the diode SD1. This drop causes the emitter of the transistor Q2 to drop to 4.0 volts, which forward biases the diode D2 to discharge the capacitor C8 directly, and to quickly discharge the capacitor C9 through the Schottky diode SD3 to a voltage of 4.6, after which the resistor R10 completes the discharge.

It will thus be seen that we have provided a new and improved combining and filter circuit which provides improved operation in phase locked loops. While we prefer that the Schottky diodes be used in the forward direction between the transistor Q1 and the output, and across the capacitor C8 in both directions, persons skilled in the art will appreciate that ordinary diodes having a 0.6 volt drop may be used. However, the relatively low voltage drop in the forward direction provided by Schottky diode SD1 makes it preferable for charging the capacitors C8, C9, and for charging and discharging the capacitor C9 by means of the diodes SD3, SD4. Further, our arrangement provides two twin-T filters to improve operation by removing the reference frequency and its second harmonic. The transistors Q1, Q2 provide the proper input and output impedances for these filters. While we have shown only one embodiment of our invention, persons skilled in the art will appreciate that modifications may be made. As already mentioned, the use of Schottky diodes is not essential. Therefore, while we have described our invention with reference to a particular embodiment, it is to be understood that modifications may be made without departing from the spirit of the invention or from the scope of the claims.