Field Effect Transistor Inverter-Level Shifter Circuitry

This invention relates to logic circuitry and in particular to field effect transistor inverter-level shifter and buffer-level shifting circuitry.

One typical field effect transistor inverter circuit uses the combination of a load device and a switching device with the drain of the load device connected to a first power supply VDD, the source of the load device and the drain of the switching device connected to an output terminal, the gate of the switching device connected to an input terminal, and the source of the switching device connected to a second power supply VSS. For n-channel devices, VDD is typically +5.0 volts, VSS is typically 0 volts (ground potential), the threshold voltage of the switching device is approximately +1.0 volt, and the impedance of the load device is substantially greater than the impedance of the switching device. An applied "1" input logic state having a potential level near +5.0 volts causes both devices to conduct and the output potential level to be close to 0 volts, a "0". An applied "0" input logic state having a potential close to 0 volts causes the switching device to be biased off, and the output potential level to be at or close to +5.0 volts, a "1". If the input "0" level is +1.4 volts, as might be the case of some worse case input "0" signal received from a TTL circuit, the impedance ratio of the two devices must be modified or the threshold voltage or the switching device must be modified to obtain the desired inversion function. Such an impedance ratio modification causes the "0" output potential level to increase and thus reduces operating noise margins. In addition, it degrades the output fall time. Modification of the threshold voltage can be acommplished by adding an ion implantation step to the fabrication process which increases the complexity thereof and thereby potentially decreases yield and increases cost.

It would be desirable to have a field effect transistor inverter-level shifter circuit which can accept input "0" levels of a magnitude above the threshold voltage of the switching device but does not suffer a significant increase in the output "0" potential level or require an extra processing step to modify the threshold voltage of the switching device.

The present invention is directed to circuitry comprising a load device and first and second field effect transistors. A first terminal of the load device is connectable to a first potential source, and a second terminal of the load device is coupled to the drain of the first transistor. The gate and source of the first transistor are coupled to the gate and drain, respectively, of the second transistor. The source of the second transistor is connectable to a second potential source. A circuitry input terminal is coupled to the gates of the first and second transistors. The second terminal of the load device and the drain of the first transistor serve as the circuitry output terminal.

The circuitry functions to provide at the output terminal an inversion and level shifting of logic levels applied to the input terminal. The conductivity of the second transistor is modulated by an applied input signal and acts to control the potential of the source of the first transistor such that the first transistor does not substantially conduct even though the input potential on the gate terminal thereof has a magnitude greater than the magnitude of the threshold voltage of the first transistor. This allows for higher input "0" logic potential levels than is the case if the second transistor is not used. Accordingly, TTL logic levels can be tolerated while maintaining useful noise margins and response time. The output signal levels of the circuitry are close enough to standard MOS levels such that a standard field effect transistor inverter circuit can be coupled by an input thereof to the output of the circuitry, and true MOS potential levels are generated at the output of the standard inverter circuit.

Viewed from another aspect, the present invention is directed to circuitry comprising a load device, a first field effect transistor having a drain coupled to the load device and having a gate coupled to a circuitry input terminal, and control circuit means having a control terminal coupled to the circuitry input terminal and having a first terminal. The control circuit means is characterized by an impedance coupled to the first terminal thereof which varies as a function of the potential level of input signals applied to the control terminal thereof. An input "0" level applied to the circuitry input terminal results in a greater impedance than an input "1" level such that with an applied input "0" level, the first transistor tends to only become essentially no more than weakly biased on, and with an applied input "1" level, the first transistor becomes heavily biased on.

These and other features and advantages of the invention are better understood from a consideration of the following drawing taken in conjunction with the accompanying drawing.

The FIGURE illustrates in electrical schematic form one embodiment in accordance with the invention.

Referring now to the FIGURE, there is illustrated a buffer-level shifter circuitry 10 which comprises a first inverter-level shifter stage illustrated within dashed line rectangle A and a second inverter-level shifter stage illustrated within dashed line rectangle B. Stage A is in accordance with the present invention and comprises depletion mode field effect transistors T1 and T3 and enhancement mode field effect transistor T2. Stage B is well known in the art and comprises depletion mode field effect transistor T4 and enhancement mode field effect transistor T5. The inclusion of T3 in inverter stage A effectively results in T2 being able to become only weekly biased on when "0" level signals are applied to input terminal 16 which have a magnitude greater than the threshold voltage of T2. This permits input "0" logic signals to have substantially higher potential levels than can be tolerated by conventional field effect transistor inverter stages such as stage B. T3 acts as a control circuit or control circuit means which selectively increases the potential on the source of T2 so as to control T2's gate-to-source voltage and thus control conduction through T2. Circuitry 10 can thus accept conventional TTL input logic signal potential levels (typically 0 to +1.4 volts) and produce output potential levels which are essentially the same as produced by conventional field effect transistor buffer circuits.

An input terminal 16 of circuitry 10 is coupled to the gates of T2 and T3. T1, which acts as a load device, has the gate and source thereof coupled to the drain of T2, to the gate of T5, and to a node 18. The source of T2 is coupled to the drain of T3 and to a node 20. T4, which acts as a load device, has the gate and source thereof coupled to the drain of T5 and to a circuitry output terminal 22. The drains of T1 and T4 are coupled together to a terminal 12 and to a power supply VDD which may be referred to as a potential source. The sources of T3 and T5 are coupled together to a terminal 14 and to a second power supply VSS, which is typically, but not necessarily, ground potential (0 volts). VSS may be referred to as a potential source. The gate and source of T1 and the drain of T2 serve as the output node or terminal of stage A, and the gate of T5 serves as an input node or terminal of stage B.

For the purposes of illustration, T1, T3, and T4 are assured to be depletion mode n-channel insulated gate field effect transistors, T2 and T5 are enhancement mode field effect transistors having a threshold potential of +0.5 volt, VDD=+3.0 volts, and VSS=0 volts. An input "0" logic signal applied to input terminal 16 is assumed to have a potential level of from 0 to +1.4 volts, and an input "1" logic signal applied to input terminal 16 is assumed to have a potential level of +1.8 to 3.0 volts.

With an input "1" applied to input terminal 16, T2 is biased on and T3, which is essentially always biased on, becomes highly conductive. As current begins to flow from T1 through T2, and then through T3, the potential of node 20 increases somewhat above VSS, but does not increase sufficiently so as to cause the gate-to-source voltage of T2 to become less than the threshold voltage thereof. Thus, T2 is biased on heavily and conducts. The ratio of the impedance of T1 versus T2 and T3 is selected such that with an input "1" signal applied to terminal 16, the potential of node 18 is +0.4 volt or less positive, an output "0", for stage A. A +0.4 volt signal at the gate of T5 biases T5 off and results in output terminal 22 assuming a potential of approximately +3.0 volts, a "1" output signal.

With an input "0" logic signal having a potential of +1.4 volts applied to input terminal 16, T3 is conductive, but not as conductive as when the potential level of the input signal is at +1.8 volts or more positive. T2 becomes weakly biased on, and a relatively low level of conduction is established through T1, T2, and T3. T3 has sufficient impedance at this bias level such that the current flow therethrough produces a potential at node 20 which is sufficiently positive to assure that T2 is essentially only weakly biased on. T2 is ideally biased off at this time. This results in a output "1" at node 18 which has a potential level of approximately +2.75 volts. The impedance of T4 is designed to be significantly higher than the impedance of T5 when both are biased on and conducting, as is the case when a "1" signal is applied to the gate of T5. A +2.75 volt signal applied to the gate of T5 causes T5 to be heavily biased on and thereby causes conduction through T4 and T5. This results in output terminal 22 being at +0.2 volt, a "0" output level.

It is thus apparent that a "0" input signal having a potential level up to +1.4 volts results in a "0" output signal having a potential level of +0.2 volt and that a "1" input signal having a potential level as low as +1.8 volts results in an output signal "1" having a potential level of +3.0 volts. Accordingly, circuitry 10 performs a buffer-level shifting function with stage A providing a first inversion-level shifting function and with stage B providing a second inversion-level shifting function. The net result is that TTL input logic levels are shifted to MOS logic levels, and input signals applied to input terminal 16 are isolated from load capacitance (not illustrated) on output terminal 22.

Stage A has been fabricated as the first stage of an input address buffer of a 4096 bit static field effect transistor random access memory. Stage A has been tested and found to be fully functional. The channel lengths (in microns) and widths (in microns) of T1, T2, and T3 are 1.25, 1.0, and 1.25, and 54, 90, and 18, respectively. Circuitry 10 has also been fabricated as a buffer-level shifter circuit which is part of the above-described memory and which receives an input signal from a sense amplifier of the memory. Circuitry 10 has been tested and found to be fully functional. The channel lengths (in microns) and widths (in microns) of T1, T2, T3, T4, and T5 are 1.0, 1.25, 1.0, 1.0, and 1.25, and 4, 20, 12, 3, and 9, respectively.

The embodiments described herein are intended to be illustrative of the general principles of the present invention. Various modifications are possible, consistent with the spirit of the invention. For example, p-channel field effect transistors can be substituted for the n-channel transistors, provided power supply levels and input logic levels are appropriately modified. Still further, depletion mode transistor T3 can be replaced by an enhancement transistor, providing the impedance thereof is properly selected. Still further, T1 can be replaced by a variety of load devices, including a resistor. Still further, stage B can be replaced with many well-known inverter stages. Still further, appropriate changes in impedance levels of the transistors, and the magnitudes of the power supplies, can facilitate the use of the circuitry to detect relatively small signal differences such as are common with emitter-coupled logic circuits or other logic families. Still further, circuitry 10 can be fabricated in CMOS with T1 and T4 being p-channel transistors and T2, T3, and T5 being n-channel transistors or with T1 and T4 being n-channel transistors and T2, T3, and T5 being p-channel transistors.