TTL Compatible CMOS Input Buffer

This invention relates to TTL compatible CMOS input buffer devices.

In the past, one of the problems with interfacing CMOS logic to TTL logic was the difference in the output level of the TTL output driver and the guaranteed noise immunity of CMOS input buffer circuits as shown in FIG. 1. The output voltage for TTL circuits is guaranteed to be 0.8 v for a low output (V.sub.OL) and 2.4 v for a high output (V.sub.OH), with power supply voltage (Vcc) between 5.5 and 4.5 volts. The CMOS input has no problem with an input of 0.8 v because the input low voltage (V.sub.IL) is normally 30% of Vcc or roughly 1.5 v, but the input high voltage (V.sub.IH) is normally 70% of Vcc or about 3.5 volts. Obviously, the V.sub.OH of TTL is not sufficient to meet the normal CMOS V.sub.IH specification.

There are several ways to correct this problem. One way is by using a pull-up resistor at the input of the CMOS device to pull up the input high voltage, but this method has a few problems. One is that with a pull up resistor there is a dc current loop from Vcc to ground whenever the TTL device's output is low, as shown in FIG. 2, and this defeats the purpose of using CMOS. Another problem is that the addition of a resistor increases device count on the board, consumes space and increases cost. The resistor can be fabricated on the chip but it will draw too much current in a CMOS environment and hence is unacceptable to CMOS users.

Another way of correcting this problem is to reduce the V.sub.IH of the CMOS input to trigger at 2.4 v. To accomplish this, the device ratios for the P and N channel transistors have to be altered. The normal device ratio in CMOS depends on the K.sub.P and K.sub.N (gain factors). Generally, K.sub.N is about three times that of K.sub.P in a polysilicon gate bulk CMOS process. This means that if channel lengths are the same for both P and N devices, then to have comparable rise and fall times at the output, the width of the P device has to be three times that of the N device (this ratio results in an input trigger voltage of about V.sub.IH =3.0 v). To reduce the V.sub.IH to 2.4 v, the N channel device drive must be increased relative to the P channel device or the width of the N device has to increase (assuming the device lengths are kept comparable). This mismatch in device ratios affects the speed and the output rise and fall times of this buffer such that the fall time is much faster than the rise time. To reduce the mismatch in output drive, another mismatched stage is used at the output of the first stage, see FIG. 3. Now, the difference in rise and fall time is not as large but the added delay due to slow rise time of the first stage remains.

Accordingly, it is an object of the invention to provide a TTL compatible CMOS input buffer with minimal voltage mismatching at the interface for lowered power consumption and improved rise-fall times for minimal time delays.

It is a further object of the invention to provide spatially constrained layout dimensions as a result of the smaller transistors utilized in a lowered power consumption environment.

It is another object of the invention to provide a transmission gate between the P and N devices of the first stage operative to act as a variable impedance whose value is controlled by the input to the buffer.

It is another object of the invention to provide a transmission gate that is a pair of transistors.

Various other objects, advantages and meritorious features of the invention will become apparent from the following specification, appended claims and accompanying drawing sheets.

The features of a specific embodiment of the invention are illustrated in the drawings in which:

FIG. 1 shows a prior art interface between a TTL output driver and a CMOS input buffer that is mismatched without buffering.

FIG. 2 shows a prior art interface between a TTL output driver and a CMOS input buffer that is mismatched but buffered by an external pull-up resistor.

FIG. 3 shows a prior art CMOS input buffer interfacing with a TTL output driver that is mismatched but buffered by an extra stage of P and N devices.

FIG. 4 shows, in schematic form, the TTL compatible CMOS input buffer of the present invention with a transmission gate in the first stage having controlled variable impedance.

FIG. 5 shows, in equivalent circuit form, the TTL compatible CMOS input buffer of the present invention of FIG. 4 with a transmission gate in the first stage having controlled variable impedance.

FIG. 6 shows a timing diagram for the TTL compatible CMOS input buffer of the present invention of FIGS. 4 and 5.

FIG. 7 is a table of CMOS MOSFET model parameters for the TTL compatible CMOS input buffer of FIG. 4.

FIG. 8 is a table of DC transfer curves for the TTL compatible CMOS input buffer of FIG. 4.

FIG. 9 is a table of transient analysis for the TTL compatible CMOS input buffer of FIG. 4.

Referring particularly to FIGS. 1 through 9 of the drawings by the characters of reference, there is illustrated a TTL compatible CMOS input buffer for carrying out the objects of the invention.

The schematic diagram of the circuit is shown in FIG. 4. The input signal, which switches between the TTL levels of 0.8 and 2.4 volts is applied to input pad 80, and is coupled through a diode circuit 85 for limiting voltage transients to the input terminal 35 of the first stage buffer 25.

This first stage 25 comprises a P type MOS transistor 15 which receives the input signal at its gate G, and is also connected by its source S to V.sub.cc and by its drain D to the transmission gate 10. This first stage also comprises an N type MOS transistor 20 which receives the same input signal at its gate G, and is connected to ground by its source S and to the transmission gate 10 by its drain D.

When a low TTL signal level of 0.8 volts is applied through the diode network 85 to point 35 and to the gates G of transistors 15 and 20, the N type transistor 20 will cut off and the P type transistor 15 will conduct, resulting in a high output at point 50. Similarly, a high input of 2.4 volts at point 35 will result in a low output at point 50. To speed up this transition, a transmission gate 10 is added to the circuit between transistors 15 and 20.

The purpose of this gate 10 is to isolate transistor 20 during transition, and any variable impedance that can be designed to have a high impedance during transitions, and a low impedance for steady state conditions may be used here.

The particular transmission gate used in this circuit is the arrangement shown, a P type MOS transistor and an N type MOS transistor connected in parallel. Using this arrangement, when a typical TTL low level signal of 0.8 volts is applied to point 35, and therefore, to the gates of P type transistors 15 and 45, both will conduct. In this mode, the impedance of the transmission gate is low due to the conduction of transistor 45. However, as the input voltage at point 35 rises to 2.4 volts, and as transistor 20 starts to conduct, transmission gate transistor 45 cuts off. At the same time, the transmission gate N type transistor 60 has not yet started to conduct. The result is a high impedance between the drains D of transistors 15 and 20. In this mode, as transistor 20 starts to conduct, it sees a high load impedance, and pulls down the voltage at point 50 with a minimum of delay.

The second stage is an ordinary CMOS inverting buffer operating at standard CMOS voltage levels. A high input signal at point 50 turns N type transistor 95 on and P type transistor 90 off resulting in a low output at point 55. Similarly, a low input results in a high output.

FIG. 5 is the equivalent diagram showing the transmission gate 10 as a variable impedance. As explained, the impedance is higher during transition between low and high inputs.

FIG. 6 is a table of waveshapes which assumes a power supply voltage, V.sub.cc, of five volts. V(a) is the input signal at point 35 and is shown initially switching from low to high at the TTL levels of 0.8 and 2.4 volts. Almost immediately, the voltage at point 50, V.sub.c, starts to go low, in spite of the voltage V(b) at point 40 staying high for a significant delay, because of the isolating action of the transmission gate 10. Finally, the inverted output V(d) at point 55 follows the timing of the original input by a small delay.

The FIG. 7 table is a self-explaining set of electrical parameters of the NMOS and PMOS transistors used in the described embodiment.

The FIG. 8 table is a set of circuit voltages and currents, V(a) at point 35, V(b) at point 40, V(c) at point 50, V(d) at point 55 and I(cc) for the entire circuit. The transition in this table occurs between the 10th and 11th lines. That is, for example, as the input voltage V(a) varies from 0.8 to 2.0 volts, the voltage at point 50, V(c), varies from 3.466 volts to 0.3754 volts (3.754.times.10.sup.-1 in the table).

FIG. 9 is a timing table. The output delay when the input goes from 0.8 to 2.4 volts is approximately 14.times.10.sup.-9 sec.

While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes will be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the invention. In addition, many modifications may be made without departing from the essential teachings of the invention.