Method of Making Ultrashort FET Using Oblique Angle Metal Deposition and Ion Implantation

1. Technical Field

The technical field of the invention is in the fabrication of semiconductor devices and in particular to field effect transistor (FET) devices wherein the dimensions involved are less than a micron (.mu.m).

As the speed of response and the packing density of devices in electronic apparatus such as integrated circuits increases, the dimensions required become so small that the specifications are exceeding the tolerances of conventional production processes and apparatus employed in production. Indirect techniques to achieve spacings are being found essential to meet the required dimensions.

2. Background Art

One indirect technique that is currently receiving attention in the art for achieving such very small dimensions is the use of the horizontal or vertical component of a processing operation that is conducted at an angle with respect to the surface on which the device being fabricated is to be formed. The angle processing technique has been used in the art in both deposition and in ion implantation processes. As one illustration, angled deposition is used to form small electrodes as is described in J. Vac. Sci. & Tech. 19, p. 693-696 (1981).

As another illustration the technique of ion implantation is performed at an angle as described in U.S. Pat. Nos. 3,873,371, 4,325,747 and 4,232,439.

Still another indirect technique is the locating source and drain electrodes in FET transistors by using the gate electrode as a mask. This technique has come to be known in the art as self-alignment. It is described in U.S. Pat. No. 3,846,822 involving ion beam milling.

FIGS. 1-6 are schematic illustrations of the intermediate structural features employed in the steps of fabrication of the invention.

The combined use of an angularly deposited mask with a subsequent angular conductivity conversion operation extending partially under that mask permits both shorter dimensions and the ability to accommodate the straggle location change when subsequent processing steps occur.

The mask is deposited at a low angle with respect to a planar surface and a subsequent conductivity conversion, such as ion implantation, extends under the mask providing an ultra-short gate FET.

For clarity of explanation, the fabrication technique will be described in connection with the fabrication of an ultra-short gate self-aligned Metal Oxide Semiconductor Field Effect Transistor (MOSFET) although in the light of the principles set forth, one skilled in the art may readily apply the technique to other structures.

In fabricating ultra-small gates on a MOSFET where the gate is of the order of 0.5 .mu.m a commonly encountered shorting problem appears in the form of a lateral movement with respect to the source and drain usually by diffusion produced by subsequent processing steps. In other words, the edges of the source and drain electrodes "straggle" with respect to the selected locations.

The technique of the invention involves a first angular deposition against a vertical face which is then used as a mask for a subsequent angular conductivity type conversion such as an ion implantation which extends partly under the mask. The first deposition is then removed and a second angular deposition against the vertical face provides much smaller and very precisely positioned gate, source and drain electrodes. By doing this, the final gate electrode has zero or very small overlap with the source and drain electrodes. This enhances the speed and performance of the device.

FIGS. 1-6 describe the individual structural features employed at specific steps as the structure is developed. The same reference numerals for like elements are employed throughout the figures.

Referring first to FIG. 1, a semiconductor substrate 1 of a monocrystalline semiconductor material, such as silicon or gallium arsenide, standard in the art is provided with a surface 2 on which the semiconductor device is to be oriented. On a portion of the surface 2 a material 3 is shaped to provide an abrupt locating face 4 essentially vertical with respect to the surface 2. The material 3 is usually insulating such as an oxide. The height of the locating face 4 is about 5,000 Angstroms. The face 4 can be formed by the standard technique in the art of reactive ion etching.

Referring next to FIG. 2 in fabricating a MOSFET, a precise thickness insulator layer 5 is placed on the surface 2, abutting the locating face 4, and will serve as the thickness of the oxide under the gate. The insulator 5 is fairly thin and it is of the order of 1-200 Angstroms. The usual technique for forming the thin insulator layer 5 on silicon is to thermally grow a thin layer of oxide over the bare silicon surface 2.

Referring next to FIG. 3, a first angular deposition is performed wherein a metal mask 6 is positioned against the face 4. The metal mask 6 has a horizontal dimension labelled A which is the desired length of the MOSFET gate and an added increment which is the expected "straggle" to be accommodated resulting from, for example, the various diffusions that are to take place at the processing temperatures that may occur. This added increment or delta (.DELTA.) is quite easy to estimate as the specifications for semiconductor materials and the materials therewith are well established. The metal for the mask 6 is deposited against the face 4 at a shallow angle shown as .phi. so that a minimum of metal is deposited on the horizontal. The metal that is deposited on the horizontal is so small that it is readily removed by operations such as etching without significantly changing the dimension A. An acceptable range for the angle .phi. is from 5.degree. to 25.degree..

Referring next to FIG. 4, a conductivity type conversion operation such as ion implantation is employed to form the source and drain electrodes. The ion implantation introduces impurities into the crystal 1 to form the regions 7 and 8. In introducing the impurities, damage occurs requiring annealing which contributes to the straggle problem. The estimated straggle is included in the .DELTA. portion of dimension A.

The ion implantation is performed at an angle labelled .gamma. with respect to the vertical and converts the conductivity type of the substrate 1 to the opposite conductivity type in the regions 7 and 8 that will be the source and drain, respectively. The location of one edge of the implanted regions 7 and 8 will be offset by a lateral distance with respect to the mask 6 which is approximately equal to the height of the mask 6 times the tangent of the angle .gamma. of implanting. The offsetting as shown in FIG. 4 moves edge of the drain 8 under the mask 6 at 9 and the source 7 away from the mask 6 at 10.

Referring next to FIG. 5, the mask 6 is now removed by such operations as a selective etch and the ion implant damage in 7 and 8 annealed with the resulting slight movement so that the resulting channel length 11 after the annealing step is essentially the predetermined value used in the dimension A of the mask 6 in FIG. 3.

Referring next to FIG. 6, a second angular metal deposition is made against the face 4 providing the metal gate 12. The angle of the deposition is low with respect to the surface 2 so that again there is a minimum of material on the horizontal surfaces for ease of removal and the dimension of the gate 12 parallel to the surface 2 over what is to become the channel of the FET is readily controlled with respect to the dimension 11. This dimension parallel to the surface 2, which is the thickness of the gate 12, is less than the total channel length and as long as the gap between the gate 12 edge and the drain 8 connection is less than one Debye length, all the injected carriers will be collected at the drain 8.

In the completed structure, the initial sidewall 4 remains in place and serves as a supporting structure for the small high aspect ratio gate 12.

External electrical connections, not shown, for device application purposes are made to the source 7, the drain 8 and the gate 12.

The technique of the invention provides an ultra-short gate FET wherein the gate length is of the order of one-half micron wherein lateral shorting has been taken into consideration in the construction, self-alignment takes place with minimized parasitic gate to source and drain overlap capacitance.

What has been described is a combined indirect technique in which a first angularly deposited member serves as a mask for an angularly directed ion implantation extending under the mask. The mask is removed and a gate is deposited against the same locating face used for the mask but the gate is thinner which permits shorter dimensions and accommodation for later processing step movement.