Method for Producing a Buried Junction Memory Device

This invention relates to the field of semiconductor apparatus, and more particularly to semiconductor devices and to processes for fabricating semiconductor devices, and integrated arrays of such devices.

In short channel MOSFET devices, that is, below 5 micron channel lengths, a threshold voltage instability is caused by the trapping of electrons in the gate oxide during normal device operation. This phenomenon has been discussed in the literature; for example: S. A. Abbas and R. C. Dockerty, "Hot-Carrier Instability in IGFET's," Applied Physics Letters, Vol. 27, pp. 147-148 (1975); T. H. Ning et al., "Threshold Instability in IGFET's Due to Emission of Leakage Electrons from Silicon Substrate into Silicon Dioxide," Applied Physics Letters, Vol. 29, pp. 198-200 (1976). Briefly, the threshold instability is caused by the fact that trapping of the charges in the "gate" oxide produces a charge in the oxide, which modifies the threshold voltage required for turning the device "on" or "off" during operation. Therefore, in order to stabilize the threshold, it would be desirable to have a MOSFET device, and a method for making such a MOSFET device, of such a structure that mitigates threshold voltage instabilities.

In order to obtain an electric field profile in an N-channel MOSFET device, such that trapping of electrons in the oxide is mitigated, a fabrication method for forming the device is used such that, in the resulting device structure, the drain region bulges out from underneath a typically thick oxide and extends in the bulk of the semiconductor to locations underneath, but removed from, the typically thin gate oxide. Thereby, during operation with such a device structure, electric field lines curve away from the gate oxide-semiconductor interface; so that electron trapping in the gate oxide is reduced, if not eliminated.

In a specific embodiment of the invention, upon a major flat (planar) surface of a monocrystalline P-type semiconductive silicon body is grown a relatively thin (200 angstroms, typically) insulating layer of silicon dioxide. Then an insulating silicon nitride layer is deposited on the thin silicon dioxide layer. On top of this nitride layer, a relatively thick (2,000 angstroms, typically) insulating layer of silicon dioxide is deposited. Using suitable conventional masking and etching steps, all three insulating layers are geometrically selectively etched away, in order to expose the portions of the major surface of the silicon body where the drains (and sources in symmetrical structures) are desired in the finished devices. Then the silicon is etched away at these exposed portions, for example, using a plasma etch, thereby creating recess regions each about 0.5 micron deep. Then, donor impurities, such as phosphorous, are implanted in symmetrically limited regions of each recess. The recesses are then oxidized, to fill them with thick silicon dioxide. Next, the originally deposited thick oxide and nitride layers can be removed, leaving thick oxide in the recesses. Heat treatments can optionally be used to push the donor impurities further out under the gate region and up closer to the silicon surface. A bulged buried drain (and bulged buried source, in symmetrical structures) geometry thus results in which the buried drain (and source) bulge from underneath the thick oxide to regions in the silicon body underneath the remaining thin oxide (but not contiguous with the thin oxide). Contacts to the drains (and sources) can then be made by conventional steps of cutting apertures through the thick oxide down to the drains (and sources); and the gate electrode can be deposited by ordinary means, to complete the transistor device.

With some added steps and modifications of the donor impurity implant, various other devices and arrays of devices, such as memory arrays, can be fabricated in a single silicon body.

This invention together with its objects, features, and advantages may be better understood from the following detailed description when read in conjunction with the drawings in which:

FIGS. 1 through 3 show in cross section various stages in the fabrication of a transistor device, in accordance with a specific embodiment of the invention;

FIG. 4 shows a cross section of a transistor memory device, in accordance with an alternate specific embodiment of the invention;

FIGS. 5 and 6 show successive stages in the fabrication of a "source-controlled" MOS capacitor memory device, in accordance with another alternate specific embodiment of the invention; and

FIG. 7 shows a top view of an integrated circuit array of "source-controlled" MOS capacitor memory devices each fabricated in accordance with the steps shown in FIGS. 5 and 6.

Only for the sake of clarity, none of the drawings is to scale.

As indicated in FIG. 1, upon a flat (planar) major surface of a P-type silicon body 10 is grown a thin insulating layer of silicon dioxide 11 about 200 angstroms in thickness, typically by thermal oxidation. Then an insulating layer of silicon nitride 12 is deposited on the thin silicon dioxide layer, and a thick insulating layer of silicon dioxide 13 is deposited on the nitride layer. Next, using a photoresist masking layer 14 to define the apertures to be etched, conventional etching techniques are used to etch the apertures through, respectively, the thick silicon dioxide layer, the nitride layer, and the thin silicon dioxide layer. In this way, there remains the nonetched layers 11, 12, and 13 of thin silicon dioxide, silicon nitride, and thick silicon dioxide, respectively. Using these layers as a mask, the exposed portions of the surface of the silicon body 10 are etched to form recesses, typically approximately 0.5.mu. in depth. This etching of recesses into the silicon can be carried out by means of exposure to a plasma etch, for example, as known in the art. Then phosphorus impurity nuclei are introduced into limited regions 15 and 16 of different recesses by means of ion implantation, typically by a phosphorus ion beam perpendicular to the silicon surface. In this way, the N+ regions 15' and 16' are created, containing an excess phosphorus donor concentration of typically about 5.times.10.sup.13 atoms per square centimeter to a depth of 10.sup.-5 centimeter in the silicon. At this point in the fabrication process, the stage is reached as shown in FIG. 1.

As indicated in FIG. 2, the exposed surfaces of the recesses are thereafter oxidized, either by a known steam or dry thermal oxidation process, thereby forming local oxide regions 17 and 19. The choice of oxidation process depends upon the ultimate phosphorus distribution desired, since all thermal treatments subsequent to the phosphorus implant affect the contours (P-N junctions) of the now buried N+ regions 15 and 16, as should be obvious to the worker in the art. In all these treatments, therefore, it is important that the controus of the buried N+ regions 15 and 16 do not reach the interface of the oxide layer 11 (to serve as gate oxide) particularly when such an N+ region is to serve as a drain of a transistor. Thus, such subsequent heat treatments can be used for the purpose of tailoring the N+ regions and hence the operating characteristics of the final device, particularly the threshold voltage. In any event, the formation by local oxidation of regions 17 and 19 is accompanied by a simultaneous driving of the phosphorus-rich buried N+ regions 15 and 16 in front of the oxide boundary.

As indicated in FIG. 3, the originally deposited thick oxide layer and the nitride layer are thereafter removed, and further heat treatments can be used to push the phosphorus-rich N+ regions 15 and 16 further out under the gate region (located at the original oxide-silicon interface) and closer to the original oxide-silicon interface. A protruding geometry for the buried N+ regions 15 and 16 can thus be achieved as shown in FIG. 3, that is, these N+ regions extend in the bulk of the semiconductor further out under the gate region than the local oxide regions 17 and 19. Apertures can then be opened in these oxide regions for source and drain contacts 21 and 22, respectively, and a gate electrode 20 (FIG. 3) can then be deposited also, as known in the art. Thus, a completed transistor device is obtained.

FIG. 4 illustrates an alternative embodiment of the invention, which is made in the same way as previously described for the device shown in FIG. 3 except for the added step of a self-aligned implant of a thin N-type "skin" or channel region 23 running along the original oxide-semiconductor interface between local oxide regions 15 and 16. This N-type region 23 is advantageously formed by implantation of ions of a significant impurity dopant after growth of the local oxide regions 15 and 16 and after removal of the original thin oxide layer 11 therebetween by a quick etch sufficient to remove thin oxide (but not thick oxide). The implant of this impurity, such as phosphorus, locally changes the conductivity to N type, as known in the art. After such an implant of the N "skin" region 23, the gate oxide 11' is regrown by thermal oxidation, typically at 1050.degree. C., which also anneals the device. Alternatively, the N "skin" region 23 is implanted just subsequent to the growth of the gate oxide, in order to minimize diffusion of this N region. In any event, this N region 23 can be used for memory device applications in which depletion of electrons from the "skin" region by suitable applied voltages can serve as a logical "0" state as opposed to a normal (undepleted) "1" state, by reason of a permanent modification of the threshold voltage caused by such electron depletion.

In the devices illustrated in FIG. 3 or 4, the electric field lines in the vicinity of the drain region 16 are curved away from the interface of the gate oxide 11 or 11'. Accordingly, electrons moving along the channel from the buried source region 15 to the buried drain region 16 (and gaining momentum thereby) do not tend to be injected into the gate oxide but are collected by the drain in accordance with the desired mode of operation. Moreover, the bulging of the source and drain regions toward each other tends to shield the channel from the undesired injection of electrons originating in the bulk of the semiconductor caused by the "substrate" potential of the semiconductor body, which causes undesirable leakage currents during source to "substrate" reverse bias operation.

The fact that the source region 15 is removed from the channel at the oxide-semiconductor surface means that, in addition to the above advantages, there is a potential barrier during operation along the source to channel path. The height and width of this barrier can be tailored either by surface doping (for example, by implantation of variously doped intervening layers) or by location of the source, or both, thus providing added flexibility of control over operating device characteristics. Similarly, there is a potential barrier at the drain which can be similarly tailored for the purpose of reducing threshold (background) currents for low voltage operation. Finally, parasitic capacitances are reduced by reason of the burial of source and drain regions as compared with conventional planar device structures.

FIGS. 5 and 6 illustrate intermediate and final stages, respectively, of the fabrication of "source-controlled" MOS capacitor devices. These devices take deliberate advantage of the control over source-to-channel barrier mentioned above. The devices are fabricated in the same way as described previously in connection with FIGS. 1 through 3, except for the implantation of phosphorus ions at an angle .theta. to the normal to the major surface, in order to produce an asymmetry in the location of the buried N.sup.+ regions 65 and 66 with respect to location in the recesses. Accordingly, the distances d.sub.1 and d.sub.2 of nearest approach of buried N.sup.+ region 65 and 66 to the intervening remaining flat surface portion of the semiconductor body are different. A given memory cell is defined essentially by the crosspoint overlap of a gate electrode stripe 60 with a buried N.sup.+ region, such as region 66. Thereby, only the N.sup.+ region of nearest approach to the flat surface is active in the operation of any given cell. The cell operates therefore not as MOSFET but as a "source-controlled" capacitor. After the local oxidation, these N.sup.+ regions bulge out under the gate oxide layer 61 only at the left-hand edges of these N.sup.+ regions but not at the right-hand edges. Moreover, an implanted N.sup.+ "skin" region 62 and a deeper implanted P.sup.+ barrier region 64 are formed at and near the surface, respectively, with an intervening P type region 63 as described below; and the gate electrode 60 is continuous and elongated as an electrode stripe, that is, encompasses many cells. These implants may be performed after gate oxide growth to ensure limited spread of these regions by thermal diffusion in subsequent processing. The implanted N.sup.30 region 62 is in present technology typically about 3 microns by 10 microns in area, due to limitations in present charge-sensor technology. Each cell has an operating region defined by the left-hand edge of a buried N.sup.+ region (such as region 66) and the proximate portion of the gate oxide together with the intervening portion N.sup.+ and P.sup.+ implanted regions 62 and 64, respectively.

The N.sup.+ and P.sup.+ regions 62 and 64 are formed by conventional ion implantation preferably after the growth of the gate oxide. The P-type region of substrate chip intervening between the N.sup.+ source region 65 and P.sup.+ implanted region 64 can be negligibly thick and will be of the same doping as that of the bulk of the substrate chip, which in turn can be the same as that of the intervening P-region 63.

For an illustrative cell design with an overlying gate oxide layer 61 thickness of 1,000 angstroms, the following approximate values of design parameters are expected to be suitable:

N.sup.+ implanted region 62:

thickness = 300 angstroms,

doping = 3.times.10.sup.12 atoms per square centimeter (arsenic);

intervening P region 63:

thickness = 0.07 micron,

doping = 4.times.10.sup.15 atoms per cubic centimeter;

P.sup.+ implanted region 64:

thickness = 0.22 micron,

doping = 3.3.times..sup.10 12 per square centimeter (boron);

N.sup.+ source region 65:

doping = 10.sup.18 atoms per cubic centimeter.

For another illustrative cell design, the overlying gate oxide layer 61 can be about 500 angstroms thick in combination with the following approximate values of design parameters:

N.sup.+ implanted region 62: same;

intervening P region 63:

thickness = 0.7 micron,

doping = same;

p.sup.+ implanted region 64:

thickness = 0.23 micron,

doping = 2.8.times.10.sup.12 atoms per square centimeter;

N.sup.+ source region 65: same.

The devices shown in FIG. 6 can be integrated in a rectangular cross-point memory array 70, as shown in FIG. 7. Gate electrode stripes G.sub.1, G.sub.2, G.sub.3, . . , run vertically in columns, while N.sup.+ buried source region stripes S.sub.1, S.sub.2, S.sub.3, . . . , run horizontally in rows. Each of the crosspoint areas enclosed by the dotted line ovals represents a separate two-terminal memory cell defined by the overlap of a gate electrode stripe with a buried source region stripe plus neighboring implanted surface regions. The accumulation vs. no accumulation of charge in the implanted surface region of a cell represents the different memory states of that cell.

The operation of a given cell will now be described. If the buried source stripe and gate electrode of the cell are both grounded (at the same voltage as that of the semiconductor substrate chip), then there is a potential barrier in the P.sup.+ implanted region which presents an obstacle against the transfer of electrons between the buried source region and the N.sup.+ implanted region of that cell. On the other hand, if a positive voltage is applied to the source region, which is more than sufficient to produce "punch-through," then this barrier is overcome and electrons stored in the N.sup.+ implanted region can flow into the source. This "punch-through" voltage will be denoted by V.sub.p. Accordingly, the application to the source region of a positive voltage V.sub.R > V.sub.p (while the gate electrode is grounded) is suitable for reading out the presence vs. absence of electrons stored in the N.sup.+ implanted region. Conversely, if a positive voltage is applied to the gate electrode (while the source region is grounded), which is more than sufficient to produce "punch-through" in the opposite sense from that produced by V.sub.R, then elctrons will flow from the source region to the N.sup.30 implanted region until the latter region contains sufficient electrons to establish equilibrium. When this equilibrium occurs for a given voltage V.sub.W thus applied to the gate electrode, the given memory cell is said to be in its "1" state; whereas, in the absence of such electrons in the N.sup.+ implanted region, the cell is in its "0" state.

For an overlying gate oxide layer 61 of 1,000 angstroms in thickness, the following approximate values are expected to be operative: V.sub.P = 3.5 volts, V.sub.R = 15 volts, V.sub.W = 11 volts; for an overlying gate oxide of 500 angstroms V.sub.P = 2.5 volts, V.sub.R = 9 volts, V.sub.W = 5.5 volts.

Operation of the cells in the array 70 can be performed as follows. In order to perform the readout of all cells in a selected row line (along a selected source stripe), the source stripe of the given row is subjected to an applied voltage of V.sub.R while simultaneously all other source stripes are maintained at "ground" potential (same potential as grounded semiconductor substrate chip). Flip-flop or other charge detectors, each connected to a different column line (gate electrode stripe), will then detect the flow vs. no flow of electron charge in the cells along the selected row in accordance with the "1" vs "0" memory states of each cell at the crosspoint of the corresponding column and selected row. This readout is destructive and thus a re-write operation is required if it is desired to restore the original "1" memory state, if any. This re-write can be performed by applying suitable voltages for selected write-in operation in each cell on the selected row.

In order to write in a given cell located at the crosspoint of a selected row and selected column, the selected row source stripe is maintained at ground potential while all other rows are subjected to V.sub.W, and simultaneously the selected column gate electrode stripe is subjected to V.sub.W while all other column gate electrode stripes are grounded or, alternatively, subjected to a voltage of V.sub.W - V.sub.P (in order to inhibit inadvertent erase of the non-selected column cells). In this manner, only the selected crosspoint cell is written in by an electron charge transfer from its buried source region to N.sup.+ implanted region.

Although the invention has been described in detail in terms of specific embodiments, various modifications can be made without departing from the scope of the invention. For example, the semiconductor body can be N-type and the implanted regions in the recesses can be P.sup.+ type. Moreover, the devices of the types illustrated in FIGS. 3 and 4 can, with obvious modifications, be incorporated into crosspoint arrays similar to the type of array 70 shown in FIG. 7. Also, other impurities of opposite conductivity type from that of the P-type bulk of the semiconductor body can be used instead of phosphorus.