US 4,388,653 AGrant
Method for Controlling Writing Timings of Picture Signals to Be Stored in a Memory
Issue Date:1983-06-14
•5 Claims
•5 Drawing Sheets
Abstract
A method for controlling writing timings of picture signals to be stored in a memory, for use in a picture reproducing machine wherein the picture signals picked up by picture scanning means are stored in the memory and then the picture signals are read out of the memory, and wherein reproduction pictures are recorded on a recording film by a reproduction recording means by using the picture signals read out. The picture signals are latched consecutively into latch circuits arranged before the memory by a first clock pulse generated by the picture scanning means, and then the picture signals read out of the latch circuits in the latching order by a second clock pulse generated by the reproduction recording means are written into the memory.
Metadata
Assignee
- Dainippon Screen Seizo Kabushiki Kaisha
Inventor
- Mitsuhiko Yamada
Application Information
Application Number:US 1816330
Filing Date:1980-08-26
Priority Date:1979-08-28
Art Unit:235
Classifications
IPC:
H04N 122
Field of Search:
358318296;302;267;264;78;77;75;127;138311
Patent Drawings (5 sheets)
Description
Background of the Invention
This invention relates to a method for controlling writing timings of picture signals to be stored in a memory, picked up by picture scanning means, for use in a picture reproducing machine such as a color scanner and a color facsimile.
A picture reproducing machine such as a color scanner for plate-making, or the like, having a buffer memory between a picture scanning means and a reproduction recording means, which controls reproduction scales and layout positions of reproduction pictures, has been proposed. In this case, in order to minimize the capacity required of such a buffer memory, picture and recording cylinders are rotated at the same speed, and each writing or reading operation of a picture signal is carried out one by one in a sampling interval, but, when the reproduction scale is changed at a certain value, several writing or reading operations are conducted in the sampling interval.
This sampling interval corresponds to the interval of picture elements, which determines the analytical power of the picture scanning means and the reproduction recording means. In the color scanner for plate-making, the analytical power required is very high, and thus the sampling interval is quite short.
The picture and the recording cylinders are controlled accurately so as to be revolved at the same speed. However, a very small amount of inequality in the rotation of the cylinders due to various mechanical errors is inevitable. Accordingly, the very small amount of relative speed variations of the cylinders do occur, and, in practice, it is impossible to adjust every starting position per one rotation of the scannings with an accuracy more than the analytical power of the picture signals.
Hence, the writing and the reading of the picture signal in a single sampling interval may be performed by using a clock pulse which is synchronous with either the picture scanning means or the reproduction recording means, but by using this clock pulse, as mentioned above, when the relative speed variations of the cylinders occur, the reproduction pictures are deformed largely rather than depending on the accuracy of each picture scanning or reproduction recording means.
In order to avoid the deformation of the reproduction picture, the writing should be carried out by a clock pulse which is synchronous with the picture scanning means and the reading should be carried out by a clock pulse which is synchronous with the reproduction recording means. However, the accesses of the writing and the reading in the memory are not always carried out in the same time. Accordingly, by the partial relative speed variation of the cylinders or the disorder of the starting positions of the scannings the phase of the clock pulses for writing and reading are shifted irregularly, and thus the timings of the writing and the reading clock pulses are overlapped, with the result of the deformation of the reproduction picture by the lack of the picture element, and so forth.
Further, the phases of the writing and the reading clock pulses are in proportion to the rotation speeds of the picture and the recording cylinders, and, if the speeds of the two cylinders synchronized two clock pulses having the same phase are obtained. Hence, the phase variations of the two clock pulses by the rotation inequalities, and the like, causes a beat.
This kind of beat is a zero beat, or the like, having a long frequency, and therefore, if the timings of the two clock pulses overlap each other, such a condition will continue for a relatively long time, resulting in a large scale of deformation of the reproduction picture.
In a conventional layout scanner, in which a plurality of original pictures are reproduced on a recording film according to the desired layout, a plurality of picture scanning means and a reproduction recording means are arranged in parallel, and a buffer memory is connected therebetween, wherein the picture signals obtained by the picture scanning means are stored into the memory, and then by reading out the picture signals consecutively of the memory the reproduction pictures are reproduced in the desired layout positions by the reproduction recording means. In this embodiment, since the plurality of picture scanning means are driven in parallel, there is less time to control the writing timings of the picture signals and thus it is rather difficult to do it.
Summary of the Invention
Therefore, it is an object of the present invention to provide a method for controlling writing timings of picture signals to be stored in a memory, picked up by picture scanning means, for use in a picture reproducing machine, free from the above described disadvantages, which is capable of reproducing exact reproduction pictures, and prevents the reproduction pictures from being deformed, and which is stable and reliable.
According to the present invention there is provided a method for controlling writing timings of picture signals to be stored in a memory, for use in a picture reproducing machine wherein the picture signals picked up by picture scanning means are stored in the memory and then the picture signals are read out of the memory, and wherein reproduction pictures are recorded on a recording film by a reproduction recording means by using the picture signals read out, comprising the steps of (a) latching the picture signals consecutively into latch circuits arranged prior to the memory by a first clock pulse generated by the picture scanning means, and (b) writing into the memory the picture signals read out of the latch circuits in the latching order by a second clock pulse generaged by the reproduction recording means.
Brief Description of Drawings
In order that the present invention may be better understood, preferred embodiments will be described with reference to the accompanying drawings, in which:
FIG. 1 is a block diagram of a layout color scanner which is capable of performing a method according to the present invention;
FIG. 2 is a time chart showing a relation between writing and reading clock pulses shown in FIG. 1;
FIG. 3 is a schematic view of one embodiment of a writing timing control circuit shown in FIG. 1;
FIG. 4 is a schematic view of another embodiment of a writing timing control circuit in FIG. 1;
FIG. 5 is a time chart of pulse signals appeared in FIG. 4; and
FIG. 6 is a schematic view of still another embodiment of a writing timing control circuit of FIG. 3, having a speed adjusting means.
Description of Preferred Embodiments
Referring now to the drawings there is shown in FIG. 1 a layout scanner which is capable of performing a method according to the present invention, comprising two picture scanning means 1 of the same type, a reproduction recording means 2, and a one block of buffer memory 3 arranged therebetween.
Picture cylinders 4 of the picture scanning means 1 and a recording cylinder 5 having the same diameter as the picture cylinders 4, of the reproduction recording means 2 are driven at the same speed by synchronous motors 6 and 7. The rotation speeds of the cylinders 4 and 5 and standard positions 10 and 11 formed on the cylinders 4 and 5 are detected in the form of electric pulse signals by rotary encoders 8 and 9 which are coaxially disposed to the cylinders 4 and 5.
A pickup head 12 of each picture scanning means 1 is moved in the direction of the cylinder's axis along a screw rod 14 by a motor 13 such as a pulse motor. A recording head 15 of the recording means 2 is moved in the direction of the cylinder's axis along a screw rod 17 by a motor 16.
Each picture scanning means 1 is provided with an operational circuit 18 which operates color control conditions such as a masking, a color correction, a detail emphasis, and so forth, of analog picture signals a.sub.1 or b.sub.1 obtained by scanning an original picture A or B photoelectrically by the pickup head 12. The operational circuit 18 outputs an analog picture signal a.sub.2 or b.sub.2 operated to an analog-digital converter 19, hereinafter referred to as an A/D converter, in which the signal a.sub.2 or b.sub.2 is converted into a digital picture signal a.sub.3 or b.sub.3. The operational circuit 18 may be positioned after the A/D converter 19 and in such a case, it should be a digital circuit. The digital picture signal a.sub.3 or b.sub.3 is sent to a writing timing control circuit 20 comprising a timing controller 25, a register 26, and a data selector 27.
The rotary encoder 8 or 9 generates a plurality of timing pulses g.sub.1 or e.sub.1 and a start pulse g.sub.2 or e.sub.2 in the standard position 10 or 11 per one rotation of the cylinder 4 or 5, which are sent to a clock pulse generator 21 or 22. The clock pulse generator 21 or 22 increases the frequency of the timing pulse g.sub.1 or e.sub.1 by a phase-lock loop circuit, or the like, to output a clock pulse g.sub.3 or e.sub.3.
When the rotation speeds of the cylinders 4 and 5 are the same, the clock pulses g.sub.3 and e.sub.3 are adjusted to the same phase, but the clock pulse generators 21 and 22 are not synchronized one another. The clock pulse generator 21 or 22 reforms the wave-shape of the start pulse g.sub.2 or e.sub.2 into a start pulse g.sub.4 or e.sub.4 having the same extent of accuracy as the analytical power of the clock pulse g.sub.3 or e.sub.3.
The clock pulse e.sub.3 is sent to a two-phase clock pulse generator 23 and is divided there into a pair of two-phase writing clock pulses e.sub.3a and e.sub.3b having the same period as that of the clock pulse e.sub.3 and a duty-cycle of less than 50% of a high level pulse width. Each of the two-phase clock pulses e.sub.3a and e.sub.3b has a phase difference 180.degree. from the other's. From the two-phase clock pulses e.sub.3a and e.sub.3b a pair of two-phase reading clock pulses e.sub.R and e.sub.R ' are prepared. Each two-phase clock pulse e.sub.R or e.sub.R ' is raised to the high level before that of the two-phase clock pulse e.sub.3a or e.sub.3b, as shown in FIG. 2.
In this embodiment, one of the two-phase clock pulses e.sub.R and e.sub.R ' is required. For example, the clock pulse e.sub.R is sent to a digital-analog converter 24, hereinafter referred to as a D/A converter, of the recording means 2, and the reading order input terminal of the memory 3.
The two-phase writing clock pulses e.sub.3a and e.sub.3b are sent to the writing timing control circuits 20 for controlling the timings of the writing of the picture signals a.sub.3 and b.sub.3 into the memory 3.
In the writing timing control circuit 20, the timing controller 25 compares the phase difference between the clock pulse g.sub.3 for determining the sampling time of the A/D converter 19 and the clock pulse e.sub.3a or e.sub.3b for determining the writing timing of the memory 3 and the pulse numbers of the clock pulses g.sub.3 and e.sub.3a or e.sub.3b per a certain time, and outputs a writing pulse gw whose timing is not overlapped to that of the reading timing of the memory 3, to the writing order input terminal of the memory 3.
The picture signals a.sub.3 or b.sub.3 are registered in the register 26 in series in synchronization with a signal g.sub.5 generated by the timing controller 25. The register 26 outputs a group of picture signals a.sub.4 or b.sub.4 in parallel, to the data selector 27. The data selector 27 rearranges the picture signals a.sub.4 or b.sub.4 arranged in parallel, to the regular serial order of picture signals a.sub.5 or b.sub.5 by a select signal g.sub.6 generated by the timing controller 25 so as to maintain the orders of the picture signals a.sub.3 or b.sub.3 by eliminating the overlap of the writing and the reading timings in the memory 3, and sends the picture signals a.sub.5 or b.sub.5 to a picture selector 28 for laying out the recording pictures.
Either picture signal a.sub.5 or b.sub.5 is fed selectively and alternately from the picture selector 28 to the data input terminal of the memory 3 in the basic period T by using the two-phase clock pulses e.sub.3a and e.sub.3b. The basic period T means the basic sampling or recording timing period which is predetermined in the clock pulse generators 21 and 22 and is to be controlled to a fixed value macroscopically.
A writing address signal X and a reading address signal Y are fed from an address controller 29. The writing address signal X is divided into address signals Xa and Xb for the original pictures A and B, and is output from the address controller 29 as an address number predetermined to be recorded depending on the writing pulse gw generated by the timing controller 25 for each original picture A or B.
The address signals Xa and Xb are alternately fed to the memory is synchronization with the writing timings for the original pictures A and B by an address selector 30 which is controlled by the two-phase clock pulses e.sub.3a and e.sub.3b.
The reading address signal Y is synchronized with the scanning position of the recording means 2 and possesses an address addressed in order of the addresses of the memory 3 by the address controller 29. The reading address signal Y reads the picture signal a.sub.6 or b.sub.6 for the original picture A or B out of the memory 3 to the D/A converter 24 in synchronization with the reading clock pulse e.sub.R.
The address controller 29 is connected to a layout position input means 31 which inputs the recording positions of the original pictures A and B, that is, the coordinates of the four corners of the reproduction pictures A' and B' to be recorded on a recording film F mounted to the recording cylinder 5, as the address numbers to the address controller.
The address numbers in the four corners of the reproduction pictures A' or B' are controlled by the address controller 29 so as to correspond to the writing start and end points of the picture signals a.sub.5 or b.sub.5.
When the recording head 15 is positioned in the recording position for the original picture A or B, the picture signal a.sub.6 or b.sub.6 read out of the memory 3 is converted into an analog picture signal a.sub.7 or b.sub.7 in the D/A converter 24, which is fed to the recording head 15. Thus, the recording head 15 records the reproduction picture A' or B' in the desired layout position on the recording film F by means of the analog picture signal a.sub.7 or b.sub.7.
If the reproduction pictures A' and B' are recorded with different reproduction scales from the original pictures A and B, for instance, the addresses of the picture signals stored in the memory 3 are repeatedly read out or are partly skipped, as disclosed in Japanese Patent Laying-Open Specification No. 54-65601 U.S. patent application Ser. No. 110,127, filed on July 8, 1980, by the same applicant assignee as the present invention.
In FIG. 3 there is shown one embodiment of the writing timing control circuit 20 in FIG. 1, which performs a method according to the present invention.
The timing controller 25 comprises a pair of base n binary-code counters 32 and 33, a pair of base n decoders 34 and 35 which convert counted codes d.sub.1 and d.sub.2 in the counters 32 and 33 into base n alternative signals d.sub.3 and d.sub.4, and two groups of n AND gates 36 and 37 for the alternative signals d.sub.3 and d.sub.4.
The clock pulses g.sub.3 and e.sub.3a are fed to calculation input terminals T of the counters 32 and 33, respectively, and the start pulse g.sub.4 is input to preset or initial terminals P.S of the counters 32 and 33 so as to carry out the initial set of the counters 32 and 33.
The clock pulse g.sub.3 is commonly fed to the AND gates 36, and the decoder 34 selects one of the AND gates through which the clock pulse g.sub.3 can pass. The clock pulse e.sub.3a is commonly fed to the AND gates 37, and the decoder 35 selects one of the AND gates through which the clock pulse e.sub.3a can pass.
The output signal from the AND gates 36, corresponding to the signal g.sub.5 in FIG. 1, is fed to the register 26. The output signal from the AND gates 37, corresponding to the select signal g.sub.6 in FIG. 1, is fed to the data selector 27. The register 26 comprising n latch circuits 26.sub.1 -26.sub.n is capable of holding n signals in the same time, each signal being written in or read out of the register 26 independently. When each of the AND gates 36 passes the signal g.sub.5, the corresponding latch circuit of the register 26 holds the picture signal a.sub.3. In this case, when the new signal is latched in the latch circuit, the previous signal is cleared. The latch circuits 26.sub.1 -26.sub.n, while they hold the signals, are sending all the signals latched therein to the data selector 27, in parallel.
The data selector 27 comprises n data switch circuits 27.sub.1 -27.sub.n which correspond to the latch circuits 26.sub.1 -26.sub.n and the n AND gates 37. When each of the AND gates 37 passes the signal g.sub.6, the corresponding data switch circuit is opened so as to pass the picture signal a.sub.4 latched in the corresponding latch circuit as the picture signal a.sub.5 to the picture selector 28.
The start pulse g.sub.4 presets the counter 32 with a count number n/2 and the counter 33 with a count number 0 before starting the scanning. Then, the counters 32 and 33 count firstly the clock pulses g.sub.3 and e.sub.3a with the count numbers (n/2+1) and 1, respectively. The count number of the counter 32 counts ahead of n/2 numbers as compared with the counter 33.
Accordingly, until the data selector 27 passes the signal latched in the register 26 according to the count number counted in the counter 32, viz., the count number in the counter 33 comes up with that in the counter 32, there is sufficient time that the counter 33 can count n/2 clock pulses e.sub.3a to spare. This means that each of the latch circuits 26.sub.1 -26.sub.n can hold the signal of n/2 numbers ahead as well as the signal now required for processing.
Consequently, if the recording cylinder 5 rotates faster than the normal speed, i.e. the relative counting speed of the counter 33 becomes faster than that of the counter 32, until the count numbers of the counters 32 and 33 become the same, the writing timing of the picture signal in the memory 3 does not fall into disorder.
Further, by blanking the first half latch circuits 26.sub.1 -26.sub.n/2, that is starting the storing of the picture signals into the latch circuits from the (n/2+1) number, if the relative counting speed of the counter 33 becomes slower than that of the counter 32, until the count numbers of the counters 32 and 33 become the same at one-cycle delay of the counter 33, the register can hold the signals of n/2 numbers ahead to be processed, and thus the writing timing of the picture signal in the memory 3 does not fall into disorder.
In the embodiment shown in FIG. 3, the clock pulse e.sub.3a is used as the writing pulse gw.
From the above description, it is readily understood that, assuming that the total numbers of the picture signals a.sub.3 and a.sub.5 written in the register 26 and read out of the data selector 27 by the clock pulses g.sub.3 and e.sub.3a from the time which the start pulse g.sub.4 is started, to a certain time are D.sub.1 and D.sub.2, when the relative difference between D.sub.1 and D.sub.2 is smaller than n/2, i.e. .vertline.D.sub.1 -D.sub.2 .vertline.<n/2, the writing timing of the picture signal in the memory 3 does not fall into disorder.
In this case, the total signal numbers D.sub.1 and D.sub.2 depend on the signal numbers corresponding to the one rotation of the cylinders 4 and 5, and the effective scanning length in the direction of the cylinder's periphery, determined according to the sizes of the original pictures A and B, and the relative difference between .vertline.D.sub.1 -D.sub.2 .vertline., depends on the difference between the relative rotation speeds of the cylinders 4 and 5, that is, the frequency difference between the clock pulses g.sub.3 and e.sub.3a. Hence, the maximum difference .vertline.D.sub.1 -D.sub.2 .vertline..sub.max between D.sub.1 and D.sub.2 per one scanning period in the direction of the cylinder's periphery may be estimated by the accuracies of the rotation speeds of the motors 6 and 7.
In order to minimize such a relative speed deviation, that is, the maximum difference .vertline.D.sub.1 -D.sub.2 .vertline..sub.max, an automatic speed adjusting means may be arranged between the motors 6 and 7, as hereinafter described with reference to FIG. 6. However, even if the automatic speed adjusting means is provided, in practice, it is almost impossible to remove the relative speed deviation with an accuracy required for the color scanner, but it is possible to minimize sufficiently the time to spare corresponding to n/2 numbers described above.
In FIG. 4 is shown another embodiment of the writing timing control circuit 20, that is, the number n equals three in FIG. 3 as regards the latch circuits of the register 26, the data switch circuits of the data selector 27, the AND gates 36 and 37, and so forth.
In this embodiment, ternary binary-code counters 32a and 33a, ternary decoders 34a and 35a, two groups of three AND gates 36a and 37a, three latch circuits 26.sub.a1 -26.sub.a3 of the register 26, and three-states type bus buffers 27.sub.a1 -27.sub.a3 of the data selector 27 correspond to the base n binary-code counters 32 and 33, the base n decoders 34 and 35, the n AND gates 36 and 37, the n latch circuits 26.sub.1 -26.sub.n of the register 26, and the data switch circuits 27.sub.1 -27.sub.n of the data selector 27 in FIG. 3, respectively.
A count pulse g.sub.7 hereinafter mentioned is input to the terminal T of the counter 33a. The counters 32a and 33a are preset to three by the start pulse g.sub.4.
The clock pulse e.sub.3a is commonly fed to the AND gates 37.sub.a1 -37.sub.a3 via an AND gate 39 which is opened or closed by a flip-flop circuit 38 for starting the count of the counter 32a before that of the counter 33a, a delay circuit 40 which delays the clock pulse e.sub.3a at a time t.sub.1, and an AND gate 41 which passes the clock pulse e.sub.3a when the count pulse g.sub.7 is input to the counter 33a.
The flip-flop circuit 38 is set by the start pulse g.sub.4, and outputs a signal g.sub.8 which closes the AND gate 39. The AND gate 39 is reset to be opened by an output signal g.sub.51 from the AND gate 36.sub.a1 when the counter 32a counts the number one.
The AND gate 41 is opened by a signal g.sub.9 which is output by a one-shot multivibrator 42 when the count signal g.sub.7 is fed to the counter 33a, and passes a clock pulse e.sub.3a ' to the three AND gates 37.sub.a1 -37.sub.a3 when the count pulse g.sub.7 is input to the counter 33a.
The signals G.sub.51, g.sub.52 and g.sub.53 output from the AND gates 36.sub.a1 -36.sub.a3 are sent to the latch circuits 26.sub.a1 -26.sub.a3, so that the latch circuit 26.sub.a1 -26.sub.a3 may latch the picture signals a.sub.3, and are also sent to a pulse generator 43 which generates the count pulse g.sub.7.
The pulse generator 43 comprises three queue control circuits 43.sub.1, 43.sub.2 and 43.sub.3 corresponding to the three latch circuits 26.sub.a1, 26.sub.a2 and 26.sub.a3. Each queue control circuit 43.sub.1, 43.sub.2 or 43.sub.3 comprises two D-type flip-flop circuits 43.sub.a1 and 43.sub.b1, 43.sub.a2 and 43.sub.b2, or 43.sub.a3 and 43.sub.b3, arranged in series.
For example, the queue control circuit 43.sub.1 is set by adding the signal g.sub.51 output from the AND gate 36.sub.a1 to the terminal T of the first flip-flop circuit 43.sub.a1. On this occasion, the first flip-flop circuit 43.sub.a1 outputs a signal f.sub.1 to the terminal D of the second flip-flop circuit 43.sub.b1, and the clock pulse e.sub.3a through the AND gate 39 is fed to the terminal T of the second flip-flop circuit 43.sub.b1. Only when the first flip-flop circuit 43.sub.a1 is in the set state, the output signal from the second flip-flop circuit 43.sub.b1 is inverted by the clock pulse e.sub.3a to raise the output signal. This output signal raised is fed to the terminal T of the counter 33a through an OR gate 44.
The other queue control circuits 43.sub.2 and 43.sub.3 have the same construction and function as the one 43.sub.1 described above, and the output signals from the second flip-flop circuits 43.sub.b2 and 43.sub.b3 are sent to the terminal T of the counter 33a via the OR gate 44 in the same manner as described above. To the terminals T of the first flip-flop circuits 43.sub.a2 and 43.sub.a3 are fed the output signals g.sub.52 and g.sub.53 from the AND gates 36.sub.a2 and 36.sub.a3, and the clock pulse e.sub.3a is supplied to the terminals T of the second flip-flop circuits 43.sub.b2 and 43.sub.b3.
Each of the three queue control circuits 43.sub.1, 43.sub.2 and 43.sub.3 and each of the three latch circuits 26.sub.a1, 26.sub.a2 and 26.sub.a3 are actuated by the signal g.sub.51, g.sub.52 or g.sub.53 output from the AND gate 36.sub.a1, 36.sub.a2 or 36.sub.a3 as soon as they receive the output signal g.sub.51, g.sub.52 or g.sub.53, and, in the same time, the signal latched in the latch circuit 26.sub.a1, 26.sub.a2 or 26.sub.a3 is read out of the bus buffer 27.sub.a1, 27.sub.a2 or 27.sub.a3.
Each first flip-flop circuit 43.sub.a1, 43.sub.a2 or 43.sub.a3 of the queue control circuit 43.sub.1, 43.sub.2 or 43.sub.3 corresponding to the latch circuit 26.sub.a1, 26.sub.a2 or 26.sub.a3 which performs the reading out by the bus buffer 27.sub.a1, 27.sub.a2 or 27.sub.a3 actuated by the signal g.sub.61, g.sub.62 or g.sub.63 output from the AND gate 37.sub.a1, 37.sub.a2 or 37.sub.a3, is reset by the signal g.sub.61, g.sub.62 or g.sub.63 which is sent to the first flip-flop circuit 43.sub.a1, 43.sub.a2 or 43.sub.a3 via an OR gate 45.sub.1, 45.sub.2 or 45.sub.3.
Each signal g.sub.61, g.sub.62 or g.sub.63 output from the AND gate 37.sub.a1, 37.sub.a2 or 37.sub.a3 is sent to an OR gate 46 which outputs the writing pulse gw. The writing pulse gw is sent to the second flip-flop circuits 43.sub.b1, 43.sub.b2 and 43.sub.b3 via an inverter 47 to reset them at the same time.
Each first flip-flop circuit 43.sub.a1, 43.sub.a2 or 43.sub.a3 of the queue control circuit 43.sub.1, 43.sub.2 or 43.sub.3 is reset as soon as the signal latched in the corresponding latch circuit 26.sub.a1, 26.sub.a2 or 26.sub.a3 is read out. The second flip-flop circuits 43.sub.b1, 43.sub.b2 and 43.sub.b3 are all reset when one of the signals latched in the latch circuits is read out.
In FIG. 5 is shown a time chart of the pulse signals appeared in FIG. 4, in which P.sub.1, P.sub.2 and P.sub.3 indicate a period at a starting time, a period at a time on which the count number of the clock pulses e.sub.3a goes forward more than that of the clock pulses g.sub.3 and thus there is no signal which have never been read out of the latch circuits 26.sub.a1, 26.sub.a2 and 26.sub.a3 in any latch circuit, and a period at a time on which the count number of the clock pulses a.sub.3a is behind more than that of the clock pulses g.sub.3 and thus there can be at least a signal which has never been read out of the latch circuit.
The going forward means the increase of the pulse numbers per the unit time, and the being behind means the decrease of the pulse numbers per the unit time.
At the starting time in the period P.sub.1, before the flip-flop circuit 38 counts the first count number of the counter 32a, the AND gate 39 is closed so as to precede the count number of the counter 32a.
The clock pulse e.sub.3a is supplied to the queue control circuit 43.sub.1 through the AND gate opened to generate the count pulse g.sub.7. The count pulse g.sub.7 generated sets forward the count number of the counter 33a, and the corresponding AND gate 37.sub.a1 opened outputs the pulse g.sub.61 to the bus buffer 27.sub.a1. The bus buffer 27.sub.a1 opened by the pulse g.sub.61 passes the signal latched in the latch circuit 26.sub.a1 when the counter 32a counts at the first time, to the memory 3. In this case, the pulse width t.sub.1 of the count pulse g.sub.7 corresponds to the delay time in the delay circuit 40.
In the period P.sub.1, as shown in FIG. 5 in the lowermost three stairs 26.sub.a1, 26.sub.a2 and 26.sub.a3 for the three latch circuits, the latching timings which are shown by cross hatchings and include the times for clearing of the signals previously latched in their leading edges, precede the reading timings shown by hatchings, and each signal latched in the latch circuits is read out in one period T.sub.1 of the clock pulse g.sub.3. Therefore, no excess signals which are not read out is latched in the other latch circuits, and the newest signals latched are always read out quickly.
In the period P.sub.2, the reading timings precede the latching timings. For example, the clock pulse e.sub.3a No. 32 is forward more than the clock pulse g.sub.3 No. 32, and, in fact, the corresponding picture signal is not latched in any latch circuits 26.sub.a1, 26.sub.a2 and 26.sub.a3.
In such a case, when the pulse signals g.sub.51 -g.sub.53 from the AND gates 36 are not sent to the first flip-flop circuits 43.sub.a1, 43.sub.a2 and 43.sub.a3, or the first flip-flop circuits 43.sub.a1, 43.sub.a2 and 43.sub.a3 do not output any signal, the clock pulse e.sub.3a No. 32 is fed to the second flip-flop circuits 43.sub.b1, 43.sub.b2 and 43.sub.b3, but no second flip-flop circuits 43.sub.b1, 43.sub.b2 and 43.sub.b3 can output the pulse g.sub.7.
Accordingly, the counter 33a cannot count the count number, and the pulses g.sub.7, g.sub.62, g.sub.9 and gw to be obtained by the clock pulse e.sub.3a No. 32 are skipped, which is equal to the skip of the clock pulse e.sub.3a No. 32.
On the other hand, the reading pulse e.sub.R No. 32 cannot be skipped, which means that the memory 3 is substantially operated in the reading precedence. Thus, the start of the reading out of the memory 3 may be delayed a certain time corresponding to the desired signals in advance in the same manner as the embodiment shown in FIG. 3.
The writing pulse gw No. 32 is obtained by the count pulse g.sub.7 No. 32 generated by the clock pulse e.sub.3a No. 33 after the latch circuit 26.sub.a2 latches the picture signal No. 32 by the clock pulse g.sub.3 No. 32.
In the period P.sub.3, the writing timing of the clock pulse e.sub.3a is behind, and at least one picture signal which has never been read out is latched in any of the latch circuits 26.sub.a1, 26.sub.a2 and 26.sub.a3.
In the periods P.sub.1 and P.sub.2, each of the picture signals latched in the latch circuits is always read out in the one period of the clock pulse g.sub.3 and no picture signal which has never been read out is latched in the latch circuits. However, in the period P.sub.3, when the writing timings of the clock pulse e.sub.3a are consecutively behind to those of the clock pulse g.sub.3, a plurality of picture signals which have never been read out, become held in the latch circuits 26.sub.a1, 26.sub.a2 and 26.sub.a3. In such a case, the picture signals latched in the latch circuits should be read out from the one earliest latched so as to maintain the order of the signals to be sent to the memory 3.
In order to remove this defects, the pulse generator 43 comprising the three queue control circuits 43.sub.1, 43.sub.2 and 43.sub.3 is provided.
Each first flip-flop circuit 43.sub.a1, 43.sub.a2 and 43.sub.a3 of the queue control circuit 43.sub.1, 43.sub.2 or 43.sub.3 is set as soon as the corresponding latch circuit 26.sub.a1, 26.sub.a2 or 26.sub.a3 latchs the picture signal, and is reset when the picture signal latched is read out. Hence, it is possible that more than one of the flip-flop circuits 43.sub.a1, 43.sub.a2 and 43.sub.a3 may be set at the same time. This situation is maintained until the picture signal latched is read out.
For example, when the clock pulse e.sub.3a is input, the flip-flop circuits 43.sub.a3 and 43.sub.a1 are set by the clock pulses g.sub.3 Nos. 60 and 61 and the picture signals Nos. 60 and 61 are latched in the latch circuits 26.sub.a3 and 26.sub.a1. On that occasion, the counter 33a counts the count pulse g.sub.7 No. 59, and thus the count number of the counter 33a is two. By the count number two the picture signal No. 59 is read out of the latch circuit 26.sub.a2.
The clock pulse e.sub.3a erects the outputs of the second flip-flop circuits 43.sub.b3 and 43.sub.b1 of the queue control circuits 43.sub.3 and 43.sub.1 by the leading edge of the clock pulse e.sub.3a, and erects the count pulse g.sub.7 which sets forward the count number of the counter 33a to three.
The clock pulse e.sub.3a ' which passes through the AND gate 41 after the time t.sub.1 from the pulse g.sub.7, passes through the AND gate 37.sub.a3 which is opened by the count number three from the counter 33a. Then, the writing pulse gw No. 60 is sent to the terminal W of the memory 3, and the picture signal No. 60 latched in the latch circuit 26.sub.a3 is read out and is sent to the memory 3 via the bus buffer 27.sub.a3.
In this case, the writing pulse gw through the AND gate 37.sub.a3 is sent to the first flip-flop circuit 43.sub.a3 via the OR gate 45.sub.3 and the leading edge of the pulse gw resets the first flip-flop circuit 43.sub.a3, and the writing pulse gw through the OR gate 46 resets the three second flip-flop circuits 43.sub.b1, 43.sub.b2 and 43.sub.b3. The flip-flop circuit 43.sub.a1 holding the picture signal No. 61, corresponding to the latch circuit 26.sub.a1, is not reset yet.
From the above description, it is readily understood that the picture signals latched in the latch circuits 36.sub.a1 -26.sub.a3 are controlled by the queue control circuits 43.sub.1, 43.sub.2 and 43.sub.3 and the counter 33a so as to be sent to the memory 3 in order of being latched.
In FIG. 6 there is shown still another embodiment of the writing timing control circuit 20 in FIG. 3, having a speed adjusting means.
In the speed adjusting means, the total numbers D.sub.1 and D.sub.2 of the picture signals a.sub.3 and a.sub.5 which are written in the latch circuits 26.sub.1 -26.sub.n of the register 26 and are read out of the data switch citcuits 27.sub.1 -27.sub.n of the data selector 27 are compared to obtain the difference number D.sub.3 =D.sub.1 -D.sub.2 corresponding to the picture signals which have never been read out, and according to the difference number D.sub.3 the scanning speed of the original picture is controlled so that the difference number D.sub.3 may be maintained at a certain value, thereby controlling the counting speed of the counter 32 of the clock pulses g.sub.3.
A pair of counters 32b and 33b are arranged in parallel with the counters 32 and 33. Each counter 32b or 33b counts clear pulses g.sub.10 or g.sub.11 of the uppermost figure of the counted codes d.sub.1 or d.sub.2, for clearing the counter 32 or 33, to output a count code d.sub.5 or d.sub.6. The codes d.sub.1 and d.sub.2 and the code d.sub.5 and d.sub.6 are arranged in parallel to obtain total number codes corresponding to the total numbers D.sub.1 and D.sub.2. The total number codes are fed to a subtractor 48.
The total number D.sub.1 and D.sub.2 are counted by the counters 32, 32b, 33 and 33b from the time the start pulse g.sub.4 is supplied. The counters 32 and 33 are preset to n/2 and 0 by the start pulse g.sub.4 and thus the counters 32 and 33 start to count from n/2 and 0. The counters 32b and 33b are reset to zero per one scanning line in the direction of the cylinder's periphery by the start pulse g.sub.4.
The subtracter 48 subtracts the total number D.sub.2 of the signal a.sub.3 from the total number D.sub.1 of the signal a.sub.5 to obtain the difference number D.sub.3 which is sent to a first comparator 49. The first comparator 49 discriminates whether the difference number D.sub.3 is decreasing or increasing on the basis of the number n/2, and outputs a discrimination signal D.sub.4 to a motor control circuit 50 which controls the rotation speed of the motor 6 for driving the picture cylinder 4 according to the discrimination signal D.sub.4 so that the difference number D.sub.3 may always be n/2.
The first comparator 49 may include a D/A converter and outputs an analog discrimination signal D.sub.4. Alternatively, the first comparator may use a digital magnitude comparator and outputs a binary discrimination signal D.sub.4.
The difference number D.sub.3 is sent to a second comparator 51 which discriminates whether the picture signals which have never been read out are exhausted or fewer. For example, the second comparator 51 comprises a magnitude comparator which outputs a signal D.sub.5 in high level H or low level L when D.sub.3 >1 or D.sub.3 .ltoreq.1. By the output signal D.sub.5 the input circuit of the clock pulse e.sub.3a is opened or closed via an AND gate 52.
That is, when the difference number D.sub.3 is at most one (actually one), the clock pulse e.sub.3a to be fed to the counter 33 and the AND gates 37 is skipped by closing the AND gate 52, in the similar manner to the previous embodiment in the period P.sub.2. Therefore, the count number of the counter 32 goes always forward more than that of the counter 33, and the difference number D.sub.3 is not reduced less than one while the difference number D.sub.3 is always supplemented.
In this embodiment, the clock pulse e.sub.3a through the AND gate 52 is used as the writing pulse gw.
The first comparator 49 or the second comparator 51 may be omitted in the embodiment in FIG. 6. For example, when only the second comparator is used, it is sufficient to settle the preset valve of the counter 32 to a certain value which is at least one number larger than that of the counter 33. In this embodiment, the latch circuits 26.sub.1 -26.sub.n for holding the picture signals which have never been read out may be reduced and the other members may also be reduced, as compared with the embodiment in FIG. 3 wherein at the starting time the counter 32 is counted to a certain number in advance.
The motor control circuit 50 may control the motor 7 for driving the recording cylinder 5, or another relative speed variation means which adjust a slight amount of relative speeds of the picture and the recording cylinders by using the discrimination signal D.sub.4 output from the first comparator 49. Even if the relative speed control described above is carried out, it is impossible to reduce the relative speed deviation to nought, and thus the minimum number of latch circuits are required to deal with the relative speed deviation.
In the above embodiments, the explanation has been performed by using the two-phase clock pulse e.sub.3a for the original picture A, but, of course, the other two-phase clock pulse e.sub.3b may be used for the original picture B in the same manner as the clock pulse e.sub.3a.
Although the present invention has been described with reference to preferred embodiments thereof, however, various changes and modifications can be made by those skilled in the art without departing from the scope of the present invention.
Claims
What is claimed is:
1. A method for controlling writing timings of each of a plurality of picture signals to be written into and stored in a memory, said signals to be used in a picture reproducing machine wherein the picture signals picked up by picture scanning means are stored in the memory and then the picture signals are read out of the memory, and wherein reproduction pictures are recorded on a recording film by a reproduction recording means by using the picture signals read out, comprising the steps of: (a) latching a plurality of the picture signals consecutively into a plurality of data storage latch circuits pre-positioned prior to the memory by a first clock pulse generated by the picture scanning means; and (b) writing into the memory each of the scanned picture signals read out of the latch circuits in the latching order by a timing control circuit processing a signal from a second clock pulse generated by the reproduction recording means and a pulse indicating latching of the next consecutive picture signal into one of said data storage circuits.
2. A method as defined in claim 1, wherein the first and second clock pulses are synchronized with the speeds of the picture and recording cylinders, respectively, in the direction of each cylinder's rotation, first and second clock pulses are counted to determine a set of sums, and then the relative speeds of the picture and recording cylinders are controlled so that the difference between the sums is always less than a certain value.
3. A method as defined in claim 2 wherein the phases of the first and second clock pulses are compared and when the phase of the second clock pulse equals or exceeds that of the first clock pulse, the picture signal latched in the latch circuit is read out by the next second clock pulse relative to said compared, second clock pulse, and when the phase of the compared, second clock pulse is less than that of the first clock pulse, the picture signal latched in the latch circuit is read out by the second clock pulse.
4. A method as defined in claim 2, wherein depending on the difference between the count numbers of the first and second clock pulses, the speed of the picture cylinder in the direction of the cylinder's periphery is controlled so that the difference may be less than a certain value.
5. A method as defined in claim 2, wherein depending on the difference between the count numbers of the first and second clock pulses, the speed of the recording cylinder in the direction of the cylinder's periphery is controlled so that the difference may be less than a certain value.
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