Radiation Hardened MOS Voltage Generator Circuit

The invention relates to voltage generator circuits for use with digital logic or memory circuits, and in particular to voltage generator circuits which are radiation hardened by circuit design.

There are many applications in which LSI circuits are used in environments which are subject to various type of radiation. The radiation affects various device parameters so as to limit the operational range of the circuit. For example, LSI random access memory circuits are only operable up to a radiation dose equal to 5.times.10.sup.3 rads [Si] total dose, or 3.times.10.sup.9 rads/sec [Si] transient dose rate.

Various process techniques are known for achieving integrated circuit radiation hardening, and some small capacity RAMs have been specifically designed and fabricated to withstand high radiation levels. The drawback of such known radiation hardened circuits is their relatively small storage capacity (for example 64 bits) per chip, their access time and the degree of radiation hardness.

There are various known circuit techniques for providing an MOS voltage generator. These techniques include a resistance divider circuit, a source follower circuit, and an MOS divider circuit. There are disadvantages associated with each of these prior art circuits for providing an MOS voltage generator which makes such approaches unsuitable for use in a radiation environment. The resistance divider circuit, for example, has a large layout size, only fair accuracy, and relatively high power dissipation. Moreover the output voltage of the resistance divider depends on variations in resistivity, length, and width.

The source follower circuit generally permits the output voltage to equal the threshold voltage, however it operates very slowly, provides very small current when its output voltage approaches the threshold voltage, and moreover the threshold voltage is not necessarily equal to the maximum threshold voltage of the driven devices after irradiation takes place.

The MOS divider circuit has a number of problems which also makes it unsuitable for the intended application in a radiation environment. The output voltage depends upon a number of independent device parameters such as the threshold voltage V.sub.T, the drain-to-source voltage V.sub.DS, the gate-to-source voltage V.sub.GS the width/length ration W/L, the parameter K'=.mu.(.sup..epsilon. ox/.sup.T ox) (where .mu. is the charge carrier mobility, .sub..epsilon. ox the dielectric constant of the gate insulating layer and .sup.T ox the thickness of the gate insulating layer), the leakage current, the body effect factor BE=.+-.(.sup.T ox/.sup..epsilon. ox) .sqroot.2q.epsilon..sub.s N (where q is the electronic charge, .epsilon..sub.s the dielectric constant of silicon, and N the concentration of dopant atoms in the silicon substrate), resistivity and supply voltage V.sub.DD. Moreover the accuracy of such a circuit is very poor, and no fairly large scale change in th supply voltage is allowed. There is relatively high power dissipation and slow operation in the saturation region. Furthermore the output voltage does not vary with the threshold voltage variations resulting from nuclear radiation MOS processing, temperature and voltage biasing effects.

In view of the above noted disadvantages, prior to the present invention there has not been an MOS voltage generator which provides considerable immunity to ionizing radiation degradation by tracking the maximum threshold voltage shifts occurring on an MOS circuit.

Briefly, and in general terms, a voltage generator for use in radiation environments is disclosed. The voltage generator is preferably implemented as a CMOS/SOS (CMOS/silicon-on-sapphire) circuit which performs parameter tracking to adjust to a wide range of non-uniform on-chip parameter variations which might occur as a result of exposure to radiation, as well as from MOS device processing temperature and supply effects.

The presently disclosed voltage generator includes a source of relatively positive and a source of relatively negative electrical potential; first and second enhancement mode field effect transistors connected in electrical series between said source of relatively positive and said source of relatively negative potential; each having respective conduction path terminals and a control terminal; means for applying a first predetermined potential to said control electrode of said first transistor; means for applying a second predetermined potential to said control electrode of said second transistor, so that a voltage is generated on the node between the conduction path terminals of said first and said second transistors equal to the threshold voltage of said first and said second transistors; and an output connected to the node between the conduction path terminals of said first and said second transistors.

FIG. 1 is a schematic diagram of a highly simplified embodiment of the present invention;

FIG. 2 is a schematic diagram of another embodiment of the present invention incorporating source follower MOSFETs to provide suitable gate voltages to the voltage generator MOSFETs; and

FIG. 3 is a schematic diagram of yet another embodiment of the present invention including not only a source follower MOSFET circuit, but additional MOSFETs for shifting the threshold voltages of the source follower MOSFETs by biasing certain MOSFETs for worst case during the time of irradiation.

In the several Figures of the drawing, like reference numerals represent like components.

FIG. 1 is a schematic diagram of a highly simplified embodiment of the present invention. FIG. 1 shows a first metal oxide semiconductor field effect transistor (MOSFET) Q.sub.1 having its conduction path connected in series between a first source of potential V.sub.DD and a second MOSFET Q.sub.2. Although MOSFETs are shown in this application, it must be realized that other types of transistor devices having a predetermined threshold voltage which can vary as a function of process temperature, voltage bias, and radiation effects are possible. In the preferred embodiments considered here, both Q.sub.1 and Q.sub.2 are enhancement mode p-channel MOSFETs with substantially equal V.sub.T threshold voltages, but the invention is not limited to PMOS technology, since NMOS or another technology could be used, and devices other than MOSFETs could be used as well. FIG. 1 also shows a first input labelled V.sub.IN1 having a potential equal to two times the threshold potential, i.e. 2V.sub.t. The gate-to-source voltage, V.sub.GS, of MOSFET Q.sub.1 is then equal to 2V.sub.T. A second input, labelled V.sub.IN2, is provided with a predetermined potential equal to 3V.sub.T. The gate-to-source voltage of MOSFET Q.sub.2 is then also equal to 2V.sub.T. The other conduction path terminal of MOSFET Q.sub.2 is connected to a second potential source, so that the first and second FETs are connected in electrical series between a source of relatively positive (V.sub.DD) and a source of relatively negative (V.sub.SS) potential. In the configuration shown in FIG. 1, the potential at the second terminal of MOSFET Q.sub.2 would be equal to V.sub.DD -2V.sub.T where V.sub.DD is the relatively positive potential of the voltage source. The output of the circuit in FIG. 1, labeled V.sub.OUT, is connected to the node between the conduction path terminals of the first and the second MOSFETs. If MOSFETs Q.sub.1 and Q.sub.2 are identically sized, and the indicated potentials are applied to their respective gates, the voltage output V.sub.OUT would be equal to V.sub.T.

Although FIG. 1 depicts a highly simplified implementation of the present invention, it demonstrates the key elements of the present invention, namely means for applying a first predetermined potential to the control electrode of the first transistor, and means for applying a second predetermined potential to the control electrode of the second transistor so that a voltage is generated on the node between the conduction path terminals of the first and second transistors which is equal to the threshold voltage of such transistors. More specifically, such a voltage is specified by requiring that the gate-to-source voltage of MOSFET Q.sub.1 be equal to 2V.sub.T, and the gate-to-source voltage of MOSFET Q.sub.2 be equal to 2V.sub.T.

The first MOSFET Q.sub.1 substantially operates in the triode region, i.e. in the region such that

where I.sub.Q.sbsb.1 is the current through the conduction path of MOSFET Q.sub.1 ; .beta. a gain factor; V.sub.GS the gate-to-source voltage; V.sub.T the threshold voltage of both Q.sub.1 and Q.sub.2 devices; and V.sub.DS the drain-to-source voltage.

The second MOSFET Q.sub.2 substantially operates in the neighborhood of the saturation point: ##EQU1##

FIG. 2 is a schematic diagram of another embodiment of the present invention which incorporates source followers MOSFETs which provide suitable gate voltages to the voltage generator MOSFETs Q.sub.1 and Q.sub.2. Turning now more specifically to the circuit shown in FIG. 2, the source follower MOSFETs are p-channel MOSFETs Q.sub.3, Q.sub.4, and Q.sub.5, having their conduction path connected in series. The threshold voltages of Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4, and Q.sub.5 are also substantially equal to V.sub.T. One conduction path terminal of MOSFET Q.sub.3 is connected to the source of relatively positive potential, V.sub.DD. The control terminal of MOSFET Q.sub.3 is connected to the other conduction path terminal of MOSFET Q.sub.3. One conduction path terminal of MOSFET Q.sub.4 is in turn connected to the node formed by the control terminal and the conduction path terminal of MOSFET Q.sub.3, while the other conduction path terminal of MOSFET Q.sub.4 is connected to the control terminal of MOSFET Q.sub.4. One conduction path terminal of MOSFET Q.sub.5 is connected to the control terminal of MOSFET Q.sub.4 and the conduction path terminal of Q.sub.4, while the other conduction path terminal of MOSFET Q.sub.5 is connected to its control terminal. The control terminal of MOSFET Q.sub.4 is connected to the control terminal of MOSFET Q.sub.1. The control terminal of MOSFET Q.sub.5 is connected to the control terminal of MOSFET Q.sub.2. MOSFETs Q.sub.3, Q.sub.4 and Q.sub.5 form a basic source follower circuit which provides potentials of suitable magnitude to the control electrodes of MOSFETs Q.sub.1 and Q.sub.2 respectively.

The circuit of FIG. 2 also includes MOSFETs Q.sub.6, Q.sub.7 and Q.sub.8 which perform control functions. MOSFETs Q.sub.6 and Q.sub.7 are p-channel MOSFETs, while MOSFET Q.sub.8 is an n-channel MOSFET. The MOSFETs Q.sub.7 and Q.sub.8 are therefore complimentary MOS transistors, and are preferably implemented using CMOS/SOS technology. MOSFET Q.sub.6 has its first conduction path terminal connected to the first source of relatively positive potential V.sub.DD, and its second conduction path terminal connected to the control terminal of MOSFET Q.sub.4, and thus also to the control terminal of MOSFET Q.sub.1. The control terminal of MOSFET Q.sub.6 is connected to a control input line which is labeled here .phi..sub.IN. This .phi..sub.IN line provides means for determining a normal mode and a stand-by mode of operation. When clock .phi..sub.IN is high, the mode is said to be normal. When .phi..sub.IN is low, the mode is said to be stand-by. The significance of the normal and the stand-by mode will be made more specific with reference to FIG. 3 and will be discussed later.

Returning now to the description of FIG. 2, MOSFETs Q.sub.7 and Q.sub.8 have their conduction path terminals connected in series between a first relatively positive source of voltage V.sub.DD and a second relatively negative source of voltage V.sub.SS. MOSFET Q.sub.7 as we have pointed out above is a p-channel MOSFET, while MOSFET Q.sub.8 is an n-channel MOSFET. The node between the MOSFETs Q.sub.7 and Q.sub.8 is connected to the control terminal of MOSFET Q.sub.5. The control terminals of MOSFETs Q.sub.7 and Q.sub.8 are connected together and to the .phi..sub.1 input line.

Having discussed the structure of the circuits shown in FIG. 2, we can now turn to its operation.

In active mode when .phi..sub.IN is high a potential equal to V.sub.DD is applied to the control terminals MOSFETs Q.sub.6, Q.sub.7, and Q.sub.8. Since Q.sub.6 and Q.sub.7 are p-channel MOSFETs, they are turned off by the high clock signal. Q.sub.8 however is an n-channel MOSFET and Q.sub.8 is turned on by the high .phi..sub.IN signal. Therefore, when the clock .phi..sub.1 is high, there is a series connection of MOSFETs Q.sub.3, Q.sub.4, Q.sub.5, and Q.sub.8 between V.sub.DD and V.sub.SS. The current of Q.sub.8 decreases the voltage on points A and B until a potential of V.sub.DD minus 2V.sub.T is reached on point A, and a potential of V.sub.DD minus 3V.sub.T is reached on point B. The output on V.sub.OUT would therefore be equal to the V.sub.T for the reason discussed from FIG. 1.

In standby mode when .phi..sub.IN is low, MOSFETs Q.sub.6 and Q.sub.7 are turned on, and MOSFET Q.sub.8 is turned off. MOSFETs Q.sub.6 and Q.sub.7 then shunt Q.sub.3, Q.sub.4, and Q.sub.5 and apply the potential of V.sub.DD to MOSFETs Q.sub.1 and Q.sub.2. Since MOSFETs Q.sub.1 and Q.sub.2 are p-channel MOSFETs, they are turned off. Although the output voltage of the circuit shown in FIG. 2 varies with processing, temperature and biasing effects on the threshold voltages of the p-channel devices, the operation is still not sufficient for providing a satisfactory voltage generator circuit particularly when the "worst case" threshold voltage shifting occurs by irradiation. The threshold voltage varies as a function of the total ionizing dose. At a total ionizing dose rate beyond 5.times.10.sub.3 rads [Si], there is considerable variation in the potential variation of the threshold voltage depending upon the voltage bias. For example, at 1.times.10.sup.6 rads [Si] for a p-channel MOSFET, a voltage bias V.sub. GS equal to minus 10 volts would result in a threshold voltage shift from approximately minus 1 volt to minus 2 volts. However, for the same p-channel MOSFET with a voltage bias V.sub.GS equal to +10 volts the threshold voltage will shift from minus one volt to minus five volts. This "worst case" shifting occurs at V.sub.GS equal to +V.sub.DD and V.sub.DS equal to 0 on p-channel MOS devices.

FIG. 3 is a schematic diagram of yet another embodiment of the MOS voltage generator circuit according to the present invention which includes not only a source follower circuit but additional devices for shifting the threshold voltages of the source following by biasing certain MOSFETs for "worst case" during the time of irradiation. Turning now to the specific details of the circuit in FIG. 3, we again point out that components with the same reference numerals as those in FIG. 2 and FIG. 1 represent corresponding components in FIG. 3. Thus, MOSFETs Q.sub.1 and Q.sub.2 are in series connection between a first source of relatively positive potential and a second source of relatively negative potential V.sub.SS. It is noted that the source of relatively positive potential in FIG. 2 has been substituted in FIG. 3 by the clock input .phi..sub.1. On FIG. 3 clock .phi..sub.1 is the complementary (inverted) signal of clock .phi..sub.1. Clock .phi..sub.2 is a delayed repetition of clock .phi..sub.1. The timing difference between .phi..sub.2 and .phi..sub.1 is necessary to assure proper potentials on nodes 15, 13 and 12 for true source follower operation of devices Q.sub.3, Q.sub.4 and Q.sub.5 at switching to normal mode. When the clock input .phi..sub.1 is high and .phi..sub.2 is low, the circuit is said to be operating in the normal mode. When .phi..sub.1 is low and .phi..sub.2 is high, the circuit is said to be in stand-by mode. MOSFETs Q.sub.3, Q.sub.4 and Q.sub.5 form the source follower circuit in FIG. 3 as represented by corresponding MOSFETs Q.sub.3, Q.sub.4, and Q.sub.5 in FIG. 2. It is noted that the conduction path terminal of MOSFET Q.sub.3 is connected to the clock input .phi..sub.1 in FIG. 3. Thus the conduction path terminal of MOSFET Q.sub.3 is selectively connectable to the source of relatively positive potential V.sub.DD when the clock signal .phi..sub.1 is high. The other conduction path terminal of MOSFET Q.sub.3 is connected to node 12, and in turn to a first conduction path terminal of MOSFET Q.sub.4 like the circuit in FIG. 2. The other conduction path terminal of MOSFET Q.sub.4 is in turn connected to node 13, and in turn to a first conduction path terminal of MOSFET Q.sub.5. The other conduction path terminal of MOSFET Q.sub.5 is connected to a node 15. There is further provided a MOSFET Q.sub.11 having a first conduction path terminal connected to a source of relative positive potential V.sub.DD, and a second conduction path terminal connected to a first conduction path terminal of another MOSFET Q.sub.12 at a common electrical junction 10. MOSFET Q.sub.11 is a p-channel MOSFET while MOSFET Q.sub.12 is an n-channel MOSFET. The second conduction path terminal of MOSFET Q.sub.12 is connected to the second conduction path terminal of MOSFET Q.sub.3. The control terminal of MOSFET Q.sub.3 is also connected to the common electrical junction 10.

Another p-channel MOSFET Q.sub.6 is provided having a first conduction path electrode connected to the source of relatively positive potential V.sub.DD, and a second connection conduction path electrode connected to a common electrical junction 11. An n-channel MOSFET Q.sub.13 is provided having a first conduction path electrode connected to the common electrode electrical junction 11 and a second conduction path electrode connected to the common electrical junction 13. The control electrode of MOSFET Q.sub.4 is also connected to common electrical junction 11. A p-channel MOSFET Q.sub.14 is provided in parallel with MOSFET Q.sub.13 between common electrical junctions 11 and 13. The control electrode of MOSFET Q.sub.13 is connected to the control electrode of MOSFET Q.sub.12 as well as to the common electrical junction 16 which is connected to the control electrodes of Q.sub.11 and Q.sub.6. The common electrical junction Q.sub.16 is further connected to the .phi..sub.1 input.

Another p-channel MOSFET Q.sub.7 is provided having a first conduction path electrode connected to V.sub.DD and second conduction path electrode connected to the common electrical junction 14. In series with the conduction path of MOSFET Q.sub.7 is MOSFET Q.sub.9. MOSFET Q.sub.9 is an n-channel MOSFET having its first conduction path electrode connected to common electrical junction 14 and a second conduction path electrode connected to common electrical junction 15. MOSFET Q.sub.10 is a p-channel MOSFET in parallel with MOSFET Q.sub.9, and has its first conduction path electrode connected to node 14 and second connected to node 15. The control electrode of MOSFET Q.sub.5 is connected to the common electrical junction 14. The control electrode of MOSFET Q.sub.9 is connected to the control electrode of Q.sub.7 and in turn to the .phi..sub.1. The control electrode of MOSFET Q.sub.12 is connected to the clock input .phi..sub.1, and the control electrode of MOSFET Q.sub.13 is likewise connected to the clock input .phi..sub.1.

MOSFETs Q.sub.15, Q.sub.16 and Q.sub.17 are n-channel MOSFETs which are further provided and connected between the source follower MOSFETs and the second source of electrical potential V.sub.SS. The first MOSFET Q.sub.15 has its conduction path connected between the node 12 and V.sub.SS. MOSFET Q.sub.16 has its conduction path connected between the node 13 and V.sub.SS. MOSFET Q.sub.17 has its conduction path connected between the node 15 and V.sub.SS. The control electrodes of MOSFETs Q.sub.15, Q.sub.16, and Q.sub.17 are connected to a second clock input .phi..sub.2. The clock input .phi..sub.2 activates the stand-by mode of the circuit. There is further provided a resistor R connected between the node 15 and V.sub.SS.

There is further provided an n-channel MOSFET Q.sub.18 having its conduction path connected in parallel with MOSFET Q.sub.2. The control electrode of MOSFET Q.sub.18 is connected to .phi..sub.1. The operation of the circuit shown in FIG. 3 can now be briefly described.

In normal mode when clock .phi..sub.1 is high and clock .phi..sub.2 is low, the drains of devices Q.sub.3, Q.sub.4 and Q.sub.5 are individually connected by low resistance with their own gates by means of MOSFETs Q.sub.12, Q.sub.13 and Q.sub.14, and Q.sub.9 and Q.sub.10, respectively. This is true since .phi..sub.1 is high Q.sub.12, Q.sub.13 and Q.sub.9 are on and since .phi..sub.1 is low, Q.sub.14 and Q.sub.10 are also on. The gate of p-channel devices Q.sub.3, Q.sub.4 and Q.sub.5 are separated from V.sub.DD since Q.sub.6, Q.sub.7 and Q.sub.11 are turned off by the high logical level of clock .phi..sub.1. The n-channel device Q.sub.18 is turned off by the low logical level of clock .phi..sub.1. The other n-channel devices Q.sub.15, Q.sub.16 and Q.sub.17 are also turned off separating nodes 12, 13 and 15 from V.sub.SS. The proper value of resistance R assists to maintain the 3V.sub.T, 2V.sub.T and V.sub.T voltage values on nodes 15, 13 and 12 respectively. In this configuration a voltage of 2V.sub.T is generated at node 11 which is applied to the A input of MOSFET Q.sub.1, and another potential of 3V.sub.T is generated at node 14 which is applied to B input of MOSFET Q.sub.2. This way the output voltage related to V.sub.DD is V.sub.T in a manner similar to that of FIG. 1 and FIG. 2.

In the stand-by mode clock .phi..sub.1 is low and clock .phi..sub.2 is high. Therefore MOSFETs Q.sub.1 -Q.sub.5 are all biased so that their drains and sources are at ground potential V.sub.SS. Moreover their gates are tied to the positive supply V.sub.DD. This is true since MOSFETs Q.sub.6, Q.sub.7 and Q.sub.11 are all on, since they are all p-channel MOSFETs and a low clock signal is applied to their gates from the .phi..sub.1 input. MOSFETs Q.sub.15, Q.sub.16 and Q.sub.17 are also all on since they are n-channel MOSFETs and have their gate connected to the .phi..sub.2 input, which is high. MOSFETs Q.sub.12, Q.sub.13 and Q.sub.9 are all off because .phi..sub.1 is low, devices Q.sub.10 and Q.sub.14 are also off since .phi..sub.1 is high and therefore there is no conductance between the individual gate and drain of devices Q.sub.3, Q.sub.4 and Q.sub.5. The output node is also on potential V.sub.SS since .phi..sub.1 is high, which turns n-channel device Q.sub.18 on. Thus a potential of V.sub.DD is applied to gates A and B of MOSFETs Q.sub.1 and Q.sub.2. The largest radiation induced deviation in threshold voltages for p-channel devices appears when the p-channel MOS device is biased in the manner such that the drain and source are at V.sub.SS and the gate is at V.sub.DD ; the radiation "worst case" is then provided for the critical devices Q.sub.1 through Q.sub.5. Thus an output voltage V.sub.OUT equal to V.sub.SS is developed at such time.

The present invention therefore achieves parameter tracking both in the normal and the "worst case" bias situations, and permits a wide range of non-uniform on-chip parameter variations which might occur as a result of exposure to radiation, or as a result of MOS processing, or variations in temperature or bias voltage. Moreover, operational range of MOS/LSI circuits is extended to extreme temperature and supply voltages by shifting operating points, precharge voltages, zero- and one- margins along with the shifts in threshold voltage.

Another important consequence of the voltage generator circuit is that the production yield of MOS/LSI circuits can be increased adjusting precharge voltages, operating points and margins in accordance with the actual threshold voltage values provided by the MOS processes.

The circuit density is also greater by permitting the use of minimum size load devices which function to apply gate bias slightly greater than the threshold voltage of the MOS load devices.

It will be apparent that while a preferred embodiment of the radiation hardened voltage generator according to the present invention has been shown and described, various modifications and changes may be made without departing from the true spirit and scope of the invention. The invention may be implemented using n-channel MOSFETs instead of p-channel MOSFETS for MOSFETs Q.sub.1 and Q.sub.2 respectively. Such a modification may be made if it is desired to have a voltage generator which is to drive n-channel transistor devices in a circuit. Such n-channel circuits self-evidently have different voltage bias conditions for "worst case" change in threshold voltage by radiation. Moreover, a particular source follower circuit is described as being implemented in the present invention, although it is readily apparent to those skilled in the art that alternative circuits may be used to provide appropriate gate bias to MOSFETs Q.sub.1 and Q.sub.2 for normal and Q.sub.1, Q.sub.2 as well as for Q.sub.3, Q.sub.4, Q.sub.5 for "radiation hardness" situations.