Temperature Compensated Constant Current MOS Field Effective Transistor Circuit

This invention relates to a MOS field effect transistor circuit exhibiting constant current property irrespective of temperature change.

As large scale integrated circuits (LSI) have been increased in size and popularity, there have been increasing demands for incorporation of an analog-value detecting circuit for detecting a predetermined analog signal level a digital LSI. This analog-value detecting circuit may be used for notifying the user of e.g. wrong operation of the LSI due to fluctuation of a source voltage or heat generation of the LSI exceeding an allowable range. While this type of analog-value detecting circuit may operated as an analog circuit in a digital LSI, the analog circuit composed of circuit elements designed for digital LSI is not generally understood to facilitate analog operation with desired accuracy. Especially in LSI's employing MOS FET's, the operating temperature range is wide, and the current characteristic thereof will be substantially changed according to temperature change within such range. For example, though the circuit constant of an analog circuit may be so set as to enable it to detect current or voltage at a predetermined level, the analog circuit will detect a current or voltage at a level varied with temperature change. Thus, it has conventionally been deemed to be difficult to contruct by using MOS FET's a compact analog-value detecting circuit capable of detecting current or voltage at a predetermined level independently of temperature change within the aforesaid operating temperature range and to incorporate a detecting circuit of large size into a chip of LSI.

An object of this invention is to provide a MOS field effect transistor circuit exhibiting constant current property irrespective of temperature change.

According to an embodiment of the invention, there may be obtained a MOS field effect transistor circuit comprising a power terminal, a MOS field effect transistor, and a unidirectional circuit element coupled in the forward direction between the gate of the MOS field effect transistor and the power terminal.

FIGS. 1 and 2 are circuit diagrams of a diode and MOS FET for illustrating the principle of this invention;

FIG. 3 is a sectional view of the semiconductor device corresponding to the circuit as shown in FIG. 1;

FIG. 4 is a graph showing the forward current characteristic of the diode;

FIG. 5 is a graph showing the relationship between the forward voltage of the diode and the temperature;

FIG. 6 is a graph showing the relationship between the threshold of the MOS FET and the temperature; and

FIG. 7 is a circuit diagram illustrating the MOS field effect transistor circuit according to an embodiment of the invention.

FIGS. 1 and 2 show the principle of the MOS FET circuit with constant-current property according to the invention. The circuit as shown in FIG. 1 has an N-channel type MOS FET 1 and a unidirectional circuit element or diode 2 coupled in the forward direction between the gate of the MOS FET 1 and a negative power terminal 3. The electric potential of the substrate of the MOS FET 1 is set at substantially the same or lower level as that of the negative power terminal 3. Meanwhile, the circuit as shown in FIG. 2 has a P-channel type MOS FET 4 and a diode 5 coupled in the forward direction between the gate of the MOS FET 4 and a positive power terminal 6. The potential of the substrate of the MOS FET 4 is set at substantially the same or higher level as that of the positive power terminal 6.

The circuit of FIG. 1, for example, may be so constructed as shown in FIG. 3. Referring now to FIG. 3, P-wells 8 and 9 are formed in the surface region of an N-conductivity type substrate 7. An N.sup.+ -type region 10 is formed in the P-well 8, while N.sup.+ -type regions 11 and 12 are formed in the P-well 9. Further, in the surface region of the substrate 7 is formed a P.sup.+ -type region 13 partly overlying the P-well 8. The P-type region 8 and the N.sup.+ -type region 10 form the diode 2, while the P-type region 9 and the N.sup.+ -type regions 11 and 12 form the MOS FET 1. A metallic electrode 14 corresponds to the negative power terminal 3, and a metallic electrode 15 is coupled to the P-type region 8 through the P.sup.+ -type region 13 at one end and to a gate electrode 16 at the other end.

As is clearly understood from FIG. 4 illustrating the forward-current property of the diode, a forward voltage higher than a predetermined forward voltage drop V.sub.F is required to obtain a forward current flow through such diode. In the circuit as shown in FIG. 1, for example, at the terminal of the diode 2 connected to the MOS FET 1 will appear a voltage higher than the voltage applied to the negative power terminal 3 by a level of the forward voltage drop V.sub.F. Such forward voltage drop V.sub.F can be set by the impurity concentration of the P-type region 8 and N.sup.+ -type region 10 in FIG. 3, and the ambient temperature. As shown in FIG. 5, the forward voltage drop V.sub.F and the temperature are in such relation that the former is reduced linearly as the latter increases. Further, as shown in FIG. 6, the relation between the threshold voltage V.sub.TH of the MOS FET and the temperature is such that former is reduced linearly as the latter increases. Accordingly, if the diode is connected in the forward direction between the power terminal and the gate of the MOS FET, the variation in the forward voltage drop of the diode owing to the temperature change will be compensated by the variation of the threshold voltage V.sub.TH in the MOS FET, thus allowing the MOS FET to lead a substantially constant current independently of the temperature change. That is, the difference (V.sub.G -V.sub.TH) between the threshold voltage V.sub.TH of the MOS FET and a gate voltage V.sub.G applied to the gate of the MOS FET through the diode in the forward direction is kept constant irrespective of the temperature change, thereby causing a constant current to flow between the drain and source of the MOS FET.

Since the forward voltage drop of the diode is small, the MOS field effect transistor circuit with preferable current property may be constructed by using a MOS FET with a low threshold voltage.

FIG. 7 illustrates a preset-voltage detecting circuit constructed by using the circuit as shown in FIG. 1. This detecting circuit is provided with an N-channel type MOS FET 21 and a diode 22 coupled between the gate of the MOS FET 21 and a negative power source -V.sub.DD. The drain of the MOS FET 21 is coupled to an output terminal 23 and grounded through a P-channel type MOS FET 24, while the source is coupled to the substrate of the MOS FET 21 and to the negative power source -V.sub.DD. The anode of the diode 22 is grounded through a P-channel MOS FET 25 used as a high-resistance element. Between the negative power source -V.sub.DD and ground is coupled a series circuit including a variable resistance 26 and a P-channel type MOS FET 27. The source of the MOS FET 27 is coupled to the substrate, the drain is coupled to the gate of the MOS FET 24, and the gate is coupled to the negative power source -V.sub.DD.

In this detecting circuit, a voltage divided by the variable resistance 26 and the MOS FET 27 is applied to the gate of the MOS FET 24, allowing the MOS FET 24 to be rendered conductive in an ordinary condition and keeping the output terminal 23 substantially at the ground potential. However, if the absolute value of the negative power source -V.sub.DD is reduced to a preset voltage level, the MOS FET 24 will be rendered nonconductive to make the potential at the output terminal 23 substantially equal to the negative power source V.sub.DD, thereby securing properly the preset voltage. In this case, if the threshold voltage of the MOS FET 21 is varied, then the current flowing through the current path of such MOS FET will be substantially changed to prevent satisfactory detection of the preset voltage level. In this detecting circuit, however, the diode 22 is coupled in the forward direction between the negative power source -V.sub.DD and the gate of the MOS FET 21, so that a substantially constant current is introduced into the current path of the MOS FET 21 as described with reference to FIG. 1, thus securing highly reliable operation of the preset-voltage detecting circuit.

Although an illustrative embodiment of this invention has been described in detail herein, it is to be understood that the invention is not limited to this precise embodiment. For instance, as shown in FIG. 3, there is employed an enhancement-type MOS FET as the MOS FET 1 shown in FIG. 1, while it is of course possible to use a depletion-type MOS FET. Furthermore, though FIG. 7 shows the voltage detecting circuit including the N-channel type MOS FET 21 to which the circuit of FIG. 1 is employed, an equivalent voltage detecting circuit may also be constructed by using a P-channel type MOS FET, employing the circuit as shown in FIG. 2.