Semiconductor Circuit for Voltage Conversion

This invention relates to the field of semiconductor apparatus and more particularly to MOS (metal-oxide-semiconductor) circuits for voltage conversion.

In many practical applications involving electrical circuits in MOS technology, such as MOS memory and logic circuits, it is desired to have an on-chip MOS circuit for multiplying or "boosting" an applied external voltage. In prior art, such voltage multiplier circuits have taken such forms as "Jacobs ladders" (see, for example, John Markus, Electronic Circuits Manual, p. 139: "DC Voltage Converter"), as well as circuits in which capacitors are alternately connected in parallel and series, an external voltage being applied to each capacitor during the parallel connection phase (see, for example, L. M. Braslavskii et al., "Means of Transformerless Voltage Conversion and Construction of Transformerless Secondary Power Sources", Instruments and Experimental Techniques, Vol. 20. No. 4, pp. 1132-1140, at pp. 1138-1139). However, these prior art techniques suffer from undesirable threshold voltage drops across the various MOS diodes used in these circuits, thereby undesirably reducing the amount of voltage multiplication or, conversely, undesirably increasing the required number of capacitors and hence the required semiconductor chip area for a given desired voltage output, as well as causing undesirable power loss. It would therefore be desirable to have a voltage multiplier circuit in MOS technology which alleviates this problem.

In accordance with the invention, a stage (FIG. 1) of a voltage converter circuit includes a capacitor (C.sub.1) having a pair of terminals each of which is connected through the source drain path of a separate MOS transistor switch (M.sub.3, M.sub.5) to a separate first and second voltage source terminal (ground, V.sub.1) for alternately connecting and disconnecting said capacitor (C.sub.1) to said first and second voltage source terminals (ground, V.sub.1), one terminal of a capacitor (C.sub.1) being also connected through the source-drain path of series-connected MOS transistor (M.sub.1) to a second voltage source terminal (V.sub.2), the gate electrode of said series-connected transistor (M.sub.1) being connected to another MOS transistor switch (M.sub.4) for alternately turning "on" and "off" said series-connected transistor (M.sub.1), CHARACTERIZED IN THAT said circuit further includes a feedback loop running from the other terminal of said capacitor C.sub.1 through a load (M.sub.2) back to the gate electrode of said series connected MOS transistor (M.sub.1). This load (M.sub.2) advantageously is formed by the source-drain path of an MOS transistor whose gate electrode is connected through the source-drain path of MOS transistor switch (M.sub.6) to a voltage source terminal and to one terminal of a second, smaller capacitor (C.sub.2) having another terminal which is connected to the gate electrode of the series-connected transistor (M.sub.1). Since it is the capacitor C.sub.1 which consumes most of the semiconductor wafer area, the extra area consumed by the added elements of this invention is more than compensated by the higher output voltage, especially in multistage embodiments (FIG. 3) of this invention.

This invention, together with its objects, features and advantages may be better understood from the following detailed description when read in conjunction with the drawings in which:

FIG. 1 is a schematic circuit diagram of a voltage converter circuit stage in MOS technology, in accordance with a specific embodiment of the invention;

FIG. 2 is a schematic circuit diagram of a voltage converter circuit stage in MOS technology, in accordance with another specific embodiment of the invention; and

FIG. 3 is a schematic circuit diagram of a voltage multiplier in MOS technology in accordance with yet another specific embodiment of the invention.

A voltage converter circuit stage 10 in MOS technology is arranged (FIG. 1) as follows:

An input terminal 11 is connected to an output terminal 13 through the drain-source path of a first series connected MOS transistor M.sub.1 connected in series with a first relatively large MOS capacitor C.sub.1. A feedback loop comprises the drain-source path of a second, feedback MOS transistor M.sub.2 which is connected between the output terminal 13 and the gate electrode of the first MOS transistor M.sub.1. The gate electrode terminal 15 of the second MOS transistor M.sub.2 is connected to its source terminal 14 through a relatively small feedback capacitor C.sub.2. Auxiliary MOS switching transistors, M.sub.3, M.sub.4, M.sub.5, and M.sub.6 are controlled by periodic clock pulse input sequence .phi. (for M.sub.3 and M.sub.4) and .PHI. (for M.sub.5 and M.sub.6). These sequences .phi. and .PHI. are identical except for voltage levels as are suitable for periodically turning "on" and "off" simultaneously all of these auxiliary switching transistors M.sub.3, M.sub.4, M.sub.5, and M.sub.6. All of the transistors M.sub.1 -M.sub.6 are typically of the enhancement mode N-MOS type. In this way, these auxiliary switching transistors periodically alternately connect and disconnect both capacitors (C.sub.1, C.sub.2) to a charging voltage V.sub.1 relative to ground, typically about +5 volts (N-MOS) relative to ground. As a result only when these capacitors are disconnected from the charging voltage V.sub.1, the series connected transistor M.sub.1 is "on" due to feedback voltage to its gate electrode supplied through the feedback transistor M.sub.2, thereby applying an input voltage V.sub.2 to one terminal (12) of the first capacitor C.sub.1 and thereby raising the potential of the output terminal 13 to the input voltage plus the charging voltage (V.sub.2 +V.sub.1). In N-MOS technology, V.sub.2 is positive.

The output potential (V.sub.2 +V.sub.1) can be used as the input voltage (instead of V.sub.2) to a similarly constructed second voltage converter circuit stage, whereby the output of this second stage will be (V.sub.2 +2V.sub.1), and so forth for as many stages as desired. As further indicated in FIG. 2, the entire circuit 20 can be integrated in single semiconductor substrate biased at a voltage V.sub.3 of typically -5 volts (back-gate bias).

During operation, the clock phase sequence .phi. alternately turns "on" and "off" the auxiliary MOS transistors M.sub.3, M.sub.4, M.sub.5 and M.sub.6. Thereby, the terminals 12 and 14 are alternately connected to and disconnected from ground potential, respectively, whereas the terminals 13 and 15 can thereby connected to and disconnected from a charging voltage V.sub.1, typically about +5 volts in N-MOS technology (the semiconductor substrate bias being about -5 volts). During the "charging" phase when .phi. turns "on" the transistors M.sub.3, M.sub.4, M.sub.5, and M.sub.6, the series transistor M.sub.1 is thus "off", since its gate electrode and drain terminal 12 are then both connected to ground, the voltage V.sub.2 at the terminal 11 never being negative.

Accordingly, during the charging phase, the capacitor C.sub.1 is disconnected from the input terminal 11. Advantageously, each of the capacitors C.sub.1 and C.sub.2 is formed by an MOS transistor whose source is permanently connected to its drain and whose gate electrode is connected to V.sub.1 during the charging phase. Also, during this charging phase, the potential on both the gate electrode and drain of the feedback transistor M.sub.2 is equal to V.sub.1 while the potential on the source of this same transistor is at ground; therefore, the transistor M.sub.2 is then "on" and supports a voltage of V.sub.1 across its source-drain (channel) path. Accordingly, both the capacitors C.sub.1 and C.sub.2 are charged to a voltage of V.sub.1 during the charging phase.

Just before the end of the charging phase, the auxiliary transistors M.sub.3, M.sub.4, M.sub.5, and M.sub.6 are all turned "off", thereby disconnecting the terminals 12 and 14 from ground and the terminals 13 and 15 from V.sub.1. At this moment of time, moreover, the positive charge on the gate electrode of the feedback capacitor C.sub.2 is still sufficient to keep the now floating terminal 15 at potential V.sub.1 while the positive charge on the gate electrode of the large capacitor C.sub.1 is still sufficient to keep the now floating terminal 13 at potential V.sub.1 ; therefore, the feedback transistor M.sub.2 remains in its "on" condition with terminal 14 at ground potential. As a result, positive charge flows through M.sub.2 to terminal 14, thereby raising the potential of this latter terminal 14. Accordingly, after a short interval of time has thus elapsed just after the end of the charging phase, the potential of terminal 14 rises to the threshold voltage of the series connected transistor M.sub.1 ; thereby, M.sub.1 turns "on" , since V.sub.2 is positive (in N-MOS technology) and the potential at terminal 12 is then at ground. Thus, the result is that the potential of terminal 12 rises to V.sub.2.

On the other hand, the voltage drop across C.sub.1 remains essentially at V.sub.1, since C.sub.1 is so much larger than the parasitic capacitance of terminal 14 to ground, and hence only a negligible amount of charge flows from the gate electrode of C.sub.1 through M.sub.2 to this terminal 14; therefore, the potential of output terminal 13 rises practically all the way to (V.sub.1 +V.sub.2), as does the potential of terminal 14; whereas the potential of terminal 15 rises to (V.sub.1 +V.sub.2)+V.sub.1 =(V.sub.2 +2V.sub.1). Accordingly, M.sub.2 remains "on", as does M.sub.1 (since the thresholds of both of these are less than V.sub.1) until the commencement of the very next "charging" phase when M.sub.3, M.sub.4, M.sub.5, and M.sub.6 turn "on" again. It is the rise in potential of output terminal 13 to (V.sub.1 +V.sub.2) which is characteristic of a "voltage adder" or one stage of a "voltage multiplier" , both of which are forms of voltage converters.

It is obvious from the above description of operation that the feedback transistor M.sub.2 could take the form of a load device of suitable impedance, thereby dispensing with the capacitor C.sub.2 and its auxiliary transistor M.sub.6. Such a load device could be simple resistor, or an MOS depletion mode transistor whose drain is permanently connected to its gate electrode.

FIG. 2 illustrates a first circuit stage 20 of a voltage multiplier MOS circuit, in accordance with another specific embodiment of the invention. Elements which are common to the circuit of FIGS. 1 and 2 have been given the same reference numerals. Basically, the circuit stage 20 of FIG. 2 is the same as the previously described stage 10 of FIG. 1 except that the control circuitry for providing the clock input sequences .phi. and .PHI. is shown in greater detail in FIG. 2.

In the circuit 20, the values of V.sub.1 and V.sub.2 are both taken to be equal to +5 volts (N-MOS technology) for convenience and simplicity. The semiconductor substrate voltage bias is typically -5 volts (back-gate bias); however, any substrate bias having between -5 volts and ground could be used. The clock input sequence .phi. as indicated in FIG. 2, is applied to a clock input terminal 21 in the form of a 5 volt pulse sequence, with typical rise and fall times of 50 nanoseconds, and pulse durations of 200 nanoseconds, thereby providing a clock period of 500 nanoseconds, that is, a 2 megahertz frequency clock. The clock input at terminal 17 is thus +5 volts during every "charging" phase when the auxiliary switching transistors are "on", and is 0 volt (ground) when these transistors are "off".

An MOS capacitor C.sub.3 together with a pair of control MOS transistors M.sub.7 and M.sub.8 have been added in the circuit 20 (in comparison with the circuit 10) for the purpose of ensuring voltage levels for the sequence .PHI. appropriate for alternately turning "on" and "off" the transistors M.sub.5 and M.sub.6. The problem of ensuring these appropriate voltage levels arises from the fact that the voltage at output terminal 13 rises to (V.sub.2 +V.sub.1), the terminal 15 to (V.sub.2 +2V.sub.1) during the phase when the auxiliary switching transistors M.sub.5 and M.sub.6 are "off" thereby raising their threshold voltages for subsequent turning "on" to a value somewhat above V.sub.1 =5 volts, typically to about 6 volts; accordingly, the capacitor C.sub.3 (in combination with M.sub.7) bootstraps the clock pulse input at terminal 17 to a voltage sufficiently above 5 volts to turn "on" the transistors M.sub.5 and M.sub.6.

For example, after the first few or more cycles of the clock .phi. at the pulsed voltage clock input terminal 17, when the clock .phi. is "low", typically 0 volts, the transistor M.sub.7 (acting as a diode) brings the voltage at the terminal 16 (gate electrode of C.sub.3) to a level of typically 4 volts, i.e., V.sub.1 (=5 volts) less the threshold of M.sub.7 (=1 volt), just before the start of every "charging" phase. Thereafter, when the clock .phi. goes "high", i.e., to +5 volts, the capacitor C.sub.3 bootstraps the voltage at terminal 16 typically to about (4+5) or 9 volts, which is more than sufficient to ensure the turning "on" of the auxiliary transistors M.sub.5 and M.sub.6. Still later on, when the clock .phi. goes "low" i.e., back to 0, the voltage at terminal 16 returns to V.sub.1 less the threshold of M.sub.7, thereby turning "off" again the auxiliary transistors M.sub.5 and M.sub.6.

The purpose of the transistor M.sub.8 is to prevent the voltage at terminal 16 from staying above the voltage V.sub.1 plus a threshold of M.sub.8 when the clock .phi. goes "low", that is, when the terminal 16 is supposed to be at a voltage suitable for turning "off" the auxiliary transistors M.sub.5 and M.sub.6. This problem, of the voltage at terminal 17 staying too high when the clock goes "low", is particularly acute where the overlap capacitance of terminal 16 with the output terminal 13 is appreciable, which is exacerbated by the presence of many stages and thus by more overlap capacitance as well as by even higher voltage on the output terminal 13 due to multistage voltage multiplication. When the clock .phi. goes "high", the transistor M.sub.8 turns "on", thereby tending to reduce the voltage at terminal 16 to about V.sub.1 plus a threshold of M.sub.8 or to about 6 volts. Thus, when the clock .phi. subsequently goes "low", the voltage at terminal 16 goes down suddenly by about 5 volts, i.e., by the clock pulse height of .phi., to a voltage of slightly over 1 volt, which is sufficiently low for turning "off" the transistors M.sub.5 and M.sub.6 even in the presence of overlap capacitance of terminal 17 with the output terminal 13 so long as this overlap capacitance is small as compared with the capacitance of the bootstrap capacitor C.sub.3.

FIG. 3 illustrates a voltage multiplier circuit of four stages. Analogous elements (not necessarily of identical parameters) of succeeding stages are labeled with the same reference numerals or subscripts plus ten. At the output terminal 43 of the fourth stage an output transistor M.sub.54 delivers the multiplier output (V.sub.2 +4V.sub.1), or typically (5+4.times.5=)25 volts, to an output capacitor (C.sub.51) at multiplier output terminal 61 only during the phases of .phi. when all the stages are mutually connected in series with the input voltage V.sub.2 at input terminal 11, that is, when the transistors M.sub.1, M.sub.11, M.sub.21, M.sub.31, and M.sub.54, are all "on". The output transistor M.sub.54 serves to deliver output at the desired multiplied voltage level immediately after the charging phase without loss of any threshold voltage. Resistor R.sub.51 represents a load element as a utilization means that conducts charge out of C.sub.51 and transfers this charge to the ground terminal. Additional output transistors M.sub.51, M.sub.52, M.sub.53 likewise furnish the output of the first, second, and third stages to the multiplier output terminal 61 only for the purpose of speeding up the transients, furnishing some output, albeit below the desired ultimate output voltage level, from the earlier, lower impedance stages. However, this later purpose is optional, so that these transistors M.sub.51, M.sub.52, and M.sub.53 can be omitted, thereby connecting to the multiplier output terminal 61 only the output transistor M.sub.54 and the output capacitor C.sub.51.

For purposes of illustration only, an example of the various parameters for the components in FIG. 3 in N-MOS technology follows (transconductances of transistors, capacitances of capacitors, resistance of resistors):

M.sub.1 =2000 microamps/volts.sup.2

M.sub.2 =25

M.sub.3 =6750

M.sub.4 =250

M.sub.5 =6750

M.sub.6 =25

M.sub.7 =25

M.sub.8 =25

M.sub.11 =1500

M.sub.12 =25

M.sub.13 =2250

M.sub.14 =250

M.sub.15 =2250

M.sub.16 =25

M.sub.21 =1000

M.sub.22 =25

M.sub.23 =750

M.sub.24 =250

M.sub.25 =750

M.sub.26 =25

M.sub.31 =1000

M.sub.32 =25

M.sub.33 =250

M.sub.34 =250

M.sub.35 =500

M.sub.36 =25

M.sub.51 =500

M.sub.52 =500

M.sub.53 =500

M.sub.54 =500

C.sub.1 =270 pf

C.sub.2 =1

C.sub.3 =30

C.sub.11 =90

C.sub.12 =1

C.sub.21 =30

C.sub.22 =1

C.sub.31 =10

C.sub.32 =2

C.sub.51 =100

R.sub.51 =10 megohm

Although this invention has been described in detail in terms of specific embodiments, various modifications can be made without departing from the scope of the invention. For example, P-MOS (P-channel) technology can be used instead of N-MOS, with reversal of polarity of the various voltage applied to the circuit. Moreover, for example, although the ratio of the capacitances C.sub.1 :C.sub.11 is equal to 270/90=3 in the above illustrative example, this ratio can be made as low as about 1.2, at some sacrifice of transient time, however. Likewise, other components can be significantly varied from the above illustrative values without significantly deteriorating the operation.