Integrated Driver Circuit for Display Device

This invention relates to a driver circuit, and more particularly to an integrated driver circuit suitable for actuating a display device used with, for example, an electronic timepiece or desk-top calculator.

Where a liquid crystal is used as a display device of, for example, an electronic timepiece, a lamp is set near the liquid crystal display device. Where it is desired to recognize time at night, the lamp is lighted and the lamp light is directed to the liquid crystal display device for visual perception of time.

Where, with a circuit for operating the above-mentioned type of display lamp, a field effect transistor (hereinafter referred to as "an MOS transistor") was used to actuate the display lamp, then it was necessary to cause a ratio between the length and width of the channel of the MOS transistor to have a considerably large value. Where an MOS transistor of such arrangement was incorporated in an integrated circuit, the manufacture of the integrated circuit was subject to a low yield due to, for example, an increase in leakage current and the appearance of a large number of pin holes in the insulating gate film of the MOS transistor. Further, the unavoidable bulky formation of the MOS transistor resulted in the enlargement of an integrated circuit chip and in consequence a higher production cost. With the conventional lamp-actuating circuit, therefore, a bipolar transistor presenting little internal resistance and a mechanical switch were provided outside of an integrated circuit. The lamp was connected to the bipolar transistor so as to be drived directly by closing the mechanical switch.

FIG. 1 illustrates the arrangement of a prior art driver circuit. An inverter circuit IN provided in an integrated form is grounded at a terminal 1. The power supply terminal 2 of the inverter circuit IN is connected to the negative pole of a cell of 1.5 volts whose positive pole is grounded. A switch SW is connected between the power supply terminal 2 and input terminal 4 of the inverter circuit IN. There is provided a bipolar NPN type transistor Tr presenting an extremely small operation resistance, whose emitter is connected to the power supply terminal 2, whose collector is connected to the grounding terminal 1 through a lamp L, and whose base is connected to the output terminal 3 of the inverter circuit IN through a resistor R1. Where, with an electronic timepiece comprising the above-mentioned driver circuit, it is desired to find time at night, the switch SW is closed to actuate the inverter circuit IN, then the bipolar NPN transistor Tr is rendered conducting to light the lamp L.

Recently, increasing demand is made to incorporate a display device-actuating circuit in an integrated arrangement for the simplification of the construction of an electronic timepiece and the elevation of its reliability. Where, however, it is attempted to incorporate the bipolar transistor of FIG. 1 in an integrated circuit arrangement, then it is necessary to connect the lamp L to the emitter, that is, the bipolar transistor must be used as an emitter follower type. Where the lamp L is connected to the emitter follower type circuit, a power sufficiently enough to drive the lamp is not obtained owing to the fact that the inverter IN produces as small an output as 1.5 volts and the base-emitter voltage V.sub.BE of the bipolar transistor Tr has a level of about 0.6V. Therefore, it is extremely hard to try to incorporate a bipolar transistor as a display device-actuating element in an integrated circuit.

Further, where it is attempted by customary practice to incorporate an MOS transistor as a display device-actuating element in an integrated circuit, then it is necessary to resolve in advance the aforesaid problems of increased leakage current and prominent appearance of pinholes in the transistor gate insulating film.

FIG. 2A shows the arrangement in which, a power source voltage V.sub.SS is impressed on the drain of an MOS transistor 5 through a lamp L, the source of said transistor 5 is grounded, and a power source voltage V.sub.SS is supplied to the gate of the transistor 5. FIG. 2B indicates another arrangement in which a power source voltage V.sub.SS is impressed on the drain of an MOS transistor 6 through a lamp L, the source of said transistor 6 is grounded, and the gate of the transistor 6 is supplied with a voltage n.multidot.V.sub.SS which is n-fold (n > 1) larger than the power source voltage V.sub.SS.

The present inventors have discovered that where, as shown in FIG. 2B, a voltage n.multidot.V.sub.SS which is n-fold larger than the power source voltage V.sub.SS supplied to the drain of the MOS transistor 6 through the lamp L is impressed on the gate of said MOS transistor 6, then it is possible to attain the same effect as the MOS transistor 5 even when the MOS transistor 6 is reduced in size to 1/n of that of the MOS transistor 5. The reason is that, with the MOS transistors 5, 6 assumed to have an equal channel length, the channel width W.sub.2 of the MOS transistor 6 can be made smaller than 1/n of the width W.sub.1 of the MOS transistor 5. If, therefore, the MOS transistor 6 is used as a display device-actuating element under the condition shown in FIG. 2B, then it is possible prominently to decrease the occurrence of leakage current in said MOS transistor 6 and also the appearance of pinholes in the gate insulating film thereof, thereby enabling a driver circuit element to be manufactured with an improved yield, and, as naturally expected, decreasing an integrated circuit chip and in consequence prominently cutting production cost. For the foregoing reason, the MOS transistor 6 can be easily incorporated in an integrated circuit together with other elements. There will now be given the reason why the MOS transistor 6 can be made smaller than the MOS transistor 5.

Now, W.sub.1 /L.sub.1 (channel width/channel length) is taken to denote the size of the MOS transistor 5, and W.sub.2 /L.sub.2 (channel width/channel length) to represent the size of the MOS transistor 6. Further, the following characters are taken to represent the items given opposite thereto.

I.sub.DS = current flowing between the drain and source

V.sub.DS = voltage impressed across the drain and source

V.sub.T = pinch off voltage

.epsilon..sub.OX = dielectric constant of an gate oxide film of the gate

T.sub.OX = thickness of the gate oxide film

.mu. = mobility of holes

V.sub.G = gate voltage

Assuming that the MOS transistors 5, 6 have an equal value in the respective items of I.sub.DS, V.sub.DS, V.sub.T, .epsilon..sub.OX, T.sub.OX and .mu., then there result the following equations (1), (2): ##EQU1## The equation (1) and (2) may be expanded as follows: ##EQU2##

Supposing V.sub.G - V.sub.T >> 1/2 V.sub.DS, the following equation (4) may be derived from the equation (3): ##EQU3## Since n > 1 and (V.sub.G /V.sub.T) - 1>0, the following equation (5) results from the equation (4): ##EQU4## Now assuming L.sub.1 = L.sub.2, then there results the following equation (6): ##EQU5##

Therefore, the object of this invention is to provide a driving circuit arranged in an integrated circuit, in which at least one MOS transistor for operating a load is incorporated together with a MOS transistor gate bias voltage circuit for generating a voltage n-fold larger than that of a power source.

According to an aspect of this invention, there is provided a driver circuit arranged in an integrated circuit which comprises a signal generator for producing output signals when supplied with the voltage of a power source; a level converting means for changing the level of one of said output signals into a control signal having a voltage level n-fold (n > 1) larger than that of a power source; and at least one field effect transistor whose ON-OFF operation is controlled by the control signal to actuate an externally provided load.

Since, according to this invention, the gate of an external load-actuating MOS transistor incorporated in an integrated circuit is supplied with a control voltage having a voltage n-fold (n > 1) larger than that of a power source, it is possible to render the subject MOS transistor very compact and utilize all the advantages derived from the miniaturization of the MOS transistor. Therefore, an integrated driver circuit whose realization has hitherto been considered difficult can now be easily provided.

FIG. 1 shows the typical arrangement of a prior art driver circuit;

FIGS. 2A, 2B are driver circuits respectively for explaining features of this invention;

FIG. 3 is a block circuit diagram of a driver circuit according to one embodiment of the invention;

FIG. 4 is a circuit diagram corresponding to FIG. 3;

FIG. 5 is a block circuit diagram of a driver circuit according to another embodiment of the invention; and

FIG. 6 is a block circuit diagram of a driver circuit according to still another embodiment of the invention.

Referring to FIG. 3, broken lines define an integrated circuit (1C) 10 in which the driver circuit of this invention is incorporated. The integrated circuit 10 contains a signal generator 11, voltage step-up circuit 12, level converter 13 and load-actuating N channel type MOS transistor 14. A cell 17 of, for example, 1.5 volts is connected between a power supply terminal 15 and grounding terminal 16 with the indicated polarity. A load 19 is connected between an output terminal 18 and the positive pole of the cell 17.

The signal generator 11 comprises, for example, a frequency divider and clock pulse generator, and sends forth prescribed output signals when supplied with a power source voltage V.sub.DD and also with a proper control signal from an input terminal 20. The level of one of the output signals issued from the signal generator 11 is stepped up by the voltage step-up circuit 12 to a voltage n V.sub.DD (n > 1) which is n-fold larger than the power source voltage V.sub.DD and the output of the circuit 12 is supplied to the level converter 13 which generates a control signal for controlling the MOS transistor 14. The level converter 13 sends forth the control signal 21 under control of another output signal from the signal generator 11. This control signal 21 has a voltage of n V.sub.DD to control ON or OFF of the MOS transistor 14. Where the MOS transistor 14 is rendered conducting, then the load 19, for example, a lamp or liquid crystal or light emitting diode is actuated. The voltage step up circuit 12 and level converter 13 may be applied in various modifications. The embodiment of FIG. 4 comprises a voltage doubler 12a used as a voltage step-up circuit and an inverter 13a used as a level converter. Referring to FIG. 4, a series circuit formed of diodes D.sub.1, D.sub.2 and capacitor C.sub.2 is connected between the power supply terminal 15 and grounding terminal 16 with the indicated polarity. An output from the signal generator 11 whose voltage level should be stepped up is supplied to a junction of the diodes D.sub.1, D.sub.2 through a capacitor C.sub.1. A voltage (impressed across both terminals of a capacitor C.sub.2) whose level has been stepped up to about 2 fold of the power source voltage V.sub.DD is impressed across both terminals of the complementary inverter 13a formed of a P channel type MOS transistor and an N channel type MOS transistor. The operation of said complementary inverter 13a is controlled by another output from the signal generator 11 to produce a gate control signal 21. The aforesaid load 19 is operated by the power source voltage V.sub.DD only when the MOS transistor 14 is rendered conducting by the control signal 21. It is obvious that since, as apparent from FIG. 4, the gate control signal 21 has a level corresponding to an amplitude of n V.sub.DD , it is possible to adapt the MOS transistor 14 having the above-mentioned advantages.

FIG. 5 is a block circuit diagram of a driver circuit adapted to light a lamp L for illuminating the liquid crystal display device (not shown) of an electronic timepiece. An integrated circuit 25 enclosed in broken lines contains a pair of input terminals 26, power supply terminals 27, 28, output terminal 29 and switch terminal 30. The paired input terminals are connected to a signal generator 32 including an oscillator and frequency divider etc. and an external circuit formed of a quartz oscillation element 33 and capacitor 34. The power supply terminals 27, 28 are connected to the positive pole (voltage V.sub.DD) of a power source E and the negative pole (voltage V.sub.SS) thereof, respectively. A lamp L is connected through a cell E between the output terminal 29 and power supply terminal 27. A switch SW is connected to a switch terminal 30. The integrated circuit 25 contains not only the signal generator 32, but also a first level-stepping up circuit 35, second level-stepping up circuit 36, first level converter 37, second level converter 38, third level converter 39, driving MOS transistor 42, control circuit 41 for controlling the operation of said MOS transistor 42 and clock control circuit 40. The voltages V.sub.DD, V.sub.SS are supplied to the signal generator 32. The voltage V.sub.DD is also supplied to the elements 35, 36, 37, 38, 39, 40, though not indicated in FIG. 5. The embodiment of FIG. 5 is so designed as to render the driving MOS transistor 42 conducting only when the switch SW is thrown in. Namely, when the switch SW is closed, the circuit 41 for controlling the operation of the driving MOS transistor 42 sends forth an output, which in turn actuates the clock control circuit 40 supplied with a clock signal from the signal generator 32, and second level converter 38. The first level-stepping up circuit 35 steps up the level of an output signal from the signal generator 32. An output from the first level step-up circuit 35 is conducted to the first level converter 37.

When supplied with a control signal from the clock control circuit 40 the first level converter 37 converts an output from the first level-stepping up circuit 35 into a first control signal, which in turn is conducted to the second level-stepping up circuit 36. When supplied with an output from the control circuit 41, the second level converter 38 converts an output from the first level-stepping up circuit 35 into a second control signal, which in turn is delivered to the third level converter 39. When supplied with the first control signal from the first level converter 37, the second level-stepping up circuit 36 further steps up the level of an output from the first level-stepping up circuit 35. An output from said second level-stepping up circuit 36 is supplied to the third level converter 39. When supplied with a second control signal from the second level converter 38, the third level converter 39 converts an output from the second level-stepping up circuit 36 into a third control signal, which in turn is transferred to the gate of the driving MOS transistor 42. Obviously, the operation of this driving MOS transistor 42 is controlled by a gate voltage equal to n-fold of the power source voltage V.sub.DD.

FIG. 6 is a block circuit diagram of an integrated driving circuit 44 (enclosed in broken lines) which is adapted to actuate a light-emitting diode display device 45 of an electronic timepiece. The integrated driving circuit 44 comprises input terminals 48 connected to a signal generator including an oscillator and frequency divider, etc. (these input terminals 48 are also connected to an external circuit formed of a quartz oscillator element 33 and capacitors 34 as in the embodiment of FIG. 5); output terminals a to h which are to be connected to the light emitting diode display device 45; output terminals D.sub.1 to D.sub.4 for supplying an input to a digit driver 49 for actuating each digit included in the light emitting diode display device 45; a terminal 50 for supplying source power (V.sub.DD); a terminal 51 for supplying source power (V.sub.SS); a terminal 52 for connecting a display switch SW.sub.3 ; and terminals 54, 53 for connecting time-correcting switches SW.sub.1, SW.sub.2 respectively. The integrated driving circuit 44 further comprises a time counting signal-producing circuit 56 for converting output signals from the signal generator 47 into time counting signals; a decoder 57 for decoding the time counting signals; an ON-OFF control circuit 58 for selective ON or OFF operation of the output terminals a to h of the decoder; a voltage-stepping up circuit 59; a level-converting assembly 60 including a plurality of level converters for selectively converting output voltage signals (having a level of n V.sub.DD) from said voltage-stepping up circuit 59 into control signals; and a plurality of MOS transistors 61a to 61h whose gates are connected to the corresponding level converters. The source of each MOS transistor is grounded and the drain thereof is connected to the corresponding one of the output terminals a to h. One of the output signals from the signal generator 47 is supplied to a clock control circuit 62. The resultant output clock pulse is stepped up to a desired voltage level by the voltage-stepping up circuit 59 to be delivered to the level-converting assembly 60. Signals D.sub.1 to D.sub.4 (denoted by the same characters as those of the output terminals) are conducted to the digit driver 49 through an ON-OFF control circuit 63. When the display switch SW.sub.3 is closed, then a display command signal 64 is supplied to the clock control circuit 62 and ON-OFF control circuits 58, 63, thereby coursing time to be indicated on the light-emitting diode display device 45.

With the embodiment of FIG. 6, the MOS transistor 61a to 61h are each so arranged as to be operated by a voltage of n V.sub.DD and can be easily incorporated in the integrated circuit 44. Throughout the foregoing embodiments, the driving MOS transistor may be of the P or N type.