Lateral Field Controlled Thyristor

1. Field of the Invention

The present invention relates to a semiconductor switching device. In particular, the invention relates to a semiconductor switching device having a high dv/dt capability.

2. Description of the Prior Art

Heretofore, when semiconductor switching devices are to be implemented in an integrated form, a plurality of lateral thyristors such as shown in FIG. 1, for example, are formed in respective islands isolated from one another by a pn-junction or a dielectric isolation layer with wirings to the electrodes of the lateral thyristors being made so that desired characteristics are obtained. Associated circuits are formed in the same semiconductor substrate. In FIG. 1, numerals 1, 2 and 3 denote an anode electrode, a cathode electrode and a gate electrode, respectively, while numeral 4 denotes a cathode region, 5 denotes a gate region, 6 denotes an anode region, and 7 denotes a semiconductor substrate. The lateral thyristor shown in FIG. 1 and in more general hitherto known thyristors suffer from drawbacks described below. When a positive voltage is applied to the anode with a negative voltage applied to the cathode electrode, the thyristor takes a blocking or non-conducting state so far as the gate electrode is closed. However, when a voltage v.sub.a which increases as a function of time (i.e. a voltage having a positive value of dv.sub.a /dt) is applied to the anode electrode 1, a displacement current is produced and flows from the anode electrode 1 to the cathode electrode 2. This displacement current will then act as a gate trigger current to drive undesirably the thyristor into the conducting state. Such phenomenon provides a serious problem particularly in applications in which the thyristor is employed in a circuit subjected to various noises and/or operated at a high switching frequency, involving a degraded reliability of the thyristor and imposing restriction to a desired high speed operation. With a view to increasing the dv/dt capability, it is known to connect an external resistor between the gate electrode 3 and the cathode electrode 2 or provide means for internally producing a short-circuit between the cathode region 4 and the gate region 5, thereby to prevent the displacement current from flowing into the cathode region as the gate trigger current. However, these measures in turn constitute a shunt current path for the gate current flowing into the cathode region 4, bringing about a new drawback that the intrinsic trigger current is increased. The increased trigger current is of course disadvantageous particularly in a circuit in which a number of the switching devices are employed since the sum of the gate currents will then amount to a significantly large value. In order to increase the dv/dt capability and at the same time reduce the trigger current, it is conceivable to provide additionally an auxiliary circuit including a transistor between the gate and the cathode region, which however means that degradation in the integration density of the switching elements and the correspondingly increased chip area well as accompanying increased manufacturing costs have to be put up with.

An object of the invention is therefore to provide a semiconductor switching device of a novel structure which evades the drawbacks of the hitherto known switching elements and is highly capable of withstanding dv/dt-effect and can be inplemented with a high integration density.

In view of above and other objects which will become more apparent as description proceeds, there is provided a semiconductor switching device which includes a semiconductor substrate of a first conductivity type having an anode region of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate adjacent to a major surface, a gate region formed adjacent to the major surface with a distance from the anode region and having a channel region of a predetermined width and depth and a cathode region formed in the gate region adjacent to the major surface so as to be directly contacted to the semiconductor substrate through the channel region, wherein a current path leading from the anode region to the cathode region through the substrate is interrupted by a depletion layer produced within the substrate in the vicinity of the channel region upon application of a reverse bias voltage between the gate and the cathode electrode. In the absence of the reverse bias voltage, the anode region, the semiconductor substrate, the gate and the cathode region cooperate to function as a thyristor.

FIG. 1 is a schematic sectional view showing a structure of a conventional semiconductor switching device.

FIG. 2 is a schematic sectional view of a semiconductor switching device according to an embodiment of the invention.

FIGS. 3A and 4A are top plan views showing electrode array patterns for the semiconductor switching device shown in FIG. 2.

FIG. 3B is a sectional view taken along the line IIIB-IIIB' in FIG. 3A.

FIG. 4B is a sectional view taken along the line IVB-IVB' in FIG. 4A.

FIG. 3C is a sectional view taken along the line IIIC-IIIC' in FIG. 3A.

FIG. 4C is a sectional view taken along the line IVC-IVC' in FIG. 4A.

FIG. 5A is a top plan view of a semiconductor switching device according to another embodiment to the present invention.

FIGS. 5B and 5C are sectional views taken along lines VB-VB' and VC-V' in FIG. 5A, respectively.

FIG. 6A in a top plan view of a semiconductor switching device according to further embodiment according to the present invention.

FIGS. 6B and 6C are sectional views taken along lines VIB-VIB' and VIC-VIC' in FIG. 6A, respectively.

FIGS. 7 to 8 show yet further embodiments of the present invention.

FIG. 9 graphically illustrates operation characteristics of the semiconductor switching device according to the present invention.

FIGS. 10A to 10C illustrate manufacturing steps for fabricating the semiconductor switching device shown in FIG. 2.

FIG. 2 shows schematically a sectional structure of a semiconductor switching device according to an embodiment of the invention. In FIG. 2, the same reference numerals are applied to like parts as in FIG. 1. Referring to FIG. 2 an anode region 6 of p.sup.+ -conductivity type and a cathode region 4 of n.sup.+ -type conductivity are provided at a same major surface of a semiconductor substrate of n-conductivity type. A gate region 5 of p.sup.+ -conductivity type is so provided as to be partially exposed around the cathode region 4 at the major surface and forms a groove or channel region 9 of n-conductivity type immediately below the n.sup.+ -cathode region 4. Consequently, the n.sup.+ -cathode region 4 is directly connected to the n-substrate 7 through the n-channel region 9. It should be mentioned here that, in the case of the illustrated structure, the anode region, the cathode region, the gate region and the channel region are each formed in a strip-like configuration. Further, a plurality of the switching devices of this structure may be provided in a single semiconductor wafer, each being formed in an island or well isolated from the others by a pn-junction layer or alternatively by an insulating or dielectric layer and interconnected in desired manner. Arrays of electrodes for the anode region, the cathode region and the gate region may practically be implemented in simplified patterns shown in FIGS. 3A, 3B and 3C and FIGS. 4A, 4B and 4C. In these figures, the same reference numerals are applied to the like parts as in FIG. 2. In FIGS. 3B; 3C and 4B; 4C, reference numeral 10 denotes a film of SiO.sub.2 which does not appear in FIGS. 3A and 4A. Although the n-channel region 9 is shown as lying within the boundary of the cathode region 4 in FIGS. 3A and 3C, it should be understood that the n-channel region may extend longitudinally beyond the cathode region 9 into the substrate region as shown in FIGS. 4A and 4C. However, in any case, the channel region 9 should preferably be positioned in a longitudinal alignment with and immediately below a middle portion of the cathode region 4 as seen from FIGS. 3A, 3C and 4A, 4C in order to assure a symmetrical current extraction and prevent non-uniformity in a current density when the switching device is turned off. It is further to be noted that the width d.sub.1 of the channel 9 is so selected as to be narrower than the widths d.sub.2, d.sub.3 of the lower surface of the cathode region 4 opposed to the major surface at both longitudinal sides of the channel region 9 as measured from the respective longitudinal edges of the channel region 9 in the width direction thereof. This arrangement is particularly important for enhancing the action and effect envisaged by the invention, as will be made more apparent as description proceeds.

FIGS. 5A, 5B, 5C shows another embodiment of a semiconductor switching device of this invention in which a plurality of channels (for example, 4 channels as seen from the figure) are provided. In FIGS. 5A, 5B, 5C, the same reference numerals are applied to like parts as in FIG. 2. Referring to FIG. 5A, a gate region 5 is integrally formed to surround a plurality of strip-like cathode regions 4 spaced apart from each other and arranged in parallel. The plurality of channel regions 9 are provided beneath the respective cathode regions. An anode electrode 1, a comb-like cathode electrode 2, and a comb-like gate electrode 3 are kept in ohmic contact with the anode region 6, the cathode regions 4 and the gate region 5. The comb-like cathode electrode 2 and the comb-like gate electrode 3 are arranged in interdigitated form. The divergent arrangement of the gate electrode in such interdigitated form provides a small voltage drop in the gate region 5, which makes easy a gate turn-off action. A plurality of anode regions may be arranged. Namely, as shown in a phantom line in FIG. 5A another anode region 6' may be added, which advantageously expands a current path and decreases a forward voltage drop.

FIGS. 6A, 6B, 6C show further embodiment of a semiconductor switching device of this invention which is a modification of FIGS. 5A, 5B, 5C and in which a high impurity region 12 of n.sup.+ conductivity type is provided to be adjacent to the anode region 6 at at least one portion thereof in an area in the main surface opposite to the gate region 5, and the anode electrode 1 is kept in ohmic contact to both the anode region 6 and the high impurity region 12.

In FIGS. 6A, 6B, 6C, the same reference numerals are applied to like parts as in FIGS. 5A, 5B, 5C. This structure provides the following effects.

1. The high impurity region 12 stops a depletion layer which may extend from the gate region 5, which enhances the breakdown voltage of the device.

2. The charges stored in the base region (the substrate 7) at the time of turn-off of the device are derived through the high impurity region 12 to the anode electrode 1 and annihilated there, which provides a short turn off time. It is of course that the above arrangement of the high impurity region 12 and the anode electrode 6 are also applied to the embodiments of FIGS. 3A, 3B, 3C and 4A, 4B, 4C.

Now, description will be made on the principle of operation of the semiconductor switching device according to the invention. It is assumed that the gate electrode 3 is connected to a negative pole of a power supply source of voltage V.sub.g with the cathode electrode 2 connected to a positive pole of the power supply source so that a junction J3 is biased reversely or backwardly when a switch S is closed. Under this condition, there will be produced a depletion layer 11 as indicated by a dashed line. However, the spatial extension of the depletion layer 11 is in general restricted in the regions other than the n-channel region 9, which can be explained by the fact that the impurity concentrations of the p.sup.+ -gate region 5 and the n.sup.+ -cathode region 4 are selected relatively higher than that of the n-channel region 9 which is equal to the impurity concentration of the n-semiconductor substrate 7. When the width d.sub.1 and depth l of the n-channel region 9 as well as the voltage V.sub.g of the power supply source are selected at appropriate values, the n-channel region 9 can be perfectly pinched off by the depletion layer 11. In such condition, no current will flow from the anode electrode 1 to the cathode electrode 2 even if a voltage which is positive relative to the cathode electrode 2 is applied to the anode electrode 1, because the n-channel region 9 constituting a part of the current path between the anode electrode 1 and the cathode electrode 2 is completely pinched off. In other words, the switching device is in a blocking or non-conducting state. Of course, a rapid rise of the anode voltage applied to the anode electrode 1 may produce a displacement current, which will not however flow across the junction J3 but flow to the gate electrode 3 and hence to the cathode electrode 2 by way of an external circuit. This feature in combination with the negative biasing of the gate electrode 3 relative to the cathode electrode 2 will never give rise to the accidental turn-on of the switching device. Even if the p-gate region 5 lying immediately below the n.sup.+ -cathode region 4 is relatively broader to bring about a voltage drop in the lateral or transverse direction due to the displacement current, the switching device can be positively prevented from being undesirably turned on by applying the gate voltage V.sub.g applied to the gate electrode 3 of a sufficiently great magnitude to overcome the lateral voltage drop described above. Further, by providing an auxiliary n.sup.+ -cathode region in the p-gate region 5 as illustrated in FIG. 7 or alternatively increasing the number of the electrodes connected to the p.sup.+ gate region 5 as illustrated in FIG. 8, the voltage drop in the lateral or transverse direction due to the displacement current can be much more reduced, thereby to inhibit more positively the erroneous turn-on of the switching device. In FIGS. 7 and 8, the same reference numerals are applied to like parts as in FIG. 2.

When the reverse bias voltage across the junction J3 between the p-gate region 5 and the n.sup.+ -cathode region 4 is removed by opening the switch S, the depletion layer 11 extending into the n-channel region 9 will then disappear, resulting in the current being allowed to flow from the anode electrode 1 to the cathode electrode 2 through the n-channel region 9 upon application of a positive voltage onto the anode electrode 1 relative to the cathode electrode 2. When positive holes are injected into the n-substrate from the p.sup.+ -anode region 6 due to the current flowing through the n-channel region 9 and reach the junction J2 formed around the p-gate region 4, electrons are then injected into the p-gate region 5 from the n.sup.+ -cathode region 4. Consequently, when a sum of the current amplification factors .alpha..sub.pnp and .alpha..sub.npn, respectively of a p.sup.+ np.sup.+ -transistor constituted by the p.sup.+ -anode region 6, the n-substrate 7 and the p.sup.+ -gate region 5 and an np.sup.+ n.sup.+ -transistor constituted by the n-substrate 7, the p.sup.+ -gate region 5 and the n.sup.+ -cathode region 4 becomes greater than 1 (a unit), a p.sup.+ np.sup.+ n.sup.+ -thyristor constituted by the p.sup.+ -anode region 6, the n-substrate 7, the p.sup.+ -gate region 5 and the n.sup.+ -cathode region 4 is turned on. The n-channel region 9 will then function as a diode, while the other portions cooperates with one another to function as a thyristor, whereby current flows into all the region of the n.sup.+ -cathode region 4. Such thyristor operation will result in an increased conducting area of the device and significantly reduce the turn-on voltage to a great advantage.

FIG. 9 graphically illustrates characteristics of the switching device according to an embodiment of the invention in which the dimensions d.sub.1 and l described hereinbefore have been selected equal to 3 .mu.m and 5 .mu.m, respectively. When the gate electrode 3 is opened with a positive voltage being applied to the anode electrode 1, the switching device is turned on (i.e. in the conducting state) to allow the anode current to flow therethrough. When the source voltage V.sub.g is -3.5 volts, no current flow will be produced because of the n-channel region 9 being pinched off. However, as the anode voltage is increased, the potential barrier produced in the n-channel region 9 is cleared by the electric field of the depletion layer 11 extending from the junction J2 around the p.sup.+ -gate region 5 toward the p.sup.+ -anode region 6, thereby to eventually allow the current to start flowing. The anode voltage which can be blocked by increasing the gate voltage will increase in a manner illustrated in FIG. 9. However, there is an upper limit imposed on the forward blocking voltage since the voltage applied across the gate-cathode path is subjected to a limit. By selecting the width d.sub.1 of the n-channel region, the pintch-off voltage can be correspondingly decreased, which means that a high anode voltage can be blocked with the aid of a relatively low gate voltage. Further, it has to be pointed out that the gate voltage can be made lower, as the depth l of the n-channel region 9 is selected greater. In practice, optimum values for the width and the depth of the n-channel 9 are selected in consideration of the reproducibility of the fabricating process as well as the thickness of the p.sup.+ -gate region 5 of the thyristor switch.

As will be appreciated from the above description, a characteristic feature of the switching device according to the invention can be seen in a composite structure including a lateral thyristor and a field controlled switching device, which is very advantageous in that a high dv/dt-capability can be attained and that integrated structure can be easily realized. These and other advantages of the invention may be more clearly understood by comparing it with a hitherto known thyristor structure such as disclosed in U.S. Pat. No. 4,060,821 and applied to a lateral thyristor, for example. In the case of the prior art structure disclosed in the above U.S. patent, there is interposed an n-layer to extend to one main surface between a cathode region and a gate region. Presence of such n-layer corresponding to the channel region 9 of the device according to the present invention will however act to increase the turn-on voltage in the case of the lateral thyristor structure according to the invention. Accordingly, the invention teaches the structure which can eliminate the need for provision of such n-type layer to assure more effective thyristor operation and allow a larger current to be processed. Further, according to the teaching of the invention, the n-channel width can be made narrower, while the area of the cathode region can be made larger than the exposed area of the gate region. Consequently, a large current can be turned on and off with a relatively low gate voltage and a relatively small area of the gate region at a relatively high integration density of the integrated structure. In the second place, the epitaxial growth process indispensable for the fabrication of the thyristor structure disclosed in the above cited U.S. patent is not required in the case of the swiching device according to the invention. In general, when a plurality of switching elements are to be implemented in an integrated structure, it is necessary to isolate the switching devices or elements from one another. In this connection, it is noted that an attempt to minimize the electrostatic capacity between the switching elements by employing an isolation of an isolated gate type will requires a specific selective epitaxial growth process, incurring expensiveness in manufacture, since such requirement can not be fulfilled by a conventional technique of uniform epitaxial growth over a whole wafer. Besides, the epitaxial growth process by itself is expensive, as pointed out in the specification of U.S. Pat. No. 4,037,245.

In the third place, difficulty may be encountered in attaining an impurity concentration of an epitaxially grown layer equal to or lower than that of the substrate. For example, when an epitaxially grown layer having an impurity concentration of 1.times.10.sup.13 cm.sup.-3 is to be formed in a semiconductor substrate having an impurity concentration of 1.times.10.sup.15 cm.sup.-3, there may undesirably be formed a high resistivity layer or a p-inversion layer in the interface between the substrate and the epitaxial layer due to a so-called auto-doping from a burried gate layer. Such high resistivity layer allows therein an abnormal instrusion of the depletion layer extending between the anode region and the gate region, involving the problem of punch-through and reducing a breakdown voltage. On the other hand, formation of the inversion layer provides an obstacle in forming the channel in a satisfactory or normal manner and at the same time gives rise to a short-circuited state between the anode electrode and the gate electrode. Even if the fatal characteristic abnormalities due to the auto-doping could be prevented from ocurring. Stacking faults and misfit dislocations will often take place at the interface between the substrate and the epitaxially grown layer, involving possibly degradation in the breakdown voltage and increase in the leak current. In contrast, the lateral type semiconductor switching device can be fabricated simply by a selective diffusion technique through treatments such as diffusion, evaporating electrode deposition and so forth advantageously for easy integration. Additionally, no dv/dt compensating circuit is required, a correspondingly increased integration density can be attained.

Next, a typical example of the process for fabricating the switching device of a structure shown in FIG. 2 will be briefly described by referring to FIG. 10A, FIG. 10B and FIG. 10C. At first, an n-semiconductor substrate 7 (FIG. 10A) is prepared which has preferably impurity concentration of 5.times.10.sup.14 atoms/cm.sup.3 and thickness not smaller than 50 .mu.m. Then the p.sup.+ -anode region 6 and the p.sup.+ -gate region 5 are formed through selective diffusion of p.sup.+ -type impurity such as boron, for example, from one major surface simultaneously with the formation of the n-channel region 9 (FIG. 10B). The anode region 6 may be of a p.sup.+ -type diffused layer of 150 .mu.m in width, 300 .mu.m in length and 15 .mu.m in depth or thickness. The p.sup.+ -gate region 5 may be of a p.sup.+ -diffused layer of 150 .mu.m wide, 300 .mu.m thick. The impurity concentration in the regions adjacent to the major surface is selected on the order of 5.times.10.sup.13 atoms/cm.sup.3 so that switching operation can be effected at the pnpn-junctions obtained when the n.sup.+ -cathode region 4 has been formed through diffusion. In practice, the processes described so far may be accomplished by placing a boronnitride wafer and a silicon wafer in a quartz tube and holding at a temperature of about 950.degree. C. for about 30 minutes in the atmosphere of an inert gas and subsequently heating the silicon wafer at about 1200.degree. C. for about four hours in an oxidiging atmosphere. The p.sup.+ -anode region 6 and the p.sup.+ -gate region 5 are formed in the major surface in opposition to each other with a distance of about 100 .mu.m therebetween. The n-channel region 9 formed in the p.sup.+ -gate region 5 should preferably have a width of 3 .mu.m and length of 260 .mu.m. Subsequently, the n.sup.+ -cathode region 4 is formed through selective diffusion of an n.sup.+ -impurity such as phosphorus, for example. When the surface dimension is selected to be of 80 .mu.m.times.280 .mu.m with a thickness of 10 .mu.m, the n.sup.+ -cathode region 4 is implemented in a structure surrounded by the p.sup.+ -gate region 5 except for the portion corresponding to the n-channel region 9 (FIG. 10C). For the diffusion of phosphorus, vapor of POCl.sub.3 may be introduced onto the silicon substrated in a heated state. For example, by such thermal treatment at 950.degree. C. for 30 minute, the phosphorus diffused layer can be formed which has a high impurity concentration in the cathode region adajent to the major surface. Thereafter, the semiconductor substrate thus obtained is subjected to a thermal treatment at 1200.degree. C. for 60 minutes in an oxidizing atmosphere thereby to form ultimately the n.sup.+ -cathode region 4 of 10 .mu.m in depth having the surface impurity concentration of 2.times.10.sup.20 atoms/cm.sup.3. Finally, the electrodes 1, 2 and 3 are contacted to the p.sup.+ -anode region 6, the n.sup.+ -cathode region 4 and the p.sup.+ -gate region 5, respectively, to accomplish the switching device of the structure according to the invention as shown in FIG. 2. The metallic electrodes may be formed of aluminium films of 2 .mu.m thick through evaporation, for example. The width of the anode electrode 1 and the cathode electrode 2 should preferably on the order of 60 .mu.m, while the gate electrode 3 should preferably be formed of an aluminium film having width of +.mu.m in the case of the illustrated embodiment. In this manner, a thyristor unit of p.sup.+ np.sup.+ n.sup.+ -structure and a diode unit of p.sup.+ nn.sup.+ -structure have been implemented in parallel to each other in the current path extending from the anode region 6 to the cathode region 4. In the above description, it has been of course assumed that the use of a protection or mask film for the selective diffusion as well as a protection film for forming the pn-junctions is indispensable for the fabrication of the intended switching device. However, since the protection technics are well known in the art, further detailed description thereof will be unnecessary. FIG. 9 graphically shows the typical characteristics of a switching device actually fabricated according to the manufacturing process described above.

The invention has now proposed a novel semiconductor switching device in which the thyristor and the diode are caused to operate in parallel to each other in the conducting state, while non-conducting or blocking state is brought about by pinch off of the channel region under the electric field control to interrupt the current flow. In the following, description will be made on advantageous feature of the switching device according to the invention by comparing with conventional switching devices in order to have a better understanding of the invention. At first, comparison will be made with a conventional semiconductor switch which incorporates a transistor as a switching device. The switching transistor is turned on upon application of a base current and turned off when the base current becomes zero. Accordingly, a current supply circuit is inevitably required in order to maintain the transistor switch in the conducting state. In contrast, in the case of the switching device according to the invention, the transition from the non-conducting state to the conducting state or vice versa can be effected merely by applying or removing the gate voltage without requiring any appreciable driving power. Certainly, a current will flow in the gate circuit even in the switching device according to the invention when the switching operation is made to go from the conducting to the non-conducting state. However, the duration of such current flow is extremely short and involves no appreciable power consumption. In this manner, the switching device according to the invention exhibits a very high ratio of the power required for the control to the power to be controlled, which is a very advantageous and desirable characteristic for a switching device. Further, the switching device according to the invention exhibits a high withstanding capability against a surge current and an excellent reliability as the switching device without sufferring from the secondary break-down phenomenon.

The advantages of the switching device according to the invention over the conventional thyristor structure such as shown in FIG. 1 will be obvious from the description made hereinbefore. In the case of the conventional field controlled switching device, the main current path is constituted only by the channel as a result of which a narrow width of the channel region will often give rise to an increaed turn-on voltage. In order to overcome this disadvantage, the channel region has been realized in a plurality of separate sub-channels, which however means that precise and elaborate treatments are required for the fabrication of the field controlled thyristor in a much complicated process. To the contrary, in the case of the semiconductor switching device according to the invention, the main current flows through the thyristor structure with the p.sup.+ nn.sup.+ -type diode structure being subjected to only a small fraction of the main current for turning on the thyristor. Thus, the cathode region can be implemented in a relatively large dimension by virtue of such structure in which the cathode region is commonly shared by the thyristor and the diode, as shown in FIG. 8. Additionally, the manufacturing process can be much simplified. In reality, a locally fine diffusion mask pattern is required only when the channel region is formed. The other fabricating steps can be carried out in the substantially same way as the conventional thyristors.

It has been found that the thyristor portion should preferably have a larger area than that of the diode portion formed by the channel region at least below the lower surface of the cathode region opposite to the major surface to flow the main current through the thyristor portion in order to make the various advantages described above to be available at maximum.

Besides, since the surface impurity concentration in the exposed surface portion of the p-gate region is higher than that of the n-base region (n-subtrate 7) as is illustrated in FIG. 5, means for conducting the displacement current to the localized gate electrode 3 can be favorably realized in a simplificated manner without requiring any complicated electrode pattern. Obviously, a plurality of the n-channel regions 9 may be provided in order to evade current concentration upon turn-on operation of the switching device.