Process for Fabricating Planar SCR Structure

The present invention relates generally to semiconductor controlled rectifiers, and more particularly to the fabrication of planar semiconductor controlled rectifiers with the aim of minimizing the device parameters r.sub.on and V.sub.f, and thereby increasing the yield of acceptable devices.

Typically, it has been the practice heretofore to fabricate the anode region at the same time as the gate region in planar SCR structures, by simultaneous diffusion of the same impurity into the basic single crystal silicon body, since both of these regions are of the same conductivity type. The anode and gate regions are of substantially higher resistivity than the opposite conductivity type cathode region, which is formed within the gate region.

I have found that a substantial increase in yield, i.e., the number of devices in any given batch which after test display acceptable operating characteristics and parameters, may be achieved for planar SCR structures by minimizing the device parameters r.sub.on and V.sub.f. In turn, the desired minimization of these parameters is obtained in accordance with my invention by diffusion of a high concentration of impurities to form a low resistivity anode region in a separate and distinct step from the diffusion of the same impurities in lower concentration to form like conductivity type but higher resistivity gate region. The low resistivity cathode region is within the gate region.

Accordingly, it is a principal object to provide a planar semiconductor controlled rectifier having minimum r.sub.on and V.sub.f.

A related object is to provide a method of fabricating such a controlled rectifier.

FIG. 1 is a sectional view illustrating the preferred embodiment of the controlled rectifier; and

FIG. 2 is a view of the top surface of the structures of FIG. 1.

FIG. 1 depicts an embodiment of a planar semiconductor controlled rectifier fabricated within a body of single crystal semiconductor material 10, preferably N-type silicon. A P-region 20 constituting the anode of the SCR at the planar surface 22 of body 10 is spaced apart from a second P-region 25, the gate, within which an N-type cathode region 30 is formed. All of these regions are formed by conventional planar diffusion techniques, the formation of the cathode within the gate requiring the usual double diffusion. According to the invention the SCR is fabricated to minimize the bulk resistance of the anode and cathode, and thereby to achieve minimization of V.sub.f and r.sub.on. V.sub.f is the anode to cathode voltage of the SCR in the "on" condition, and r.sub.on is the small signal resistance of the SCR in the "on" condition.

While SCR's of the present invention may be fabricated in any suitable body in which they are electrically isolated from one another and/or from other devices of an integrated circuit (IC), it is preferred that the devices be formed in single crystal silicon islands isolated from each other and from a polycrystalline silicon substrate by a thin dielectric layer (e.g., SiO.sub.2). The process of producing such a structure is well known and, since it forms no part of the present invention, need not be discussed in further detail.

In the illustrative embodiment, each single crystal island 10 is N-type silicon doped to a resistivity of approximately 4 ohms-cm, and has a thickness of about 1 mil to an underlying buried layer (not shown) of 5 ohms per square (ohms/sQ.). The polycrystalline wafer containing the islands is cleaned and a 6000 A (6KA) layer of oxide is grown on its surface in a steam ambient at 1100.degree. C, as a diffusion mask. A photoresist and oxide etch procedure is used to expose the planar surface 22 at the desired location of the gate region of each SCR. As is well known, in this procedure a photoresist layer is deposited on the oxide mask, the photoresist is exposed to light in accordance with the desired pattern, the pattern is developed to remove unexposed portions of the photoresist, and the thus-exposed portions of the oxide layer are removed with a suitable etchant.

The remaining photoresist is then removed by stripping to leave an oxide mask with windows for the subsequent gate deposition.

The wafer is then cleaned and processed through a conventional open tube deposition-diffusion sequence with a P-type dopant to form a 3.3 micron deep gate region 25 with a resistivity of 200 ohms per square in the gate location for each SCR. Preferably the P-type dopant is boron, but any other P-type dopant, such as gallium, which will controllably yield an approximately 200 ohms/sq gate region is acceptable. The boron surface impurity concentration is approximately 5 .times. 10.sup.18 atoms/cc for such a resistivity.

During and following the diffusion of the gate region, silicon dioxide is regrown, thereby covering the gate windows and reforming a complete oxide layer.

Another photoresist and oxide etch procedure identical to that described above is performed to open windows at desired locations for diffusion of the anode region of each SCR. After cleaning the wafer, a conventional P-type deposition-diffusion procedure is performed to form an anode region 20 having a depth of 3 microns and a resistivity of 3 ohms/sq. Using a boron dopant, a surface concentration of approximately 5 .times. 10.sup.20 atoms/cc is required for this resistivity. The wafer is then subject to oxidation at 1000.degree. C. in a steam ambient to grow 4 KA of oxide over the windows through which the anode regions were diffused. It is important to note that the anode region 20 is diffused in an entirely separate step from the gate region diffusion, and with a substantially lower resistivity.

Another photoresist and oxide etch process is performed to provide windows for duffusing the cathode regions 30 for each SCR in the respective previously formed gate regions 25. A conventional N-type deposition-diffusion procedure is then performed to form 2.9 micron deep cathode regions of 1.5 ohms/sq. Preferably the N-type dopant is phosphorus but other N-type dopants, such as arsenic or antimony are also acceptable. A phosphorus dopant in a surface impurity concentration of approximately 1 .times. 10.sup.21 atoms/cc provides the desired relatively low resistance of the cathode region. Thus, the anode region 20 and the cathode region 30 are both formed with very low resistivities. The resistivity of the gate region is at least approximately two orders of magnitude greater.

A photoresist and oxide etch procedure is now performed to expose the desired anode contact region 35, cathode contact region 40, and gate contact region 45. The wafer is then chemically cleaned and 50 micro-inches of aluminum is evaporated onto the wafer surface. A final photoresist and aluminum etch is performed to define contact metal to the gate, anode and cathode regions. The final topography is shown in FIG. 2. For the sake of simplicity and clarity, no contacts are shown in the section view of FIG. 1.

The wafers are baked for 20 hours at 300.degree. C to complete the fabrication.

Although the present invention is described by way of example for fabrication in dielectrically isolated single crystal islands, the same basic process may be performed using epitaxial wafers or uniformly doped wafers with junction isolation.

It will also be apparent that all of the N and P regions may be reversed without affecting the essence of the invention.