Electronic Circuit for a Quartz Crystal Watch

The present invention relates to an electronic circuit for a quartz crystal timepiece provided with a stepping motor and comprising an oscillator followed by a divider feeding a logic stage for the control of the said motor.

It is known that one of the principal problems in electronic timepieces consists in finding a way to reduce the size of the electronic circuits. Now in a circuit, particularly if it relates to an integrated circuit the terminal connections take up a lot of room. It is thus important to be able to reduce their number.

This number is defined on the one hand by those of the external components which must be connected to the circuit and on the other hand by those of the controlling and actuating terminals. It could concern for example the control of the frequency of the quartz crystal and the actuating of the stopping of the timepiece when it is to be reset.

In a quartz crystal timepiece having digital display using a stepping motor, the integrated circuit used comprises two supply terminals, two terminals for the quartz crystal, two terminals for the motor and one terminal for controlling stopping of the timepiece. There is no terminal for the measurement of the frequency of the quartz crystal, as this can be effected on one of the terminals of the motor. There is in effect, at this point, the frequency derived by division of that of the quartz crystal.

The terminal to which the motor is connected thus fulfils two functions, that of controlling a motor and that of permitting the measurement of the frequency of the quartz crystal.

The invention proposes to reduce the number of external terminals by a circuit in which the terminals used for the control of the motor also serve to test the frequency of the oscillator and/or to effect the stopping of the watch as well as the return-to-zero of the stages of the divider.

According to the present invention there is provided an electronic circuit for a quartz crystal timepiece provided with a stepping motor and comprising an oscillator followed by a divider feeding a logic stage for the control of the motor, external terminals of the circuit used for the control of the motor being utilised to regulate a frequency derived from the said divider and/or to effect the stopping of the timepiece when it is being returned-to-zero by at least one stage of the said divider.

The present invention will be described further, by way of example, with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of a first circuit according to the present invention;

FIG. 2 is a detailed schematic diagram of the circuit of FIG. 1;

FIG. 3 is an impulse diagram of the circuit of FIG. 2;

FIG. 4 is a detailed schematic diagram of a second embodiment; and

FIG. 5 is a set of impulse diagrams of the circuit of FIG. 4.

In FIG. 1 there is shown a circuit of a quartz crystal timepiece having a polarised stepping motor. An oscillator 1, provided with a quartz crystal 2 and a variable capacitor 3 for regulating the frequency, distributes its impulses on a divider 4 having several stages which actuates a logic circuit 5 for controlling the motor, shown schematically by a coil 7. Between the motor 7 and the control logic 5 there is a driver stage 6. Two supply terminals are shown at + V.sub.BB and -V.sub.BB. To enable the frequency of the quartz crystal to be measured an output 8 of one of the stages of the divider 4 provides a frequency called "of measurement" to one of the terminals B of the motor 7. A measuring instrument may be applied to terminal B of motor 7 for measurement of the frequency transmitted form output 8 to terminal B, this measurement enabling determination of the frequency of oscillator 1. This measurement frequency is also supplied via the other terminal A of the motor 7 to a reset-circuit 9 which compares this frequency with another frequency called "reading signal" from an output 10 of one of the stages of the divider 4. A switch 11 to permit the watch to be stopped is connected between the terminal + V.sub.BB and the terminal A of the motor 7. The outlet of the comparator 9 can deliver a return-to-zero signal "RES" to all or some of the stages of the divider 4.

During normal functioning, when the switch 11 is open, the terminals A and B feed control current to the motor. The measurement frequency, applied at B, can likewise be measured at A between the drive impulses, as the resistance of the motor is small.

The comparator 9 permits the detection, by the rhythm of a reading signal, of the presence or absence of the measurement frequency at A between the drive impulses.

When the switch 11 is open the measurement frequency passes from B to A and the comparator 9 gives no return-to-zero signal "RES" at its outlet. On the other hand, the closing of the switch 11 pulls the terminal A to the potential + V.sub.BB of the battery, of which the low internal resistance blocks the transmission of the measurement frequency. The comparator 9 will then give a return-to-zero signal to the last or to all of the stages of the divider 4 to return them to zero and to lock them in this state.

After the time-setting of the timepiece by normal external mechanical means and the opening of the switch 11, the signal "RES" disappears and the divider 4 starts to function again. After a time interval determined by the number of stages which have been put back to zero, the motor will receive a drive impulse. The polarity of the impulse will always be the same, which implies a mechanical positioning of the motor at the time of the time-setting, so that it functions as soon as the first drive impulse is received.

In the more detailed diagram of FIG. 2, there is illustrated a divider comprising the stages a to w, which are flip-flops having two inputs C1 and C1 two outputs Q and Q and a zero resetting `RAZ`, and correctors 18 and 19 working across NAND gates 16 and 17. The frequency provided by the oscillator (not shown) is 32768 Hz and by a successive division by two, there is obtained at the outlet of the stage o a frequency of 1 Hz. The stages p to s with the corrector 18 divide this frequency by ten then the stages t to v with the corrector 19, divide this result by six, so that the impulses at the outlet of the stage v will have a period of one minute. The correctors 18 and 19 work in known manner, and detect the potentials "1" at certain outlets of the divider stages to send a short impulse coming, in our example, from the outlet Q of the stage d, across the NAND gates 16 and 17 to the zero resetting inputs of the stages p to v. In the logic circuit 5 the outlets Q and Q of the final stage w alternately open the NAND gates 20 and 21 each minute. Once in a minute the outlet Q of the stage v enables an impulse provided by the outlet Q of the stage j (f.sub.2) to reach the gates 20 and 21. This impulse will only pass the NAND gate 20 or 21 which has just opened at this instant to actuate the motor 7 in a manner which will be described hereunder.

The pilot stage 6 comprises two pairs of complimentary transistors T.sub.1, T.sub.2, and T.sub.3, T.sub.4, the emitters of T.sub.1 and T.sub.3 are connected to the terminal -V.sub.BB of the battery, the emitters of T.sub.2 and T.sub.4 are, themselves, connected to the terminal +V.sub.BB, the collectors of T.sub.1 and T.sub.2 are connected and form the terminal A of the motor 7 whilst the collectors of T.sub.3 and T.sub.4, likewise connected, form the terminal B of the motor 7. The outlet C of the logic circuit 5 feeds the base of T.sub.2 via a resistance R.sub.2 and the base of T.sub.3 via an inverter I.sub.2 and a resistance R.sub.3, whilst the outlet D of the logic circuit 5 feeds the base of T.sub.4 via a resistance R.sub.4 and the base of T.sub.1 via an inverter I.sub.1 and a resistance R.sub.1. In the example shown the timepiece does not give any indication of the seconds, the motor 7 only receives one impulse per minute. This impulse is of short duration (for example between 15 and 20 milliseconds, in the example under consideration this duration is of 15,625 ms). In the example of FIG. 2, the outlets C and D are in a logic state "1" corresponding to the voltage +V.sub.BB, the transistors T.sub.1, T.sub.2, T.sub.3 and T.sub.4 are blocked and no current at all can pass into the winding of the motor 7. A first drive impulse is released if, for example, the outlet C emits a negative impulse (logic level "0" corresponding to the voltage -V.sub.BB). In effect, during this impulse, the transistor T.sub.3 will open, shortcircuiting the terminal B to the terminal -V.sub.BB, the transistor T.sub.2 will likewise open and the terminal A will be short-circuited to the terminal +V.sub.BB. The current impulse will thus pass from A to B. One minute later, it is the turn of the outlet D to provide a negative impulse which will open the transistors T.sub.1 and T.sub.4 : the terminal B will then be found at the voltage +V.sub.BB and the terminal A at the voltage -V.sub.BB . The current will thus pass from B to A. The polarity of the drive impulses is thus reversed from one impulse to the other.

In FIG. 2 several trains of impulses f.sub.1, f.sub.2, f.sub.3, the frequencies of which differ are taken from the divider 4. These trains of impulses feed the inputs of a NAND gate 12. The output of this NAND gate 12 supplies a reading signal via an inverter 13 to one of the inputs of a second NAND gate 14. The complementary train of impulses of f.sub.1, thus f.sub.1 is taken to the terminal B of the motor 7 through a resistor R9. This frequency can then be measured at the terminal A or B of the motor 7. The train of impulses f.sub.1 then feeds the second input of the NAND gate 14. A switch 11 is placed between the feed terminal +V.sub.BB and the terminal A of the motor 7.

The diagram of FIG. 3 illustrates the functioning of FIG. 2. In normal functioning (to the left of the broken line F) the reading signal resulting from the conjunction of the impulses f.sub.1, f.sub.2, and f.sub.3 at the output of inverter 13 is shown which in Boolean algebra reads:

This signal does not pass the NAND gate 14 which is receiving the complimentary impulses f.sub.1 at its second input. As soon as the switch 11 (broken line F) is closed, the impulses from the reading signal f.sub.1 .multidot. f.sub.2 .multidot. f.sub.3 will pass the NAND gate 14 and furnish the impulse RES. These latter impulses RES, on the one hand via the inverter 15 will return the stages l, m, n, o and w, to zero, and on the other hand, via the NAND gates 16 and 17 will return the stages p to v to zero. These impulses RES permit moreover inhibition of the logic circuit 5 which will maintain its outlets C and D at potential "1" and no drive impulse will thereafter be supplied to the motor 7.

The diagram of FIG. 3 illustrates the functioning of the zero resetting. It can be seen that thanks to the inverter 13, the output of the NAND gate 14, during normal working, cannot deliver any return-to-zero signal RES. However, as soon as the switch 11 is closed, terminal A passes to the logic level "1" and the first impulse issued from the NAND gate 12 is transmitted to the stages of the divider 4. The broken line F indicates the instant at which the switch 11 closes. It is noted that the motor will restart one minute after the reopening of the switch 11.

It could happen that the switch 11 is closed during a drive impulse, that is to say when the terminal A is short circuited by the transistor T.sub.1 to the terminal -V.sub.BB. To avoid a short circuiting of the battery there can again be seen in FIG. 2 a protection device. This comprises the NPN transistor T.sub.5 the base of which is connected by a resistance R.sub.5 at the output of the inverter I.sub.1, its emitter is connected on the terminal -V.sub.BB and its collector is connected to the emitter of an NPN transistor T.sub.6 the base of which is connected, through a resistor R6 to the terminal A of the motor 7 and the collector of which goes to the collector of a PNP transistor T.sub.7 connected as a diode and the emitter of which is connected to the terminal +V.sub.BB. The base of the transistor T.sub.7 is connected to the base of a PNP transistor T.sub.8 the emitter of which is connected to the terminal +V.sub.BB and the collector of which is connected directly to the base of a NPN transistor T.sub.9 the collector of which is connected directly to the base of the transistor T.sub.1 and the emitter of which is connected to the terminal -V.sub.BB.

When the transistor T.sub.1 is saturated T.sub.5 is also saturated and the point A is at -V.sub.BB. If the switch 11 is closed, A passes very rapidly to +V.sub.BB and the battery discharges a large current. In this state, T.sub.6 conducts and the current of its collector is transmitted by the transistors T.sub.7 and T.sub.8 to the transistor T.sub.9 which becomes saturated and blocks T.sub.1. Thanks to this device the short circuit current only lasts a very short instant, equal to the turn on time of the transistors T.sub.6, T.sub.7, T.sub.8 and T.sub.9.

FIG. 4 illustrates another example of an embodiment with a single pole motor. Note likewise that the pilot stage of the motor 7 is composed of MOSFET transistors. The dividing chain 4 which, here, only comprises twenty-one stages a to u with a corrector 22 which permits dividing the frequency of the impulses at the output of the stage o (1 Hz) by 60. The correction impulse emanating from the outlet Q of the stage j every minute will pass the NAND gate 23, the reverse impulse can be used to control the motor 7. This will appear on the grid of the n-channel transistor T10 the source of which is connected to earth G and the drain of which is connected to the terminal E of the motor 7. The other terminal of the motor 7 is connected to the supply terminal +V.sub.BB. At each drive impulse, the transistor T10 will open and will allow current to pass into the motor 7. As in the preceding example, the switch 11 is arranged in parallel with the motor 7. The logic circuit 24 furnishes impulses f.sub.L, the frequency of which corresponds to that of the impulses f.sub.4 at the outlet Q of the stage n (2 Hz) and the length of which corresponds to that of the impulses provided at the outlet Q of the stage a. These positive impulses f.sub.L drive the gate of an n-channel transistor T11, the source of which is connected to earth G and the drain, of which is connected via a resistance R7 to the terminal E of the motor. The impulses f.sub.L will thus appear at the terminal E of the motor. However, since the value of the resistance R7 is made equal to the resistance of the coil of the motor 7, the height of the impulses f.sub.L at the terminal E of the motor will only be 1/2V.sub.BB. They are thus too small and too short to actuate the motor, but sufficient to be counted. The impulses f.sub.L also feed the invertor, formed by the n-channel transistor T12 and by the p-channel transistor T13, providing inverted f.sub.L pulses which drive the gate of a p-channel transistor T14, the source of which is connected to the feed terminal V.sub.BB and the drain of which is connected to the sources of two other p-channel transistors T15 and T16. The gates of the transistors T15 and T16, and the drain of the transistor T15 are connected to the terminal E of the motor 7 whilst the drain of the transistor T16 is connected via a resistance R8 to the earth G of the circuit.

There can be seen that, the switch 11 being open, the impulses f.sub.L will be transmitted to the drain of the transistor T16, thus will appear positive, on the resistance R8. When the switch 11 is closed, the transistors T15 and T16 are blocked and the voltage on the resistance R8 remains zero.

The drain of the transistor T16 is connected to the input S25 of an RS flip-flop 25, the output Q25 of which feeds one of the inputs of a NOR gate 30. On the other hand, two trains of impulses f.sub.4 and f.sub.5 drawn from the outputs Q of the stages n and m respectively, feed the two inputs of a NOR gate 26 the output of which feeds the input R25 of the RS flip-flop 25. The impulses f.sub.4 likewise feed directly one of the inputs of a NAND gate 27. The impulses f.sub.5 feed the second inlet of the NAND gate 27 via an inverter 28. The output of NAND gate 27 is connected to the second input of the NOR gate 30. The output of this gate 30 is, on the one hand, connected to the return-to-zero inputs RES of the stages k to o of the divider, and, on the other hand, via an inverter 29 to one of the inputs of the NAND gate 23 which the corrector circuit 22 is connected.

FIG. 5 illustrates the functioning of the return-to-zero impulses RES which appear at the output of the NOR gate 30 when the switch 11 is closed, the instant of its closing being indicated by the broken line F. From Boolean algebra, the output signal of the NAND gate 27 is written:

and the output signal of the NOR gate 26 is written:

Thus the signal f.sub.L is interrupted after the closing of the switch 11 which makes that the output Q25 of the flip-flop circuit 25 to remain at zero thus permitting the signal f.sub.4 + f.sub.5 to pass the NOR gate 30.

It is obvious that the choice of impulse trains f.sub.4 and f.sub.5 is not fundamental, and other impulse train combinations may be used to form the reading signal and, parting, the return-to-zero signal.