Electrically Driven Time Piece With Means for Effecting a Precise Setting of Time

The present invention concerns an electrically driven timepiece and in particular a timepiece provided with a highly accurate time standard, such as for example a quartz controlled oscillator.

Such timepieces have been widely publicized in recent years, particularly in view of their extraordinary precision which may run to an accumulated error of 1 minute or less per year. Where such timepieces are provided with a seconds indication either in the form of a seconds hand or an electro-optic digital seconds indication it is noted that users are irritated should the timepiece show even the slightest inaccuracy when compared for example with broadcast time signals. For this reason various means have been proposed for effecting seconds correction, particularly when the time is being reset for one reason or another.

It has already been proposed in timepieces provided with high frequency time standards and divider circuits to effect time setting electrically by switching a higher than normal frequency signal from the divider chain to the display arrangement. Thus for example a quartz oscillator normally having an output frequency of 32 768 Hz might have this frequency reduced to 1 Hz through a chain of dividers and the 1 Hz output of the final divider stage would then control the advance of the seconds display. If instead of utilizing the 1 Hz output, a higher frequency of, say 32 Hz, was employed it is clearly evident that time setting in respect at least of seconds and minutes could be considerably accelerated, since, in fact, the minutes display would be advanced by approximately one minute in every two seconds.

The problem of such an arrangement arises when it is desired to set the seconds display exactly in conformity with a standard time signal. As can be easily realized, with the seconds display advancing at such a rapid rate, it will be difficult for the user to stop the display at exactly the desired moment, particularly where seconds time signals may be forthcoming at 10 second intervals. It is therefore desirable to provide means by which the user, after having set the time display approximately, may then stop the display, wait for the next time signal and upon receipt of said time restart the display.

The invention accordingly provides an electrically driven timepiece wherein setting of the time display is accomplished through logic circuitry which enables changes to the information displayed to proceed more rapidly than normal and including an externally actuable switch associated with a ring counter which is arranged and adapted so as successively to switch the display to a more rapid drive rate, to stop the display and to return the display to a normal drive rate upon successive actuations of the switch.

For a better understanding of the invention reference will now be had to the drawings in which

FIG. 1 is an illustration of the basic logic circuit of the invention

FIG. 1A illustrates a NAND-gate along with its associated truth-table

FIG. 1B illustrates a NOR-gate with its associated truth-table

FIG. 1C illustrates a modification of the basic logic circuit of FIG. 1.

FIG. 2 is a timing diagram showing the operation of a simplified version of the invention in which an internal micro-switch is not utilized and

FIG. 3 is a timing diagram showing the operation utilizing all the elements of FIG. 1.

The upper portion of FIG. 1 shows a typical time-piece driving circuit including a crystal controlled oscillator 1, the frequency of which is reduced by means of a frequency divider 2. From the frequency divider various outputs are obtained, certain of which are eventually used to actuate a display means including a motor control unit 3, and in the version illustrated, a motor 4, which may be coupled through a conventional mechanism 8 to drive time indicating hands 9.

It should be clearly realized that although in the illustrated version a motor has been shown, nevertheless the invention is equally applicable to a timepiece utilizing an electro-optical type of display, either of the analogue or of the digital type. In such instance the motor 4 along with its control circuits would be replaced by storage registers and decoders.

It will be noted that output lines labeled f.sub.1, f.sub.2 in the drawing pass through a portion of the time setting control circuit on their way to the motor control unit 3. The standard output which has been designated to f.sub.1, may normally be at a frequency of 1 Hz and is passed via NAND-gates A.sub.2 and A.sub.3 to the motor control unit 3. Thus, in accordance, with the truth-table shown in FIG. 1A it is obvious that both these gates must have enabling high level 1-inputs in order to pass the signal f.sub.1. It follows that under normal operating conditions of the timepiece bistable flip-flops FF.sub.3 and FF.sub.4 will be in their cleared conditions so that a high level 1-output i is applied from flip-flop FF.sub. 4 to NAND-gate A.sub.2 whereas a low level O-output i is applied to NAND-gate A.sub.1 from bistable flip-flop FF.sub.4. It is equally clear that a high level 1-output h is applied to NAND-gate A.sub.3 from FF.sub.3. In view of the low level high input to NAND-gate A.sub.1, its output level will be maintained at the high level 1, whereby the output signal f.sub.1 is inverted twice on its way to the control unit 3. It will be noted that the signal f.sub.3 which may for example be at a frequency of 128 Hz is used to reset the control unit 3, thereby reducing the output pulse width and thereby the power consumption.

In a simplified embodiment of the invention, switch 6 is omitted and no connection is provided to the D input of bistable device FF.sub.2 which will at all times remain cleared whereby the output signal on Line d will remain at a high level 1. FIG. 2 illustrates the waveforms occuring on various leads in this embodiment, the waveforms of FIG. 2 being designated by the same reference characters as the lead shown in FIG. 1.

Consider now the sequence of events which follows actuation of push-button 5, which for example in the case of a watch might be incorporated into the crown, although other arrangements are certainly possible. Upon being actuated push-button 5 applies a high level signal to bistable device FF.sub.1. This high level signal results in the output labeled a going high as long as push-button 5 is actuated.

In view of what has already been said regarding flip-flop FF.sub.2, the output from NOR-gate A.sub.4 will be a low level 0. Until the moment at which flip-flop FF.sub.1 has been set by actuation of push-button 5, the output on line k from NOR-gate A.sub.5 will have been at a high level 1. Upon setting of flip-flop FF.sub.1 this changes to low level 0. Flip-flops FF.sub.3 and FF.sub.4 are of a type known in the art as JK flip-flops and are connected so as to form a cycle of three binary ring counter. Such arrangements are well-known to the prior art and in this respect reference may be had to the NV Philips publication "Electronic Applications," volume 28, No. 3, page 104. Thus the first application of a low level signal on the line k changes the state of flip-flop FF.sub.4 while leaving flip-flop FF.sub.3 in its original state. FIG. 2 illustrates this and shows more specifically that following the change of state of flip-flop FF.sub.4 NAND-gate A.sub.2 is blocked, NAND-gate A.sub.1 is enabled and NAND-gate A.sub.3 remains enabled. Thus in place of pulse train f.sub.1, pulse train f.sub.2 which may for example be at a frequency of 32 Hz, passes to the control unit 3, being inverted twice at A.sub.1 and A.sub.3 prior to its arrival. The display therefore will be advanced 32 times more quickly than under normal operation.

Should push-button 5 now be actuated a second time the same sequence of events will follow except that the second low level signal appearing on line k now has the effect that FF.sub.3 changes state whereby output h now is at a low level 0 whereby NAND-gate A.sub.3 is blocked. With NAND-gate A.sub.3 thus blocked neither of the pulse sequences f.sub.1 or f.sub.2 can pass therethrough hence the further advance of the display is stopped.

A slightly different embodiment is illustrated in FIG. 1c wherein the lead h is connected to a reset input on the frequency divider 2 rather than to aninput of NAND-gate A.sub.3. The effect is that blocking is accomplished at a reset input to the frequency divider rather than at NAND-gate A.sub.3 whereby a subsequent restarting operation will ensure that the display is restarted exactly one second following application of a restart signal. Should such a version be used then NAND-gate A.sub.3 may be replaced by a two input NAND-gate A.sub.3. Otherwise, the circuit of FIG. 1c operates in the same manner as the circuit of FIG. 1.

The user has thus effectively advanced the display of the timepiece to a desired point and has stopped the display whilst awaiting receipt of the standard time signal. Upon receipt of such standard time signal push-button 5 is once again actuated and once again a low going signal will appear on line k. The result of this is to restore flip-flops FF.sub.3 and FF.sub.4 to their original states as shown in FIG. 2 whereby initial conditions will once again be established and the display will receive the signal f.sub.1.

Through addition of a micro-switch 6 a more sophisticated version of the invention may be obtained and this will now be described with reference to FIGS. 1 and 3.

Micro-switch 6 may, in the case of an electro-mechanical motor driven display, be associated with the seconds axle. Such axle may be provided with a cam 7 which rotates normally once each minute. At a point on the cam, for instance corresponding to the 0-position of the seconds hand, the cam is adapted to actuate the micro-switch 6. Should an electro-optic type of display be utilized the cam and micro-switch 6 would be replaced by detecting means associated with the seconds display register which would produce a suitable signal whenever the register was returned to 0 for example. Should either of these correcting arrangements be desired for timepieces which do not display seconds, it is quite obvious that precisely the same principles may be applied for the setting of a minutes display or for that matter an hours display.

The functioning of the invention utilizing the auxiliary switch 6 is as follows. When push-button 5 is actuated by the user precisely the same sequence of events follows as described with reference to FIG. 1. That is to say, flip-flop FF.sub.4 changes state while flip-flop FF.sub.3 remains in its initial state. Thus the high frequency pulse train f.sub.2 is used to advance the display rapidly.

The advance of the display will in this second instance equally affect the cam 7 or alternately a display register in the event of an electro-optic type of display. The rotation of the cam, as shown, eventually closes switch 6 and applies setting signal c to flip-flop FF.sub.2. The normally high output Q is replaced by a low going output on line d. At this point it will be realized that output i and h are both low, whereby the output from NOR-gate A.sub.7 on line g will be high. Since at this time the signal on line k is likewise high the result is that output signal e from NAND-gate A.sub.6 is low. The effect of this is, upon the change of state of flip-flop FF.sub.2 brought about by micro-switch 6, to send a high going signal to NOR-gate A.sub.5 which results in a low going signal on line k. The effect of this low going signal is to advance the ring counter formed by flip-flops FF.sub.3 and FF.sub.4 just as had been effected in the earlier case by a second actuation of push-button 5. Here, however, the user maintains push-button 5 depressed as long as he wishes the time setting operation to proceed. He releases push-button 5 at approximately the moment when the objective is achieved and the display automatically stops at the next O-crossing.

To restart the display upon receipt of a time signal the user will then actuate once again the push-button and it will be realized that with a high level signal from line h applied to NOR-gate A.sub.7 the output on line g will be low level, whereby the output from NAND-gate A.sub.6 will be high level, whereby NOR-gate A.sub.4 is blocked. Thus the following actuation of switch 5 follows the same sequence as in the example initially described whereby flip-flops FF.sub.3 and FF.sub.4 are restored to their initial condition and the display proceeds normally.

It will be observed that flip-flops FF.sub.1 and FF.sub.2 are clocked by the signal f.sub.4. Signal f.sub.4 has not been illustrated in the timing diagrams of FIGS. 2 and 3, but its frequency will be chosen in order to provide signals as short as possible, but at the same time sufficiently long in duration to suppress the effects of parasitic type of signals generated by actuation of switches 5 or 6 in FIGS. 2 and 3, the waveforms I.M. represent advance pulses applied to the motor by the motor control unit 3 as the unit is alternately set and reset by the pulses n and f.sub.3.