Current Squaring Circuit

This invention relates to a current squaring circuit for producing an output current having a magnitude proportional to the square of the magnitude of the input current applied thereto.

There are known electric devices performing the function of electrically squaring an electrical quantity, such as wattmeters employing differential thermocouples, squaring circuits utilizing a broken line approximation, and analog multipliers, etc. In such electric devices, the input and output have a narrow effective range and the operating range over which the output has a relative error less than 1% is only one or two decades.

Accordingly it is an object of the present invention to eliminate the disadvantages of the prior art practice as above described by the provision of a current squaring circuit having an effective range of about three decades for the input and about six decades for the output while being operative at a frequency equal to or higher than 100 kilohertz with a relative error maintained at about 1% over the entire effective range.

It is another object of the present invention to provide a new and improved current squaring circuit capable of compensating for differences in characteristics between the transistors used.

The present invention provides a circuit for squaring a current, comprising, in combination, a first transistor of a first type conductivity having the emitter electrode maintained at a first predetermined fixed voltage and the base electrode and the collector electrode connected to each other and to a source of constant current, a second transistor of the first type conductivity having the collector electrode maintained at a second predetermined fixed voltage, and the base electrode connected to the base electrode of the first transistor, a third transistor of a second type conductivity having the emitter electrode connected to the emitter electrode of the second transistor and the base electrode and the collector electrode connected to each other and to one of a pair of input terminals for the input signal current, and a fourth transistor of the second type conductivity having the emitter electrode connected to the emitter electrode of the first transistor, the base electrode connected to the base electrode of the third transistor and the collector electrode connected to one of a pair of current output terminals for the output signal.

In a preferred embodiment of the present invention, the first and second transistors may be of the NPN type and the third and fourth transistors are of the PNP type or vice versa.

The present invention will become more readily apparent from the following detailed description taken in conjunction with the accompanying drawing wherein a single FIGURE illustrates a circuit diagram of one embodiment of the current squaring circuit of the present invention.

In the preferred embodiment of the present invention shown in the FIGURE, a first NPN type transistor Q.sub.1 has the emitter electrode connected to a reference potential through a first source of constant voltage S.sub.1, and the base and the collector electrode connected to each other and to the reference potential through a source of constant current A. A second NPN type transistor Q.sub.2 has the collector electrode connected to the reference potential through a second source of constant voltage S.sub.2, the base electrode connected to the base electrode of the first transistor Q.sub.1 and the emitter electrode connected to the emitter electrode of a third transistor Q.sub.3 of the PNP type which has the base and the collector electrode connected to each other and to terminal a one of a pair of input terminals for the input signal current with the other input terminal b connected to the reference or ground potential. The base electrode of the third transistor Q.sub.3 is connected to the base electrode of a fourth transistor Q.sub.4 of the PNP type which has the emitter electrode connected to both the emitter electrode of the first transistor Q.sub.1 and the first source of constant voltage S.sub.1 and the collector electrode connected to terminal c one of a pair of output terminals, for the output signal current. The other output terminal d is connected to the reference or ground potential.

In operation, the input signal current I.sub.in flows through the transistors Q.sub.2 and Q.sub.3 and the voltage developed at the collector electrode of the transistor Q.sub.3 is applied to the base electrode of the transistor Q.sub.4 to control the collector current thereof. This collector current provides the output signal current I.sub.out proportional to the square of the input signal current I.sub.in as will be subsequently described in detail.

The transistor Q.sub.1 serves to impart to the base electrode of the transistor Q.sub.2 a base voltage related to the voltage E.sub.1 of source S.sub.1 that is in turn adjusted by the magnitude of current from the source of constant current A.

It is now assumed that all the transistors Q.sub.1, Q.sub.2, Q.sub.3 and Q.sub.4 are identical in characteristics to one another and for a given collector current of I.sub.o, all the transistors have a common base-to-emitter voltage of V.sub.o. It is also assumed that the I.sub.o and V.sub.o are of 1 milliampere and 0.6 volt respectively.

As well known, the collector current I.sub.o of each transistor is expressed by ##EQU1## where V designates a base-to-emitter voltage, q an electric charge of an electron, k a Boltzmann's constant and T designates an absolute temperature.

Assuming that the source of constant current A produces an output current of I.sub.o (which is of 1 milliampere in this example) and each of the transistors has a direct current-amplification factor of .beta., the respective transistors have the following relationships between a voltage and a current:

The first transistor Q.sub.1 has a collector current I.sub.c1 = expressed by ##EQU2##

The second transistor Q.sub.2 has a collector current I.sub.c2 expressed by ##EQU3##

The third transistor Q.sub.3 has a collector current I.sub.c3 expressed by ##EQU4## and the fourth transistor Q.sub.4 has a collector current I.sub.c4 expressed by ##EQU5##

In the above equations V.sub.1, V.sub.2, V.sub.3 and V.sub.4 designate base-to-emitter voltages of the transistors Q.sub.1, Q.sub.2, Q.sub.3 and Q.sub.4 respectively.

Due to the connection of its base to its collector electrode, each of the transistors Q.sub.1 or Q.sub.3 has an emitter-to-collector voltage equal to a base-to-emitter voltage thereof. However the transistors Q.sub.2 and Q.sub.4 have emitter-to-collector voltages as determined by the sources of constant voltage S.sub.1 and S.sub.2 respectively. In order to render the emitter-to-collector voltages of the respective transistors substantially equal to one another, the sources S.sub.1 and S.sub.2 provide preferably output voltages E.sub.1 and E.sub.2 nearly equal to the V.sub.o and twice the V.sub.o respectively. By multiplying the equation (3) by the equation (4) and then dividing by the equation (2), there is given ##EQU6## substituting equation (3) into the above equations for I.sub.c2 yields ##EQU7##

Since the current-amplification factor .beta. has a value on the order of 100, .beta./(1+.beta.) has a value substantially equal to 1. Also if the input signal current I.sub.in has a maximum magnitude of 1 milliampere that is equal to the magnitude of I.sub.o then the equation (6) has a denominator I.sub.o - I.sub.in /(1+.beta.) substantially equal in magnitude to the I.sub.o. The total error resulting from the two approximations just described is on the order of 1%. With those approximations permissible, the equation (6) can be reduced to ##EQU8## The equation (7) describes that the output signal current I.sub.out is proportional to the square of the input signal current I.sub.in.

In the foregoing it has been assumed that all the transistors have a magnitude of the base-to-emitter voltage V.sub.o equal to one another for the collector current thereof having a predetermined common magnitude I.sub.o such as 1 milliampere. However transistors actually available are slightly different in base-to-emitter voltage from one to another. This means that the square characteristic represented by the equation (7) is attended with a factor having a value not equal to 1. Therefore it becomes necessary to adjust the gain obtained between the input and the output of the current squaring circuit. To this end, the arrangement illustrated can be provided with a means for adjusting the output current from the source of constant current A to control the emitter-to-collector V.sub.1 of the transistor Q.sub.1 thereby to compensate for the unequal V.sub.o 's.

In the FIGURE the transistors Q.sub.1 and Q.sub.2 are shown as being of the NPN type and the transistors Q.sub.3 and Q.sub.4 are shown as being of the PNP type, the selection of the transistors is facilitated by taking account of the fact that it is required only to impart a common magnitude of the voltage V.sub.o to the pair of transistors Q.sub.1 and Q.sub.2 while the other pair of transistors Q.sub.3 and Q.sub.4 has the same voltage V.sub.o. That is, since identical transistors can be used as a pair of transistors having the same type conductivity, transistors which are equal in the magnitude of the voltage V.sub.o to each other are readily be available.

The range of input signal current with which the circuit can retain the square characteristic has a lower limit as determined by the decrease in direct current-amplification factor due to the reduction in collector current of each of the transistors Q.sub.2 and Q.sub.3, the reverse saturation current flowing across the base and collector electrodes of the transistor Q.sub.4 etc. and an upper limit as determined by the increase in base current of each of the transistors Q.sub.2 and Q.sub.4, heat generated by the respective transistors etc. With high frequency silicon transistors for use with small signals properly selected as the transistors Q.sub.1 through Q.sub.4, it has been found that a signal range over which the square characteristic can be retained is about three decades with respect to the input and about six decades with respect to the output. For example, the input signal current I.sub.in typically ranges from 1 microampere to 1 milliampere and the output signal current I.sub.out ranges from 1 nano-ampere to 1 milliampere.

While the transistor Q.sub.4 which supplies the output signal current undergoes the greatest charge in current, a reduction in the direct current-amplification factor .beta. thereof in a low current range causes no error in the output signal current directly. Since the base current of the transistor Q.sub.4 is negligible with respect to the collector current of the transistor Q.sub.3 even in the region in which the base transistor current of transistor Q.sub.4 is not negligible with respect to the collector current thereof due to a decrease in the direct current-amplification factor .beta., the arrangement shown retains the square characteristic. This is because the collector current of the transistor Q.sub.4 decreases more sharply than the collector currents of the transistors Q.sub.2 and Q.sub.3 in the low current region. It has been found that, with the current amplification factor .beta. of the transistor Q.sub.4 decreased to 0.1, at an operating point having input and output signal currents of 1 microampere and 1 nano-ampere respectively this decrease in amplification factor actually imparts an error of about 2% to the square characteristic. A good frequency response exhibited in the low current region by the circuit of the present invention. For the same reason, the circuit has an upper frequency response limit equal to the frequency at which the alternating current-amplification factor decreases to the order of 0.1. This FIGURE permits an upper frequency response limit of 100 kiloherlz or more when small signal high frequency transistors are used.

Thus it can be seen that the present invention has provided a square characteristic circuit having a wide operational range previously not obtained with an extremely simple circuit configuration including a combination of one pair of NPN type transistors, another pair of PNP type transistors, a source of constant current and a pair of sources of constant voltage, the transistors in each pair having approximately the same characteristics. Therefore a present invention has the high utility value in the fields of the instrumentation, control, etc.

While the present invention has been illustrated and described in conjunction with a single preferred embodiment thereof it is to be understood that numerous changes and modifications may be resorted to without departing from the spirit and scope of the present invention. For example, the transistors along with the sources may be reversed in polarity from those illustrated.