Semiconductor package including stacked chips and method of manufacturing the semiconductor package

[0001] This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0102512, filed on Aug. 17, 2022 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

[0002] The present disclosure relates to a semiconductor package and, more specifically, to a semiconductor package including a plurality of stacked chips and a method of manufacturing the same.

[0003] In a bonding process of stacking a plurality of semiconductor chips, a space between the stacked semiconductor chips may be filled with a non-conductive film (NCF). When the non-conductive film is not sufficiently dispersed between the semiconductor chips, voids may occur in corner regions between the semiconductor chips. The voids may cause a pressing phenomenon in the corner regions, and thus, warpage may occur in the stacked semiconductor chips.

[0004] A semiconductor package includes a first semiconductor chip including a substrate having a first upper surface and a first lower surface opposite to the first upper surface. The substrate has a central region and corner regions around the central region. A plurality of through electrodes penetrates through the central region of the substrate. A bonding pad is electrically connected to the through electrode and has a first height from the first upper surface. A plurality of dummy pads respectively extend from the first upper surface on the corner regions of the substrate and having a second height that is higher than the first height. A second semiconductor chip has a second upper surface and a second lower surface opposite to the second upper surface. The second semiconductor chip is disposed on the first semiconductor chip via conductive bumps that are disposed on the second lower surface and are electrically connected to the bonding pads.

[0005] A semiconductor package includes a first semiconductor chip including a substrate having a first upper surface and a first lower surface opposite to the first upper surface. The substrate has a central region and edge regions around the central region. A plurality of through electrodes penetrate through the central region of the substrate. A bonding pad is electrically connected to the through electrode and has a first height from the first upper surface. A plurality of dummy pads respectively extend from the first upper surface on the edge regions of the substrate and having a second height that is higher than the first height. A second semiconductor chip has a second upper surface and a second lower surface opposite to the second upper surface. The second semiconductor chip is disposed on the first semiconductor chip via conductive bumps that are disposed on the second lower surface and are electrically connected to the bonding pads. An adhesive is configured to fill a space between the first and second semiconductors in the central region.

[0006] A semiconductor package includes a first semiconductor chip including a first substrate having a first upper surface and a first lower surface opposite to the first upper surface. A first through electrode extends through the first substrate in a vertical direction. A first bonding pad is disposed on the first through electrode and having a first height from the first upper surface. A plurality of first dummy pads respectively extends from the first upper surface and having a second height that is higher than the first height, in the vertical direction. A second semiconductor chip including a second substrate has a second upper surface and a second lower surface opposite to the second upper surface. A second through electrode extends through the second substrate in the vertical direction. A second bonding pad is disposed on the second through electrode and having a third height from the second upper surface. A second conductive bump is disposed on the second lower surface and is electrically connected to the first bonding pad. A plurality of second dummy pads respectively extend from the second upper surface and having a fourth height that is higher than the third height in the vertical direction. A third semiconductor chip has a third upper surface and a third lower surface opposite to the third upper surface. The third semiconductor chip is disposed on the second semiconductor chip through a third conductive bump disposed on the third lower surface and is electrically connected to the second bonding pad. An adhesive is configured to fill a space between the first to third semiconductors. The adhesive includes a non-conductive film (NCF) material.

[0007] A semiconductor package includes a first semiconductor chip including a substrate having a first upper surface and a first lower surface opposite to the first upper surface. The substrate has a central region and corner regions around the central region. A plurality of through electrodes pass through the central region of the substrate. A bonding pad electrically connects to the through electrode and has a first height from the first upper surface. A plurality of dummy pads respectively extend from the first upper surface on the corner regions of the substrate and having a second height that is higher than the first height. A second semiconductor chip has a second upper surface and a second lower surface opposite to the second upper surface. The second semiconductor chip is disposed on the first semiconductor chip through conductive bumps disposed on the second lower surface and is electrically connected to the bonding pads.

[0018] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

[0019] FIG. 1 is a plan view illustrating a semiconductor package in accordance with example embodiments. FIG. 2 is a cross-sectional view taken along the line A-A′ in FIG. 1. FIG. 3 is a cross-sectional view taken along the line B-B′ in FIG. 1. FIG. 4 is an enlarged cross-sectional view illustrating portion ‘C’ in FIG. 3. FIG. 5 is a plan view illustrating a first semiconductor chip in FIG. 3.

[0020] Referring to FIGS. 1 to 5, a semiconductor package 10 may include stacked semiconductor chips. The semiconductor package 10 may include stacked first to fourth semiconductor chips 100, 200, 300 and 400. The semiconductor package 10 may include an adhesive 500 filling a space between the stacked first to fourth semiconductor chips 100, 200, 300 and 400 and attaching them to each other.

[0021] The plurality of semiconductor chips 100, 200, 300, 400 may be vertically stacked. In this embodiment, the first to fourth semiconductor chips 100, 200, 300, 400 may be substantially the same as or similar to each other. Thus, same or similar components are denoted by the same or similar reference numerals, and to the extent that a description of such an element has been omitted, it may be understood that the element is at least similar to a corresponding element that has been described herein.

[0022] In this embodiment, it is exemplified that the semiconductor package as a multi-chip package includes four stacked semiconductor chips 100, 200, 300, 400. However, the present embodiment is not necessarily limited thereto, and for example, the semiconductor package may include 8, 12, or 16 stacked semiconductor chips.

[0023] Each of the first to fourth semiconductor chips 100, 200, 300, 400 may include an integrated circuit chip that is fabricated by performing semiconductor manufacturing processes. Each of the semiconductor chips may include, for example, a memory chip or a logic chip. The semiconductor package 10 may include a memory device. The memory device may include a high bandwidth memory (HBM) device.

[0024] Hereinafter, the first semiconductor chip 100 will be described first.

[0025] The first semiconductor chip 100 may include a first substrate 110 having a first upper surface 112 and a first lower surface 114 opposite to the first upper surface. A first connecting pad 120 is disposed on the first lower surface 114. A first bonding pad 130 is disposed on the first upper surface 112. A first conductive bump 140 is disposed on the first connecting pad 120. A first dummy pad 160 is disposed on the first upper surface 112. In addition, the first semiconductor chip 100 may further include a first through electrode 150 penetrating the first substrate 110 and a first protective layer 116 disposed on the first upper surface 112.

[0026] The first upper surface 112 of the first substrate 110 may be an inactive surface, and the first lower surface 114 may be an active surface. Circuit patterns may be disposed on the first lower surface 114 of the first substrate 110. The first lower surface 114 may be referred to as a front side surface on which the circuit patterns are formed, and the first upper surface 112 may be referred to as a backside surface.

[0027] The first substrate 110 may include a central region CA and an edge region EA at least partially surrounding the central region CA. The central region CA may be referred a region in which the first bonding pad 130, the first connecting pad 120, the first through electrode 150, and the first conductive bump 140 of the first semiconductor chip 100 are disposed.

[0028] For example, the first substrate 110 may include a semiconductor material such as silicon, germanium, or silicon-germanium. The first substrate 110 may include a III-V compound semiconductor such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), or the like. In some embodiments, the first substrate 110 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0029] The circuit patterns may include transistors, diodes, and the like. The circuit patterns may constitute circuit elements. Accordingly, the first semiconductor chip 100 may be a semiconductor device in which a plurality of circuit elements is formed.

[0030] In example embodiments, a first activation layer 118 may be disposed on the first lower surface 114 of the first substrate 110. The first activation layer 118 may include an insulating layer and a plurality of redistribution wirings disposed in the insulating layer. The redistribution wirings may be connected to one side of the first through electrode 150. The first connecting pad 120 may be connected to the redistribution wirings electrically connected to the first through electrode 150. The insulating layer may include silicon oxide, carbon-doped silicon oxide, silicon carbonitride (SiCN), or the like.

[0031] The first conductive bump 140 may be disposed on the first connecting pad 120. The first conductive bump 140 may provide an electrical movement path for electrically connecting the first semiconductor chip 100 to another semiconductor device. The first conductive bump 140 may mount the first semiconductor chip 100 on the other semiconductor device. For example, the first conductive bumps 140 may include micro bumps (μBump).

[0032] The first protective layer 116 may be disposed on the first upper surface 112 of the first substrate 110. The first protective layer 116 may be formed of an insulating material to protect the first substrate 110. The first protective layer 116 may be formed of an oxide film or a nitride film, or may be formed of a double layer of an oxide film and a nitride film. The first protective layer 116 may be formed of an oxide film, for example, a silicon oxide film (SiO₂) using a high-density plasma chemical vapor deposition (HDP-CVD) process.

[0033] The first bonding pad 130 may be formed on the first protective layer 116 and may be electrically connected to the first through electrode 150. The first bonding pad 130 may be electrically connected to the first through electrode 150 at the other side opposite to the one side of the first through electrode 150. The first bonding pad 130 may have a first height H1.

[0034] The first through electrode 150 may penetrate the first substrate 110 in a vertical direction. One end of the first through electrode 150 may be electrically connected to the redistribution wirings. The other end of the first through electrode 150 may be exposed to the first upper surface 112 of the first substrate 110. The first through electrode 150 may be electrically connected to the first bonding pad 130 through the other exposed end.

[0035] The first connecting pad 120, the first bonding pad 130, and the first through electrode 150 may include a same metal. For example, the metal may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and titanium (Ti). However, the present invention is not necessarily limited thereto, and may include a material capable of bonding by interdiffusion of metals by an annealing process at a high temperature.

[0036] In example embodiments, the second semiconductor chip 200 may include a second substrate 210, a second bonding pad 230 and a second dummy pad 260 disposed on a second upper surface 212 of the second substrate 210, a second connecting pad 220 disposed on a second lower surface 214 of the second substrate 210, and the second conductive bump 240 disposed on the second connecting pad 220. The second semiconductor chip 200 may further include a second through electrode 250 penetrating the second substrate 210 in the vertical direction and a second protective layer 216 disposed on the second upper surface 212. A second activation layer 218 may be disposed on the second lower surface 214 of the second substrate 210.

[0037] The second lower surface 214 of the second substrate 210 may face the first upper surface 112 of the first substrate 110. The second conductive bump 240 of the second semiconductor chip 200 may be directly bonded to the first bonding pad 130 of the first semiconductor chip 100. The second semiconductor chip 200 may be mounted on the first semiconductor chip 100 by a flip chip bonding method. The second connecting pad 220 of the second semiconductor chip 200 may be electrically connected to the first bonding pad 130 of the first semiconductor chip 100 by the second conductive bump 240. The second lower surface 214 may be referred to as a front side surface on which the circuit patterns are formed, and the second upper surface 212 may be referred to as a backside surface.

[0038] In example embodiments, the third semiconductor chip 300 may include a third substrate 310, a third bonding pad 330 and a third dummy pad 360 disposed on a third upper surface 312 of the third substrate 310, the third connecting pad 320 disposed on a third lower surface 314 of the third substrate 310, and the third conductive bump 340 disposed on the third connecting pad 320. The third lower surface 314 may be referred to as a front side surface on which the circuit patterns are formed, and the third upper surface 312 may be referred to as a backside surface. The third semiconductor chip 300 may further include a third through electrode 350 penetrating the third substrate 310 in the vertical direction and a third protective layer 316 disposed on the third upper surface 312. A third activation layer 318 may be disposed on the third lower surface 314 of the third substrate 310. The third semiconductor chip 300 may be mounted on the second semiconductor chip 200 by the flip chip bonding method.

[0039] The fourth semiconductor chip 400 may include a fourth substrate 410 and a fourth connecting pad 420 disposed on a fourth lower surface 414 of the fourth substrate 410. A fourth activation layer 418 may be disposed on the fourth lower surface 414 of the fourth substrate 410. The fourth lower surface 414 may be referred to as a front side surface on which the circuit patterns are formed, and the fourth upper surface 412 may be referred to as a backside surface. The fourth semiconductor chip 400 may include a fourth conductive bump 440 disposed on the fourth connecting pad 420. The fourth semiconductor chip 400 may be mounted on the third semiconductor chip 300 by the flip chip bonding method.

[0040] In example embodiments, the first semiconductor chip 100 may include a plurality of the first dummy pads 160 disposed on the first upper surface 112 of the first substrate 110. The first dummy pads 160 may support the second lower surface 214 of the second semiconductor chip 200 in a bonding process for connecting the first semiconductor chip 100 and the second semiconductor chip 200 to each other.

[0041] The first dummy pads 160 may respectively extend from the first upper surface 112 of the first substrate 110 in the vertical direction. The first dummy pad 160 may have a second height H2. The second height H2 of the first dummy pad 160 may be higher than the first height H1 of the first bonding pad 130. Since the second height H2 of the first dummy pad 160 is higher than the first height H1 of the first bonding pad 130, the first dummy pad 160 may support the second lower surface 214 of the second semiconductor chip 200 when the second semiconductor chip 200 is bent under force. For example, the second height H2 of the first dummy pad 160 may be within a range of 3 μm to 30 μm. A diameter D1 of the first dummy pad 160 may be within a range of 10 μm to 50 μm.

[0042] For example, the second height H2 of the first dummy pad 160 may be equal to the first distance L1 between the first upper surface 112 of the first semiconductor chip 100 and the second lower surface 214 of the second semiconductor chip 200. When the second height H2 and the first distance L1 are the same, the first dummy pad 160 may support the second lower surface 214 of the second semiconductor chip 200.

[0043] The first dummy pad 160 may include a cylindrical shape, a quadrilateral pole shape, an octagonal pole shape, or the like. The first dummy pad 160 may include a same material as the first connecting pad 120, the first bonding pad 130, and the first conductive bump 140. For example, the first dummy pad 160 may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and titanium (Ti).

[0044] As illustrated in FIG. 5, the first dummy pads 160 may be disposed in the edge region EA surrounding the central region CA on the first upper surface 112 of the first semiconductor chip 100. Since the second semiconductor chip 200 includes the second conductive bump 240 and the second through electrode 250 in the central region CA, the second semiconductor chip 200 may be bent in the vertical direction on the edge region EA where there is no supporting structure. The first dummy pads 160 may support the second lower surface 214 of the second semiconductor chip 200 in the edge region EA.

[0045] The first dummy pads 160 may be disposed in the first to fourth corner regions C1, C2, C3, C4 on the first upper surface 112 of the first semiconductor chip 100. The first to fourth corner regions may be disposed in vertex regions of the first semiconductor chip 100 in the edge region EA of the first semiconductor chip 100. The number of first dummy pads 160 disposed in each of the corner regions C1, C2, C3, C4 may be the same. For example, the number of the first dummy pads 160 disposed in each of the corner regions C1, C2, C3, C4 may be within a range of 10 to 100.

[0046] Arrangements of the first dummy pads 160 disposed in each of the corner regions C1, C2, C3, C4 may be symmetrical to each other. The first dummy pads 160 may uniformly distribute a force applied from the second lower surface 214 of the second semiconductor chip 200 through the symmetrical arrangement.

[0047] For example, the arrangement of the first dummy pads 160a in the first corner region C1 may be symmetrical with respect to the Y-axis with the first dummy pads 160b in the second corner region C2. The arrangement of the first dummy pads 160a in the first corner region C1 may be symmetrical with respect to the X-axis with the third dummy pads 160c in the third corner region C3. The arrangement of the first dummy pads 160b in the second corner region C2 may be symmetrical with respect to the X-axis with the first dummy pads 160d in the fourth corner region C4. The arrangement of the third dummy pads 160c in the third corner region C3 may be symmetric with respect to the Y-axis with the first dummy pads 160d in the fourth corner region C4.

[0048] Similarly, the second and third semiconductor chips 200, 300 may also include second and third dummy pads 260, 360 in the edge region of the upper surface, respectively.

[0049] In example embodiments, the second semiconductor chip 200 may include second dummy pads 260 formed on the edge regions of the second upper surface 212 of the second substrate 210. The second dummy pads 260 may support the third lower surface 314 of the third semiconductor chip 300 in a bonding process of connecting the second semiconductor chip 200 and the third semiconductor chip 300 mounted on the second semiconductor chip 200 to each other.

[0050] The second dummy pads 260 may be disposed between the third lower surface 314 of the third substrate 310 and the second upper surface 212 of the second substrate 210. The second dummy pads 260 may be disposed in the edge region EA surrounding the central region CA on the second upper surface 212 of the second semiconductor chip 200. For example, the second dummy pads 260 may be disposed on the same axis as the first dummy pads 160 in the vertical direction.

[0051] In example embodiments, the third semiconductor chip 300 may include third dummy pads 360 formed on the edge regions of the third upper surface 312 of the third substrate 310. The third dummy pads 360 may support the fourth lower surface 414 of the fourth semiconductor chip 400 in a bonding process of connecting the third semiconductor chip 300 and the fourth semiconductor chip 400 mounted on the third semiconductor chip 300 to each other.

[0052] The third dummy pads 360 may be disposed between the fourth lower surface 414 of the fourth substrate 410 and the third upper surface 312 of the third substrate 310. The third dummy pads 360 may be disposed in the edge region EA surrounding the central region CA on the third upper surface 312 of the third semiconductor chip 300. For example, the third dummy pads 360 may be disposed on the same axis as the second dummy pads 260 in the vertical direction.

[0053] In example embodiments, the semiconductor package 10 may further include an adhesive 500 for attaching the first to fourth semiconductor chips 100, 200, 300, 400 to each other. The adhesive 500 may fill spaces between the first to fourth semiconductor chips 100, 200, 300, 400. For example, the adhesive 500 may include a non-conductive film (NCF) material.

[0054] Since the adhesive 500 is dispersed from the central region CA to the edge region EA, the first to fourth corner regions C1, C2, C3, C4 might not be sufficiently coated. The first to fourth semiconductor chips 100, 200, 300, 400 might not be supported by the adhesive 500 in the uncoated first to fourth corner regions C1, C2, C3, C4. The first to third dummy pads 160, 260, 360 may support the second to fourth semiconductor chips 200, 300, 400 in the first to fourth corner regions C1, C2, C3, C4 so that the adhesive 500 does not spread.

[0055] In example embodiments, the semiconductor package 10 may further include a seal 600 covering the second, third, and fourth semiconductor chips 200, 300, 400 on the first semiconductor chip 100. The seal 600 may cover side surfaces of the second, third, and fourth semiconductor chips 200, 300, 400. The seal 600 may cover an upper surface of the fourth semiconductor chip 400. For example, the seal 600 may include a thermosetting resin or the like.

[0056] As described above, Since the second height H2 of the first dummy pad 160 is higher than the first height H1 of the first bonding pad 130 that electrically connects the first and second semiconductor chips 100, 200. The first dummy pads 160 may support between the first and second semiconductor chips 100, 200. Similarly, the second dummy pads 260 may support between the second and third semiconductor chips 200, 300, and the third dummy pads 360 may support between the third and fourth semiconductor chips 300, 400. As the first to third dummy pads 160, 260, 360 are disposed in corner regions C1, C2, C3, C4 between the first to fourth semiconductor chips 100, 200, 300, 400, the first to third dummy pads 160, 260, 360 may prevent the second and third semiconductor chips 200, 300 from a pressure generated in the corner regions C1, C2, C3, C4 that the non-conductive film (NCF) material cannot reach.

[0057] Hereinafter, a method of manufacturing the semiconductor package of FIG. 1 will be described.

[0058] FIGS. 6 to 24 are views illustrating a method of manufacturing a semiconductor package in accordance with example embodiments. FIG. 16 is a plan view illustrating a second wafer in FIG. 15. FIG. 20 is a plan view illustrating a stacked semiconductor package. FIG. 21 is a cross-sectional view taken along the line D-D′ in FIG. 20. FIG. 22 is a cross-sectional view taken along the line E-E′ in FIG. 20.

[0059] Referring to FIG. 6, first, a second wafer W2 on which a plurality of second semiconductor chips (dies) are formed may be prepared.

[0060] In example embodiments, the second wafer W2 may include a second substrate 210, a second through electrode 250 partially penetrating the second substrate 210, and a second connecting pad 220 disposed on the second through electrode 250.

[0061] For example, the second substrate 210 may include a semiconductor material such as silicon, germanium, or silicon-germanium. The second substrate 210 may include a III-V compound semiconductor such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), or the like. According to some embodiments, the second substrate 210 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0062] The second substrate 210 may have a second upper surface 212 and a second lower surface 214 opposite to the second upper surface 212. A second activation layer 218 may be disposed on the second lower surface 214 of the second substrate 210. The second activation layer 218 may include an insulating layer and a plurality of redistribution wirings disposed in the insulating layer. The redistribution wirings may be connected to one side of the second through electrode 250. Circuit patterns may be formed on the second activation layer 218.

[0063] The second substrate 210 may include a die region in which the circuit patterns and cells are formed and a scribe lane region surrounding the die region. The second substrate 210 may be individualized by cutting along the scribe lane region that separates the plurality of die regions of the second wafer W2 by a subsequent sawing process.

[0064] The circuit patterns may include transistors, capacitors, diodes, and the like. The circuit patterns may constitute circuit elements. Accordingly, the second semiconductor chip may be a semiconductor device having a plurality of circuit elements formed therein. The circuit patterns may be formed by performing a Front End of Line (FEOL) process for manufacturing the semiconductor device on the second lower surface 214 of the second substrate 210. A surface of the second substrate on which the FEOL process is performed may be referred to as a front side surface of the second substrate, and a surface opposite to the front surface may be referred to as a backside surface.

[0065] Referring to FIGS. 7 to 10, a second protective layer 216 may be formed on the second upper surface 212 of the second wafer W2.

[0066] As illustrated in FIGS. 7 and 8, the second upper surface 212 of the second substrate 210 may be polished using a substrate support system (WSS). After attaching the second wafer W2 on a carrier substrate CS through an adhesive film 20, the second upper surface 212 of the second substrate 210 may be removed until a portion of the second through electrode 250 is exposed.

[0067] The second upper surface 212 of the second substrate 210 may be partially removed by a grinding process such as a chemical mechanical polishing (CMP) process. Accordingly, a thickness of the second substrate 210 may be reduced to a desired thickness. One end of the second through electrode 250 may be exposed from the second upper surface 212 of the second substrate 210. The one end of the second through electrode 250 may protrude from the second upper surface 212 of the second substrate 210.

[0068] As illustrated in FIG. 9, a second protective layer 216 covering the second through electrode 250 protruding from the second upper surface 212 of the second substrate 210 may be formed.

[0069] As illustrated in FIG. 10, the second protective layer 216 may be polished. The second upper surface 212 of the second substrate 210 may be removed until a portion of the second through electrode 250 is exposed. The second protective layer 216 may be partially removed by the grinding process. One end of the second through electrode 250 may be exposed from the second protective layer 216.

[0070] Referring to FIGS. 11 to 16, second bonding pads 230 electrically connected to the second through electrode 250 on the second upper surface 212 of the second substrate 210, and a second dummy pad 260 may be formed.

[0071] As illustrated in FIG. 11, a photoresist layer 30 may be formed on the second upper surface 212 of the second wafer W2. The photoresist layer 30 may cover the second protective layer 216 and the one end of the second through electrode 250.

[0072] Then, as illustrated in FIG. 12, a photoresist pattern 32 having a first opening 34 exposing a second bonding pad region and a second opening 36 exposing a second dummy pad region may be formed by performing an exposure process on the photoresist layer 30. For example, a diameter of the second opening 36 may be within a range of 10 μm to 50 μm.

[0073] Then, as illustrated in FIG. 13, the second bonding pads 230 may be formed by a first plating process performed in the first opening 34 on the second protective layer 216. The first bonding pad 130 may have a first height H1 in the first opening 34. The first height H1 from the second upper surface 212 may be lower than an upper surface of the photoresist pattern 32.

[0074] Then, as illustrated in FIG. 14, the second dummy pads 260 may be formed by a second plating process performed in the second opening 36 on the second protective layer 216. The first dummy pad 160 may have a second height H2 in the second opening 36. The second height H2 of the first dummy pad 160 may be higher than the first height H1 of the second bonding pad 230. The first and second plating processes may include an electrolytic plating process or an electroless plating process.

[0075] For example, the second bonding pad 230 and the second dummy pad 260 may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and titanium (Ti).

[0076] As illustrated in FIGS. 15 and 16, the second bonding pad 230 and the second dummy pad 260 may be formed on the second upper surface 212 of the second substrate 210 by removing the photoresist pattern 32.

[0077] The second dummy pads 260 may be formed in an edge region EA surrounding a central region CA on the second upper surface 212 of the second substrate 210. The second dummy pads 260 may be formed in first to fourth corner regions C1, C2, C3, C4 on the second upper surface 212 of the second substrate 210. The first to fourth corner regions may be formed in vertex regions of the second substrate 210 in the edge region EA of the second substrate 210. An arrangement of the second dummy pads 260 disposed in each of the corner regions C1, C2, C3, C4 may be symmetrical with respect to each other.

[0078] Referring to FIG. 17, second conductive bumps 240 may be formed on the second connecting pads 220.

[0079] The second conductive bump 240 may be formed on the second connecting pad 220. For example, after filling a temporary opening of a photoresist pattern with a conductive material, the photoresist pattern may be removed and a reflow process may be performed to form the second conductive bump 240. For example, the conductive material may be formed by a plating process. Alternatively, the second conductive bump 240 may be formed by a screen printing method, a deposition method, or the like. For example, the second conductive bump 240 may include a C4 bump.

[0080] Referring to FIG. 18, the individual second semiconductor chip 200 may be formed by cutting the second wafer W2 along a scribe lane region. The second wafer W2 may be cut by a sawing process.

[0081] Referring to FIGS. 19 to 22, the second semiconductor chip 200 may be attached on a first wafer W1. A third semiconductor chip 300 manufactured through the same process as that of the second semiconductor chip 200 may be attached to the second semiconductor chip 200. A fourth semiconductor chip 400 may be attached on the third semiconductor chip 300. The second to fourth semiconductor chips 200, 300, 400 may be attached to the first wafer W1 through flip chip bonding.

[0082] In example embodiments, the second semiconductor chips 200 may be disposed on the first wafer W1 to correspond to the die regions. The second lower surface 214 of the second substrate 210 of the second semiconductor chip 200 may face the first wafer W1.

[0083] The second semiconductor chip 200 may be attached to the first upper surface 112 of the first wafer W1 by performing a thermal compression process at a predetermined temperature (e.g., about 400° C. or less). The second semiconductor chip 200 and the first wafer W1 may be bonded to each other by the thermal compression process. For example, the second conductive bumps 240 of the second semiconductor chip 200 may be respectively bonded to the first bonding pads 130 disposed on the first upper surface 112 of the first wafer W1. In the thermal compression process, an adhesive material 510a may be formed between the first wafer W1 and the second semiconductor chip 200. For example, the adhesive material 510 may include a non-conductive film (NCF) material.

[0084] Then, processes similar to those described with reference to FIGS. 6 to 18 may be performed to form third and fourth semiconductor chips 300, 400. The third and fourth semiconductor chips 300, 400 may be sequentially disposed on the second semiconductor chip 200. A front surface of the third semiconductor chip 300 may be stacked toward a rear surface of the second semiconductor chip 200. A front surface of the fourth semiconductor chip 400 may be stacked to face a rear surface of the third semiconductor chip 300. In the thermal compression process, the adhesive material 510b may be formed between the second and third semiconductor chips 200, 300.

[0085] The third semiconductor chip 300 and the second semiconductor chip 200 may be bonded to each other by the flip chip bonding by the thermal compression process. For example, the third conductive bumps 340 of the third semiconductor chip 300 may be directly bonded to the second bonding pads 230 of the second semiconductor chip 200.

[0086] Similarly, the fourth semiconductor chip 400 and the third semiconductor chip 300 may be bonded by the flip chip bonding by the thermal compression process. For example, the fourth conductive bumps 440 of the fourth semiconductor chip 400 may be directly bonded to the third bonding pads 330 of the third semiconductor chip 300. In the thermal compression process, the adhesive material 510c may be formed between the third and fourth semiconductor chips 300, 400.

[0087] It will be understood that the number of stacked semiconductor chips is not necessarily limited thereto. For example, 4, 8, or 12 semiconductor chips may be sequentially stacked on the fourth semiconductor chip 400.

[0088] As illustrated in FIGS. 20 to 22, the adhesive material 510b may be dispersed between the second and third semiconductor chips 200, 300 by the thermal compression process. The adhesive material 510b may be dispersed from the central region CA to the edge region EA on the second upper surface 212 of the second semiconductor chip 200.

[0089] Since the adhesive material 510b is dispersed from the central region CA to the edge region EA, the adhesive material 510b might not be sufficiently dispersed in the edge region EA. The adhesive material 510b might not be sufficiently dispersed in the first to fourth corner regions C1, C2, C3, C4 of the second semiconductor chip 200.

[0090] In the thermal compression process, the third semiconductor chip 300 may receive a force from the third upper surface 312. The adhesive material 510b disposed between the second and third semiconductor chips 200, 300 may support the force.

[0091] The second dummy pads 260 formed on the second upper surface 212 of the second semiconductor chip 200 may support the third lower surface 314 of the third semiconductor chip 300 in the edge region EA where the adhesive material 510b is not sufficiently dispersed. The second dummy pads 260 may support the third lower surface 314 of the third semiconductor chip 300 in the first to fourth corner regions C1, C2, C3, C4.

[0092] Similarly, the first dummy pads 160 formed on the first upper surface 112 of the first wafer W1 may support the second lower surface 214 of the second semiconductor chip 200 in the edge region EA where the adhesive material 510a is not sufficiently dispersed. The first dummy pads 160 may support the second lower surface 214 of the second semiconductor chip 200 in the first to fourth corner regions C1, C2, C3, C4.

[0093] The third dummy pads 360 formed on the third upper surface 312 of the third semiconductor chip 300 may support the fourth lower surface 414 of the fourth semiconductor chip 400 in the edge region EA where the adhesive material 510c is not sufficiently dispersed. The third dummy pads 360 may support the fourth lower surface 414 of the fourth semiconductor chip 400 in the first to fourth corner regions C1, C2, C3, C4.

[0094] Referring to FIG. 23, a seal 600 may be formed on stacked structures of the first wafer W1 and the second to fourth semiconductor chips 200, 300, 400.

[0095] In example embodiments, the seal 600 may be formed on the first wafer W1 to fill spaces between the second, third, and fourth semiconductor chips 200, 300, 400. The seal 600 may surround the second, third, and fourth semiconductor chips 200, 300, 400. The seal 600 may be formed by a dispensing process or a spin coating process. For example, the seal 600 may include a thermosetting resin or the like.

[0096] Referring to FIG. 24, the first wafer W1 and the seal 600 may be cut along the scribe lane region to form the semiconductor package in FIG. 1. The first wafer W1 and the seal 600 may be cut by a dicing process.

[0097] FIG. 25 is a plan view illustrating a semiconductor package including dummy pads having support pads in accordance with example embodiments. FIG. 26 is a cross-sectional view taken along the line F-F′ in FIG. 25. FIG. 27 is an enlarged cross-sectional view illustrating portion ‘G’ in FIG. 26. The semiconductor package may be substantially the same as or similar to the semiconductor package described with reference to FIGS. 1 to 5 except for a configuration of a dummy pad. Thus, same or similar components are denoted by the same or similar reference numerals, and to the extent that a description of such an element has been omitted, it may be understood that the element is at least similar to a corresponding element that has been described herein.

[0098] Referring to FIGS. 25 to 27, a semiconductor package 12 may include the first to fourth semiconductor chips 100, 200, 300, 400 and the adhesive 500.

[0099] The first semiconductor chip 100 of the semiconductor package 12 may include the first substrate 110 having the first upper surface 112 and the first lower surface 114 opposite to the first upper surface 112, the first connecting pad 120 disposed on the first lower surface 114, the first bonding pad 130 disposed on the first upper surface 112, the first conductive bump 140 disposed on the first connecting pad 120, and the first dummy pad 160 disposed on the first upper surface 112. Also, the first semiconductor chip 100 may include the first through electrode 150 penetrating the first substrate 110.

[0100] In example embodiments, the first dummy pad 160 may include a support bar 162 extending in the vertical direction from the first upper surface 112 and support pad 164 disposed on support bar 162.

[0101] The support bars 162 may respectively extend from the first upper surface 112 of the first substrate 110 in the vertical direction. The support bar 162 may have a second diameter D2 and a third height H3. The third height H3 of the support bar 162 may be higher than the first height H1 of the first bonding pad 130. Since the third height H3 of the support bar 162 is higher than the first height H1 of the first bonding pad 130, the support bar 162 may support the second lower surface 214 of the second semiconductor chip 200 when the second semiconductor chip 200 is bent under force. For example, the third height H3 of the support bar 162 may be within a range of 3 μm to 30 μm. The second diameter D2 of the support bar 162 may be within a range of 10 μm to 50 μm.

[0102] The support pad 164 may be disposed at one end of the support bar 162. The support pad 164 may have a third diameter D3. The third diameter D3 of the support pad 164 may be larger than the second diameter D2 of the support bar 162. For example, the third diameter D3 of the support pad 164 may be within a range of 15 μm to 70 μm.

[0103] Since the third diameter D3 of the support pad 164 is larger than the second diameter D2 of the support bar 162, the first dummy pads 160 may support the second lower surface 214 of the second semiconductor chip 200 with the larger area in a bonding process of connecting the first semiconductor chip 100 and the second semiconductor chip 200 mounted on the first semiconductor chip 100 to each other.

[0104] The foregoing is illustrative of example embodiments and is not to be construed as necessary limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in example embodiments without materially departing from the novel teachings and aspects of the present disclosure.