US 8,313,984 B2Grant
Die substrate with reinforcement structure
Issue Date:2012-11-20
•18 Claims
•10 Drawing Sheets
Abstract
Various semiconductor chip package substrates with reinforcement and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a package substrate that has a first side and a second side opposite to the first side. The first side has a central area adapted to receive a semiconductor chip. A solder reinforcement structure is formed on the first side of the package substrate outside of the central area to resist bending of the package substrate.
Metadata
Assignee
- ATI Technologies ULC
Inventors
- Roden Topacio
- Adam Zbrzezny
Application Information
Application Number:US 12/051,330
Filing Date:2008-03-19
Priority Date:2008-03-19
Art Unit:2891
Classifications
IPC:
H01L21/00H01L21/44
Patent Drawings (10 sheets)
Description
Background of the Invention
[0001] 1. Field of the Invention
[0002] This invention relates generally to semiconductor processing, and more particularly to semiconductor chip package substrates and methods of making the same.
[0003] 2. Description of the Related Art
[0004] Many current integrated circuits are formed as multiple dice on a common silicon wafer. After the basic process steps to form the circuits on the dice are complete, the individual dice are cut from the wafer. The cut dice are then usually mounted to structures, such as circuit boards, or packaged in some form of enclosure.
[0005] One frequently-used package consists of a substrate upon which a die is mounted. The upper surface of the substrate includes electrical interconnects. The die is manufactured with a plurality of bond pads. A collection of solder bumps are provided between the bond pads of the die and substrate interconnects to establish ohmic contact. An underfill material is deposited between the die and the substrate to act as a material that prevents damage to the solder bumps due to mismatches in the coefficients of thermal expansion between the die and the substrate, and an adhesive to hold the die. The substrate interconnects include an array of solder pads that are arranged to line up with the die solder bumps. After the die is seated on the substrate, a reflow process is performed to enable the solder bumps of the die to metallurgically bond to the solder pads of the substrate.
[0006] One conventional type of substrate consists of a core laminated between upper and lower build-up layers. The core itself usually consists of four layers of glass filled epoxy. The build-up layers, which may number four or more on opposite sides of the core, are formed from some type of resin. Various metallization structures are interspersed in the core and build-up layers in order to provide electrical pathways between pins, pads or other solder balls on the lowermost layer of the substrate and the pads that bond with the chip solder bumps. The pins, pads or solder balls are designed to electrically interface with a pin grid array socket, a land grid array socket or a ball grid array land pattern of another electrical device, such as a printed circuit board.
[0007] The core provides a certain stiffness to the substrate. Even with that provided stiffness, conventional substrates still tend to warp due to mismatches in coefficients of thermal expansion for the chip, underfill and substrate. However, there is a need to provide shorter electrical pathways in package substrates in order to lower power supply inductance and improve power fidelity for power transferred through the substrate. The difficult problem is how to reduce the electrical pathways without inducing potentially damaging substrate warping.
[0008] One conventional technique for shoring up the stiffness of a chip package substrate involves the mounting of a stiffener ring to an upper side of the package substrate. These types of conventional stiffeners are frequently fabricated from copper, aluminum or steel and require an adhesive to adhere to the substrate.
[0009] The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
Summary of the Invention
[0010] In accordance with one aspect of the present invention, a method of manufacturing is provided that includes providing a package substrate that has a first side and a second side opposite to the first side. The first side has a central area adapted to receive a semiconductor chip. A solder reinforcement structure is formed on the first side of the package substrate outside of the central area to resist bending of the package substrate.
[0011] In accordance with another aspect of the present invention, a method of manufacturing is provided that includes providing a package substrate that has a first side and a second side opposite to the first side. The first side has a central area adapted to receive a semiconductor chip. A solder-wettable surface is formed on the first side outside the central area. A solder mask is formed on the first side of the package substrate while leaving at least a portion of the solder-wettable surface exposed. Solder is deposited on the solder-wettable surface to form a reinforcement structure on the first side of the package substrate to resist bending of the package substrate.
[0012] In accordance with another aspect of the present invention, an apparatus is provided that includes a package substrate that has a first side and a second side opposite to the first side. The first side has a central area adapted to receive a semiconductor chip. A solder reinforcement structure is on the first side of the package substrate outside of the central area to resist bending of the package substrate.
Brief Description of the Drawings
[0013] The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:
[0014] FIG. 1 is a pictorial view of an exemplary conventional semiconductor chip package that includes a semiconductor chip mounted on a substrate;
[0015] FIG. 2 is a sectional view of FIG. 1 taken at section 2-2;
[0016] FIG. 3 is a sectional view like FIG. 2 depicting a mounting of the conventional semiconductor chip package to a printed circuit board;
[0017] FIG. 4 is a magnified view of a small portion of FIG. 3 ;
[0018] FIG. 5 is a magnified view like FIG. 4 depicting the aftermath of a solder reflow;
[0019] FIG. 6 is a pictorial view of an exemplary embodiment of a semiconductor chip package that includes a substrate reinforcement structure;
[0020] FIG. 7 is a pictorial view of an exemplary package substrate prior to solder mask formation;
[0021] FIG. 8 is a pictorial view of the substrate of FIG. 7 following solder mask formation;
[0022] FIG. 9 is a pictorial view like FIG. 8 depicting solder application;
[0023] FIG. 10 is a sectional view of FIG. 9 taken at section 10-10;
[0024] FIG. 11 is a sectional view like FIG. 10 depicting stencil removal;
[0025] FIG. 12 is a sectional view like FIG. 11 depicting a mounting of a semiconductor chip to the substrate;
[0026] FIG. 13 is a sectional view like FIG. 12 depicting a mounting of the semiconductor chip package to a printed circuit board;
[0027] FIG. 14 is a plan view of an alternate exemplary embodiment of a semiconductor chip package substrate that includes a reinforcement member;
[0028] FIG. 15 is a plan view of another alternate exemplary embodiment of a semiconductor chip package substrate that includes a reinforcement member;
[0029] FIG. 16 is a plan view of an exemplary embodiment of a solder stencil;
[0030] FIG. 17 is a pictorial view of an exemplary embodiment of a semiconductor chip package coupled to another electronic device; and
[0031] FIG. 18 is a partially exploded pictorial of another exemplary embodiment of a semiconductor chip package that includes a substrate reinforcement structure.
Detailed Description of Specific Embodiments
[0032] In the drawings described below, reference numerals are generally repeated where identical elements appear in more than one figure. Turning now to the drawings, and in particular to FIG. 1 , therein is shown a pictorial view of an exemplary conventional semiconductor chip package 10 that includes a semiconductor chip 15 mounted on a substrate 20. The substrate 20 is depicted as a ball grid array and thus includes a plurality of solder balls 25 that are destined for metallurgical connection to a printed circuit board (not shown). A few passive devices 30a, 30b, 30c, 30d, 30e and 30f, such as capacitors, are depicted on an upper surface 35 of the substrate 20. The chip 15 is flip-chip mounted to the substrate 20 and electrically connected thereto by way of a plurality of solder bumps which are not visible in FIG. 1 , but will be in subsequent figures.
[0033] Note that FIG. 1 depicts a problem that may arise with conventional semiconductor chip package substrates, namely, the downward bending or warping of the substrate 20 and in particular at the corners 40, 45, 50 and 55 thereof. The physical mechanisms that lead to such downward warping will be described in conjunction with subsequent figures. Attention is now turned to FIG. 2 , which is a sectional view of the chip package 10 of FIG. 1 taken at section 2-2. Note that because of the location of section 2-2, only the passive devices 30c and 30e and the corners 45 and 55 of the substrate 20 are visible in FIG. 2 . As mentioned briefly above, the semiconductor chip 15 is electrically and mechanically connected to the substrate 20 by way of a plurality of solder bumps 60. The bumps 60 are electrically connected to the balls 25 of the substrate 20 by conductors incorporated into the substrate 20 that are not visible. An underfill material layer 65 is deposited beneath the chip 15 and on the upper surface 30 of the substrate 20 to address issues of differing coefficients of thermal expansion between the chip 15 and the substrate 20. Much of the warpage of the substrate 20 and in particular at the corners 45 and 55 thereof, is caused by the mechanical forces imposed on the substrate 20 at the time that the solder bumps 60 beneath the chip 15 are reflowed and the underfill material layer 65 is thermally cured.
[0034] Product yield issues that may arise as a result of the warpage of the substrate 20 can come into play when it is time to mount the substrate 20 and in particular the solder balls 25 thereof to another structure such as a printed circuit board land pattern. Attention is now turned to FIG. 3 , which is a sectional view like FIG. 2 , but depicts the semiconductor chip package 10 positioned slightly above a printed circuit board 70 that includes an upwardly facing land pattern 75. During the mounting procedure, the substrate 20 is seated on the land pattern 75 such that the solder balls 25 of the substrate contact corresponding ball pads of the land pattern 75, two of which are labeled 80 and 85. A reflow process is then performed to establish metallurgical connections between the balls 25 and the pads 80 and 85.
[0035] The warping of the substrate 20 can cause a variety of spatial misalignments associated with the balls 25 and the pads 80 and 85 that can lead to poor mounting outcomes. The effects can be better visualized by focusing on a small portion of the package 10 circumscribed by the oval 90. One of the solder balls within the oval 90 is separately labeled 95. The portion circumscribed by the oval 90 is shown at greater magnification in FIG. 4 .
[0036] Attention is now turned to FIG. 4 . Note that a small portion of the land pattern 75 and the underlying printed circuit board 70 are visible as well as the ball pads 80 and 85 and the solder balls 25 and 95 of the substrate 20. Several potential undesirable outcomes are depicted. To begin with, the lateral alignment between the solder ball 95 and the underlying target ball pad 85 is misaligned as a result of the warping of the substrate 20. The warping has also caused the pitch P1 between the solder balls 25 and 95 to be smaller than a design pitch between the balls 25 and 95 if the substrate 20 were not warped. The fallout of this smaller than desired ball pitch will be depicted and described in conjunction with the next figure. In addition, the ball 25 of the substrate 20 may be elevated above the respective target ball pad 80, which may or may not lead to adhesion problems during a subsequent reflow of the solder balls 25 and 95.
[0037] FIG. 5 is a magnified sectional view like FIG. 4 , but depicts the aftermath of a solder reflow process to establish metallurgical connections between the solder balls 25 and 95 and the underlying target ball pads 80 and 85 of the land pattern 75. Because the pre-reflow pitch P1 (see FIG. 4 ) is smaller than planned due to the warping of the substrate 20, the balls 25 and 95 have merged during reflow to produce a highly undesirable and yield limiting short circuit situation. Whether the substrate 20 can be subsequently lifted from the printed circuit board 70 and successfully refurbished or must be consigned to scrap is an open question.
[0038] FIG. 6 depicts a pictorial view of an exemplary embodiment of a semiconductor chip package 100 that alleviates some of the deficiencies of the aforementioned conventional semiconductor chip package 10. The package 100 includes a substrate 115 designed to have a semiconductor chip or die 120 mounted thereon or multiple chips if desired. The chip 120 may be any of a myriad of different types of circuit devices used in electronics, such as, for example, microprocessors, graphics processors, combined microprocessor/graphics processors, application specific integrated circuits, memory devices or the like, and may be single or multi-core. An underfill material layer 125 may be positioned beneath the chip 120 to lessen the effects of differential coefficients of thermal expansion between the chip 120 and the substrate 115.
[0039] The substrate 115 may consist of a core/build-up configuration. In this regard, the substrate 115 may consist of a central core upon which one or more build-up layers are formed and below which an additional one or more build-up layers are formed. The core itself may consist of a stack of one or more layers. One example of such an arrangement may be termed a so called “2-4-2” arrangement where a four-layer core laminated between two sets of two build-up layers. The number of layers in the substrate 115 can vary from four to sixteen or more, although less than four may be used. So-called “coreless” designs may be used as well. The layers of the substrate 115 consist of an insulating material, such as various well-known epoxies, interspersed with metal interconnects.
[0040] To interface with other electronic devices, the substrate 115 may be configured as a ball grid array as shown or some other type of substrate interconnection scheme. A plurality of solder balls 130 are coupled to the substrate 115. The semiconductor chip 120 may be flip-chip mounted to the substrate 115. A plurality of electrical interconnects are not visible but are incorporated into the substrate 115 in order to establish electrical interconnections between the chip 120 and the plurality of solder balls 130.
[0041] Note that a solder mask 135 is formed on an upper surface of the substrate 115. A plurality of passive devices, which may be capacitors, inductors or other electronic components, are mounted to the solder mask 135 with solder structures that are not visible due to the scale of FIG. 6 , but will be visible in subsequent figures. Just a few of the passive devices are shown and labeled 140a, 140b, 140c, 140d and 140e, respectively. Like the chip 120, the passive devices 140a, 140b, 140c, 140d and 140e are electrically interconnected with other components of the package 100 by way of a plurality of conductors which are not visible in FIG. 6 . To counteract the potential for substrate warpage, such as that depicted in FIGS. 1-5 , the substrate 115 of this exemplary embodiment is provided with a reinforcement structure that consists of four reinforcement members 145a, 145b, 145c and 145d designed to resist the downward warping of the corners 147a, 147b, 147c and 147d of the substrate 115. Note that the reinforcement member 145c is shown exploded from the solder mask 135 to reveal its structure. The reinforcement member 145c is metallurgically connected to an underlying solder-wettable surface that consists of a conductor pad 150c that is formed in the substrate 115 in this embodiment. Similar pads that make up the remainder of the solder-wettable surface are positioned in the substrate 115 beneath the reinforcement members 145a, 145b and 145d but are not visible in FIG. 6 .
[0042] In this illustrative embodiment, the reinforcement members 145a, 145b, 145c and 145d are patterned as elbow-shaped members. The reinforcement members 145a, 145b, 145c and 145d are advantageously composed of solder that may be the same type of solder used to fabricate other structures in the substrate 115 as described more fully below. In this way, the reinforcement members 145a, 145b, 145c and 145d may be fabricated without the requirement of additional process steps or the provision of separate reinforcement rings of the type described in the Background section hereof.
[0043] An exemplary method of fabricating the reinforcement members 145a, 145b, 145c and 145d depicted in FIG. 6 may be understood by referring now to FIGS. 7 , 8, 9, 10 and 11 and initially to FIG. 7 , which is a pictorial view of the substrate 115 prior to application of the solder mask 135 (see FIG. 6 ) thereto. The conductor pad 150c that was partially obscured by the solder mask 135 in FIG. 6 is now visible along with three other conductor pads 150a, 150b and 150d. The conductor pads 150a, 150b, 150c and 150d are positioned outside of a central area 151 of a side 152 of the substrate 115. An opposite side 153 of the substrate 115 is designed to receive the solder balls 130 depicted in FIG. 6 . The central area 151 includes an array 154 of bump pads that are designed to be electrically connected to the semiconductor chip 120 shown in FIG. 6 during subsequent processing. The conductor pad 150c and three other conductor pads 150a, 150b and 150d are slated to receive the reinforcement members 145a, 145b, 145c and 145d depicted in FIG. 6 . In addition, the substrate 115 includes component pads 155a, 155b, 155c, 155d and 155e that are designed to electrically connect to the passive devices 140a, 140b, 140c, 140d and 140e depicted in FIG. 6 by way of solder portions that fill various openings in the solder mask 135 depicted in FIG. 6 . As noted above, there are a plurality of interconnects in the substrate 115 that connect various elements electrically. A few of these interconnects or traces 160 are depicted connected to the component pad 155e and one such trace 165 is depicted connected to the conductor pad 150b. However, just a few of the conductor traces are depicted for simplicity of illustration. The skilled artisan will appreciate that there may be large numbers of such conductors in the substrate 115 including in various layers thereof. The various traces 160 and 165 may be tied to ground, or some other potential level.
[0044] The conductor pads 150a, 150b, 150c and 150d are fabricated on the substrate 115 with preselected shapes or patterns that are designed to match the desired shapes for the subsequently formed reinforcement members (145a, 145b, 145c and 145d in FIG. 6 ). Well-known techniques for forming conductor pads on chip substrates may be used such as electroplating or other plating techniques and followed by lithographic masking and well-known etch processes. The same material deposition and lithographic patterning and etching process may be done to fabricate the component pads 155a, 155b, 155c, 155d and 155e as well. Exemplary materials for the pads 150a, 150b, 150c and 150d and 155a, 155b, 155c, 155d and 155e include copper, silver, gold, platinum, palladium, combinations of these or the like.
[0045] As shown in FIG. 8 , the solder mask 135 is formed on the substrate 115 and provided with a plurality of openings 170a, 170b, 170c and 170d that correspond to the desired positions and shapes of the subsequently formed reinforcement members 145a, 145b, 145c and 145d shown in FIG. 6 . In addition, the solder mask 135 is provided with openings 175a, 175b, 175c, 175d and 175e proximate the positions of the underlying component pads 155a, 155b, 155c, 155d and 155e shown in FIG. 7 . Finally, an array 177 of openings is provided in vertical alignment with the array 154 of bump pads shown in FIG. 7 . The array 177 of openings is filled with solder that will bond with the semiconductor chip 120 shown in FIG. 6 during subsequent processing. The solder mask 135 may be fabricated from a variety of suitable materials for solder mask fabrication, such as, for example, PSR-4000 AUS703 manufactured by Taiyo Ink Mfg. Co., Ltd. or SR7000 manufactured by Hitachi Chemical Co., Ltd. The openings 170a, 170b, 170c and 170d, 175a, 175b, 175c, 175d and 175e and the array 177 of openings may be formed by well-known lithographic masking and etching. As is evident from FIG. 8 , the openings 170a, 170b, 170c and 170d are etched down to the underlying solder-wettable surface consisting of the conductor pads 150a, 150b, 150c and 150d. In order to properly wet, at least some of the pads 150a, 150b, 150c and 150d must be exposed. With the openings 170a, 170b, 170c and 170d and 175a, 175b, 175c, 175d and 175e formed, the solder mask 135 is ready for solder deposition.
[0046] Attention is now turned to FIG. 9 , which depicts the application of solder 180 through a stencil 185 that is patterned with a plurality of openings 190a, 190b, 190c and 190d that are designed to match the size and shape and position of the underlying openings 170a, 170b, 170c and 170d and another plurality of openings 195a, 195b, 195c, 195d and 195e that are designed to match the size and shape and position of the underlying openings 175a, 175b, 175c, 175d and 175e (not visible in FIG. 9 but visible in FIG. 8 ) of the solder mask 135. The solder 180 may be deposited in paste form on the solder stencil 185 by an applicator 200 of one sort or another and the stencil 185 thereafter swiped to compress the solder 180 into the openings 190a, 190b, 190c and 190d and 195a, 195b, 195c, 195d and 195e. The stencil 185 may be composed of well-known metals, plastics or ceramics. The solder may be lead-based or lead-free. Examples of suitable lead-free solders include tin-silver, tin-copper, tin-silver-copper or the like.
[0047] The interaction of the stencil 185, the solder mask 135 and the substrate 115 during the deposition process may be understood by referring now to FIG. 10 , which is a sectional view of FIG. 9 taken at section 10-10. Note that because of the location of section 10-10, a portion of the opening 190d, the opening 170d will be visible as well as the openings 195d and 175d and a portion of the openings 190c and 175c will be visible. As the solder 180 is deposited into the openings 170d and 190d, solder 180 will contact the underlying pad 150b and extend vertically almost to the upper surface 202 of the stencil 185. The same will be true for solder 180 deposited on the pads 155d and 150a in the remaining openings 175d/195d and 170c/190c.
[0048] After solder deposition, the stencil 185 is removed to leave the now formed solder reinforcement members 145d and 145c and a solder portion 180 projecting slightly above the solder mask 135 as shown in FIG. 11 . The reinforcement member 145d in the opening 170d is in contact with the underlying conductor pad 150d, the portion of solder 180 in the opening 175d is in contact with the underlying component pad 155d and the reinforcement member 145c in the opening 170c is in contact with the underlying conductor pad 150c. At this stage, the substrate 115 and the solder mask 135 are ready for the mounting of passive devices and the semiconductor chip. Note that portions of the reinforcement members 145c and 145d extend onto an upper surface 203 of the solder mask 135. The amount of solder that extends over the surface 203 may be increased as desired by widening the openings 190c and 190d in the stencil 185 shown in FIG. 10 to allow for a greater volume of solder to be applied.
[0049] Attention is now turned to FIG. 12 , which is a sectional view like FIG. 11 , but shows the mounting of the passive device 140d to the solder 180 in the opening 175d of the solder mask 135. Of course it should be understood that the other passive devices 140a, 140b, 140c and 140d depicted in FIG. 6 may be mounted to the substrate 115 at this time as well. The semiconductor chip 120 may be mounted to the substrate 115 in flip-chip fashion by way of a plurality of solder bumps 205 affixed to the chip 120 and a reflow process may be performed in order to temporarily liquify the solder bumps 205 and the solder structure 180 that connects to the passive device 140d. The reflow process will produce a transient melting of the reinforcement members 145d and 145c (as well as the remaining reinforcement members 145a and 145b (see FIG. 6 ). As the substrate 115 cools to below the melting point of the reinforcement members 145d and 145c and back to room temperature, the reinforcement members 145c and 145d shown in FIGS. 6 and 12 and the members 145a and 145b shown in FIG. 6 will contract faster than the substrate 115. This contraction will have a tendency to pull the corners 147a, 147b, 147c and 147d (see FIG. 6 ) of the substrate 115 upward and thereby resist the downward warping depicted in FIGS. 1-5 .
[0050] Following the reflow and cool down for the attachment of the chip 120 and the passive device 140d, the plural solder balls 130 may be applied to the substrate 115 as depicted in FIG. 13 . At this stage, the package 100 may be mounted to a printed circuit board 210 by way of the ball grid array of solder balls 130 or other mechanism if another style of interconnect is used. Another solder reflow is performed to temporarily melt the solder balls 130. During this reflow, any room temperature warpage of the substrate 115 will tend to relax or flatten. During this thermal cycle, the reinforcement members 145c and 145d (and the members 145a and 145b shown in FIG. 6 ) will also melt and thus not add any warping forces to the substrate 115.
[0051] In the foregoing illustrative embodiment, the reinforcement structure consists of four uniform perimeter reinforcement members. However, the skilled artisan will appreciate that a variety of geometries may be used for reinforcing the substrate. FIG. 14 depicts an alternate exemplary embodiment of a semiconductor chip package 100′ that includes a substrate upon which the semiconductor chip 120 is mounted and a reinforcement structure that consists of four reinforcement members 145a′, 145b′, 145c′ and 145d′. In this illustrative embodiment, a given reinforcement member, such as the reinforcement member 145a′ is configured generally as an elbow-like structure, albeit with a pair of cutouts 215 and 220 that are designed to expose additional portions of the corner 147a′ of the substrate 115′. The other reinforcement members 145b′, 145c′ and 145d′ may have a similar geometry as shown. The cutouts 210 and 215 provide additional space on the substrate 115′ to facilitate the placement of the substrate 115′ in various jigs or pick and place machines that may be useful for performing various process steps on the substrate 115′. The reinforcement members 145b′, 145c′ and 145d′ may be fabricated using the same general techniques disclosed elsewhere herein. Of course, a solder-wettable surface (not visible) that is akin to the conductor pads 150a, 150b, 150c and 150d shown in FIG. 7 is provided on the substrate 115′ to which the reinforcement members 145a′, 145b′, 145c′ and 145d′ bond.
[0052] Another alternate exemplary embodiment of a semiconductor chip package 100″ is depicted as an overhead view in FIG. 15 . In this illustrative embodiment, the package 100″ includes a substrate 115″ that is designed to receive the semiconductor chip 120. In this illustrative embodiment, a reinforcement structure 145a″ consists of a reinforcement ring that may extend around the entire perimeter of the substrate 115″. The respective corners 225a, 225b, 225c and 225d of the reinforcement structure 145a″ may have cut out shapes like the reinforcement member 145a′ depicted in FIG. 14 . Of course, a solder-wettable surface (not visible) that is akin to, but perhaps more extensive than, the conductor pads 150a, 150b, 150c and 150d shown in FIG. 7 is provided on the substrate 115″ to which the reinforcement member 145a″ bonds. The reinforcement member 145a″ may be fabricated using the same general techniques disclosed elsewhere herein. However, another type of stencil design that is suited to fashioning solder into a continuous ring may be used. A plan view of such an exemplary stencil 230 is shown in FIG. 16 . The stencil 230 is provided with four sets 235a, 235b, 235c and 235d of corner slot openings and four sets 237a, 237b, 237c and 237d of edge slot openings. Each of the sets 235a, 235b, 235c, 235d, 237a, 237b, 237c and 237d includes several slots, one of which is labeled 240. During initial stenciling, solder will be pressed through and take on the shape of the sets 235a, 235b, 235c, 235d, 237a, 237b, 237c and 237d of slots 240. During a subsequent reflow, the melted solder segments will merge together to form the reinforcement member 145a″ shown in FIG. 15 . Without the slots 240, a central portion 245 of the stencil 230 would have to be supported by some other mechanism.
[0053] Any of the illustrative embodiments of the chip packages disclosed herein may be mounted in another electronic device. In this regard, FIG. 17 shows an exemplary electronic device 250 that may be a computer, a digital television, a handheld mobile device, a personal computer, a server, a memory device, an add-in board such as a graphics card, or any other computing device employing semiconductors. The semiconductor chip package 100 may be attached to the device 250 to provide a desired functionality.
[0054] In the foregoing illustrative embodiments, reinforcement structures are positioned on one side of a substrate. However, the skilled artisan will appreciate that it is possible to configure a semiconductor chip package with reinforcement structures on both sides of the package substrate. In this regard, attention is now turned to FIG. 18 , which is a partially exploded pictorial of a semiconductor chip package 260 that consists of the package substrate 115, and the solder mask 135 upon which a semiconductor chip 120 is positioned. The combination of the substrate 115, the solder mask 135 and the chip 120 may be configured essentially as described elsewhere herein in conjunction with the package 100. In this illustrative embodiment, a second solder mask 265 may be coupled to the under side 267 of the substrate 115. The solder mask 265 may be patterned with a set of openings 270a, 270b, 270c and 270d that are sized and spaced to receive a corresponding plurality of solder reinforcement structures 275a, 275b, 275c and 275d. The openings 270a, 270b, 270c and 270d and the solder structures 275a, 275b, 275c and 275d may be formed and materially similar to the structures that make up the solder mask 135 and the reinforcement structures 145a, 145b, 145c and 145d. The mask 265 may be provided with a grid array of openings 280 that are designed to accommodate interconnection with a ball grid array 285 that is shown exploded downward from the solder mask 265. There may be additional solder material or other conductor materials to establish electrical interconnection between the solder balls 285 and underlying conductor structures of the substrate 115 that are not visible in FIG. 18 . Again, it should be understood that the shapes, number and configuration of the reinforcement structures 145a, 145b, 145c and 145d and 275a, 275b, 275c and 275d may be varied or unified as described generally herein.
[0055] Any of the exemplary embodiments disclosed herein may be embodied in instructions disposed in a computer readable medium, such as, for example, semiconductor, magnetic disk optical disk or other storage medium or as a computer data signal. The instructions or software may be capable of synthesizing and/or simulating the circuit structures disclosed herein. In an exemplary embodiment, an electronic design automation program, such as Cadence APD, Encore or the like, may be used to synthesize the disclosed circuit structures. The resulting code may be used to fabricate the disclosed circuit structures.
[0056] While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
Claims
What is claimed is:
1. A method of manufacturing, comprising:
providing a package substrate having a first side and a second side opposite to the first side, the first side having a central area adapted to receive a semiconductor chip; and
forming a solder reinforcement structure on the first side of the package substrate outside of the central area to resist bending of the package substrate.
2. The method of claim 1, wherein the package substrate comprises four corners, the forming a solder reinforcement structure comprises forming a solder reinforcement member proximate each of the four corners.
3. The method of claim 1, wherein the forming a solder reinforcement structure comprises forming a solder mask on the first side of the package substrate with a plurality of openings and depositing solder into the plurality of openings.
4. The method of claim 3, comprising placing a stencil on the solder mask, depositing the solder through the stencil and removing the stencil.
5. The method of claim 1, wherein the forming a solder reinforcement structure comprises forming a solder ring.
6. The method of claim 1, comprising coupling a semiconductor chip to the first side of the package substrate.
7. The method of claim 6, comprising coupling the package substrate to an electronic device.
8. The method of claim 1, wherein the method is performed by executing instructions stored in a computer readable medium.
9. A method of manufacturing, comprising:
applying a first portion of solder and second portion of solder to a side of a package substrate, the side having an edge and a central area adapted to receive a semiconductor chip; and
whereby the first portion is adapted to receive a passive component and the second portion is positioned nearer the edge than the first portion and adapted to reinforce and resist bending of the package substrate.
10. The method of claim 9, comprising mounting a passive component on the first portion.
11. The method of claim 9, wherein the second portion comprises a ring.
12. The method of claim 9, wherein the applying the first and second portions of solder comprises forming a solder mask on the first side of the package substrate with a plurality of openings and depositing the first portion into at least one of the plurality of openings and the second portion into at least one of the plurality of openings.
13. The method of claim 12, comprising placing a stencil on the solder mask, depositing the first and second portions of solder in paste form through the stencil and removing the stencil.
14. A method of manufacturing, comprising:
applying a first portion of solder and second portion of solder to a side of a package substrate, the side having four corners and a central area adapted to receive a semiconductor chip; and
whereby the first portion is adapted to receive a passive component and the second portion includes a solder structure proximate each of the four corners, the solder structures being nearer to the corners than to the central area, the second portion adapted to reinforce and resist bending of the package substrate.
15. The method of claim 14, comprising mounting a passive component on the first portion.
16. The method of claim 14, wherein the solder structures comprises elbow structures.
17. The method of claim 14, wherein the applying the first and second portions of solder comprises forming a solder mask on the first side of the package substrate with a plurality of openings and depositing the first portion into at least one of the plurality of openings and the second portion into at least four of the plurality of openings.
18. The method of claim 17, comprising placing a stencil on the solder mask, depositing the first and second portions of solder in paste form through the stencil and removing the stencil.
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