US 10,418,331 B2Grant
Interconnection structures and methods for transfer-printed integrated circuit elements with improved interconnection alignment tolerance
Issue Date:2019-09-17
•12 Claims
•20 Drawing Sheets
Abstract
An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed.
Metadata
Assignee
- X-Celeprint Limited
Inventor
- Christopher Bower
Application Information
Application Number:US 15/863,164
Filing Date:2018-01-05
Priority Date:2010-11-23
Art Unit:2826
Classifications
IPC:
H01L29/10H01L23/538H01L21/683H01L23/00H01L21/66
Field of Search:
H01L 23/538H01L 23/5382H01L 23/5383H01L 23/5387H01L 24/03H01L 24/04H01L 24/27H01L 24/28H01L 24/29H01L 2224/8012H01L 23/5389H01L 21/6835H01L 24/19H01L 24/20H01L 24/82H01L 24/83
Patent Drawings (20 sheets)
Description
Claim of Priority
[0001] This application is a division of U.S. patent application Ser. No. 13/302,497, entitled Interconnection Structures and Methods for Transfer-Printed Integrated Circuit Elements with Improved Interconnection Alignment Tolerance, filed on Nov. 22, 2011, which claims priority under 35 U.S.C. § 119(e) from U.S. Provisional Patent Application Ser. No. 61/416,527 entitled Interconnection Structure and Method for Transfer-Printed Integrated Circuits, filed with the United States Patent and Trademark Office on Nov. 23, 2010, the disclosure of which is incorporated by reference herein in its entirety.
Field of the Invention
[0002] The present invention relates to integrated circuit device fabrication, and more particularly, to apparatus and methods for assembling integrated circuit elements on a substrate.
Background of the Invention
[0003] Large substrates with electronically active components distributed over the extent of the substrate are used in a variety of electronic systems, for example imaging devices such as flat-panel liquid crystal or OLED display devices and in digital radiographic plates. Large substrates with electrically active components are also found in flat-panel solar cells.
[0004] The electronically active components on flat-panel substrates are typically formed by sputtering a layer of inorganic semiconductor material or by spin-coating a layer of organic semiconductor material over the entire substrate and processing the layer to form electronic components. However, such coatings typically may have relatively poor electronic characteristics. Inorganic semiconductor materials can be processed to improve their electronic characteristics; for example, amorphous silicon can be heat-treated to form polycrystalline silicon. In other processes, microcrystalline semiconductor layers can be formed by using an underlying seeding layer. These methods typically improve the electron mobility of the semiconductor, but the performance of the resulting layer may still be worse than is often desired or needed.
[0005] The substrate and layer of semiconductor material can be photo-lithographically processed to define electronically active components, such as transistors. Such transistors are known as thin-film transistors (TFTs) since they are formed in a thin layer of semiconductor material, typically silicon. The photo-lithographic processing typically requires high-resolution mask steps to pattern the semiconductor materials and metal interconnections on the substrate. In these devices, the substrate is often made of glass, for example, Corning Eagle® or Jade® glass designed for display applications.
[0006] However, these conventional thin-film techniques may have limitations. Despite processing methods used to improve the performance of thin-film transistors, such transistors may have a performance lower than the performance of conventional integrated circuits formed in mono-crystalline semiconductor material. Also, semiconductor material and active components may be used on only portions of the substrate, leading to wasted material and increased material and processing costs. The substrate materials may be limited by the processing steps that may be necessary to process the semiconductor material, as well as the photo-lithographic steps used to pattern the active components. For example, plastic substrates have a limited chemical and heat tolerance and typically do not readily survive photo-lithographic processing. Furthermore, the manufacturing equipment used to process large substrates with thin-film circuitry may require relatively high resolution and may be expensive.
[0007] In another manufacturing technique, a mono-crystalline semiconductor wafer may be employed as the substrate. While this approach can provide substrates with similar performance as integrated circuits, the size of such substrates may be limited, for example, to a 12-inch diameter circle, and the wafers are relatively expensive compared to other substrate materials such as glass or polymer.
[0008] In yet another approach, thin layers of semiconductor may be bonded to a substrate and then processed. Such a method is known as semiconductor-on-glass or silicon-on-glass (SOG) and is described, for example, in U.S. Patent Application Publication No. 2008/0224254, published Sep. 18, 2008. If the semiconductor material is crystalline, high-performance thin-film circuits can be obtained. However, the bonding technique can be expensive and the high-resolution processing equipment needed to form thin-film active components on large substrates may be expensive.
[0009] It is also known to provide relatively large integrated circuits in surface mountable packages that are directly adhered to a substrate. However, these integrated circuits are relatively large and additional layers may not be easily formed over the integrated circuits. Furthermore, electrical inter-connections to the surface-mountable package may require high-resolution patterning.
[0010] Publication number 11-142878 of the Patent Abstracts of Japan entitled “Formation of Display Transistor Array Panel” describes etching a substrate to remove it from a thin-film transistor array on which the TFT array was formed. TFT circuits formed on a first substrate can be transferred to a second substrate by adhering the first substrate and the TFTs to the surface of the second substrate and then etching away the first substrate, leaving the TFTs bonded to the second substrate. This method typically requires etching a significant quantity of material and risks damaging the exposed TFT array. Also, as with the other techniques discussed above, the patterned processing may require expensive, high-resolution equipment.
[0011] Another method of locating material on a substrate is described in U.S. Pat. No. 7,127,810. In this method, a first substrate carries a thin-film object to be transferred to a second substrate. An adhesive is applied to the object to be transferred or to the second substrate in the desired location of the object. The substrates are aligned and brought into contact. A laser beam irradiates the object to abrade the transferring thin film so that the transferring thin film adheres to the second substrate. The first and second substrates are separated, peeling the film in the abraded areas from the first substrate and transferring it to the second substrate. In one embodiment, a plurality of objects may be selectively transferred by employing a plurality of laser beams to abrade selected areas. Objects to be transferred can include thin-film circuits. Further processing, for example to provide electrical interconnections between the transferred objects, may require high-resolution processing.
[0012] U.S. Pat. No. 6,969,624 describes a method of transferring a device from a first substrate onto a holding substrate by selectively irradiating an interface with an energy beam. The interface is located between a device for transfer and the first substrate and includes a material that generates ablation upon irradiation, thereby releasing the device from the substrate. For example, a light-emitting device (LED) can be made of a nitride semiconductor on a sapphire substrate. The energy beam is directed to the interface between the sapphire substrate and the LED nitride semiconductor releasing the LED and allowing the LED to adhere to a holding substrate coated with an adhesive. The adhesive is then cured. These methods, however, may require the patterned deposition of adhesive on the object(s) or on the second substrate. Moreover, the laser beam that irradiates the object may be shaped to match the shape of the object and the laser abrasion can damage the object to be transferred. Furthermore, the adhesive cure takes time, which may reduce the throughput of the manufacturing system. Further processing, for example to provide electrical interconnections between the transferred objects, may also require high-resolution processing.
[0013] In another method for transferring active components from one substrate to another, described in “AMOLED Displays using Transfer-Printed Integrated Circuits” published in the Proceedings of the 2009 Society for Information Display International Symposium Jun. 2-5, 2009, in San Antonio, Tex., US, vol. 40, Book 2, ISSN 0009-0966X, paper 63.2 p. 947, small integrated circuits (chiplets) with connection pads formed on the chiplet surface are formed in a wafer and released from the wafer by etching beneath the circuits. A PDMS stamp is pressed against the wafer and the circuits adhered to the stamp. The circuits are then pressed against a substrate coated with an adhesive, adhered to the substrate, and the adhesive is subsequently cured. Subsequent photo-lithographic processes are used to form electrical wires over the substrate and on to the connection pads. However, the position and orientation of the chiplets resulting from the printing process can vary somewhat. Thus, the connection pads may need to be relatively large so that the wires formed by the photo-lithographic processing steps contact the contact pads. The relatively large connection pads can reduce the space available for circuits and circuit connections, and thus can reduce the functionality of the chiplets.
Summary of the Invention
[0014] According to some embodiments of the present invention, integrated circuit elements are provided on a receiving substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof, where the connection pad and the conductor element are electrically separated. At least one of the integrated circuit elements is misaligned on the receiving substrate relative to a desired position thereon such that the at least one of the integrated circuit elements is positioned on the receiving substrate at a distance from the desired position that is greater than or equal to a distance between the conductor element and the connection pad. A conductive layer is formed on the receiving substrate including the integrated circuit elements thereon such that the connection pad of each of the integrated circuit elements is electrically connected to the conductive layer.
[0015] In some embodiments, each of the integrated circuit elements may include an insulating layer on the chiplet substrate that exposes at least a portion of the connection pad to the conductive layer and covers the conductor element on the surface of each chiplet substrate to electrically separate or isolate the conductor element from the conductive layer.
[0016] In some embodiments, a planarization layer may be formed on the receiving substrate including the integrated circuit elements thereon. The planarization layer may include via openings therein, where respective positions of the via openings in the planarization layer may be based on respective desired positions of the integrated circuit elements on the receiving substrate. The conductive layer may be formed on the planarization layer and in the via openings to electrically contact the connection pad of each of the integrated circuit elements.
[0017] In some embodiments, at least one of the via openings has a diameter or other dimension sufficient to expose a portion of the connection pad and a portion of the insulating layer covering the conductor element of the at least one of the integrated circuit elements that is misaligned on the receiving substrate. For example, the dimension of the at least one of the via openings may be greater than the distance between the conductor element and the connection pad on the surface of the chiplet substrate.
[0018] In some embodiments, the connection pad of each of the integrated circuit elements may be coupled to an active element therein such that the conductive layer provides an electrical connection between respective active elements of each chiplet substrate, and the conductor element of each of the integrated circuit elements may provide an electrical connection between respective active elements of a same chiplet substrate.
[0019] In some embodiments, each chiplet substrate may include a plurality of connection pads and a plurality of conductor elements, and at least one of the conductor elements may be provided between adjacent ones of the connection pads on the surface of each chiplet substrate.
[0020] In some embodiments, the integrated circuit elements including a plurality of active elements therein may be formed on a source substrate. The integrated circuit elements may be transferred from the source substrate to the receiving substrate such that the at least one of the integrated circuit elements is misaligned on the receiving substrate relative to the desired position.
[0021] In some embodiments, the source substrate may include a sacrificial layer thereon between the integrated circuit elements and the source substrate. The integrated circuit elements may be transferred by separating the integrated circuit elements from one another on the source substrate to define tethers attaching the integrated circuit elements to respective anchor areas on the source substrate, and etching the sacrificial layer to release the integrated circuit elements from the source substrate without releasing the anchor areas therefrom.
[0022] In some embodiments, the integrated circuit elements may be transferred by pressing a stamp against the source substrate to break the tethers attaching the integrated circuit elements to the respective anchor areas, retracting the stamp from the source substrate such that the integrated circuit elements are adhered to the stamp, pressing the stamp including the integrated circuit elements thereon against the receiving substrate, and retracting the stamp from the receiving substrate to delaminate the integrated circuit elements therefrom and such that the at least one of the integrated circuit elements is misaligned on the receiving substrate relative to the desired position.
[0023] In some embodiments, a protective layer may be formed on the integrated circuit elements prior to separating and/or etching. The protective layer may include a silicon dioxide layer and an amorphous silicon layer thereon.
[0024] According to further embodiments of the present invention, an electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon at a distance from the desired position that is greater than or equal to a distance between the conductor element and the connection pad. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires.
[0025] In some embodiments, a planarization layer including via openings therein may be provided on the backplane substrate including the integrated circuit elements thereon. The conductive wires may respectively extend into the corresponding via openings to electrically contact the connection pad of each of the integrated circuit elements.
[0026] In some embodiments, respective positions of the via openings in the planarization layer may be based on respective desired positions of the integrated circuit elements on the backplane substrate. At least one of the via openings may expose a portion of the connection pad and a portion of the insulating layer covering the conductor element of the at least one of the integrated circuit element that is misaligned on the receiving substrate.
[0027] In some embodiments, the exposed portion of the connection pad may be smaller than a dimension of the at least one via opening.
[0028] In some embodiments, an adhesive layer may be provided between each of the chiplet substrates and the backplane substrate. The adhesive layer adheres each of the chiplet substrates to the backplane substrate.
[0029] In some embodiments, the connection pad of each of the integrated circuit elements may be coupled to an active element therein, and the conductive wires may provide an electrical connection between respective active elements of each chiplet substrate. Also, in some embodiments, the conductor element of each of the integrated circuit elements may provide an electrical connection between respective active elements of a same chiplet substrate.
[0030] In some embodiments, each chiplet substrate may include a plurality of connection pads and a plurality of conductor elements on the surface thereof. At least one of the conductor elements may be provided between adjacent ones of the connection pads on the surface of each chiplet substrate.
[0031] In some embodiments, the integrated circuit elements may be transfer-printed elements.
[0032] In some embodiments, the conductor element and the connection pad on each chiplet substrate may be portions of a same metal layer.
[0033] According to still further embodiments of the present invention, a substrate for printing transferrable integrated circuit chiplets includes a patterned sacrificial layer on the substrate, and a plurality of integrated circuit chiplets on the patterned sacrificial layer. Each of the integrated circuit chiplets includes a separate chiplet substrate detached from the substrate by a pattern of the sacrificial layer, active elements on or in the chiplet substrate, a connection pad on a surface of the chiplet substrate, chiplet wires on or in the chiplet substrate electrically connecting the active elements and the connection pad, a conductor electrically separate from the connection pad on the surface of the chiplet substrate, where the conductor is electrically connected to a chiplet wire or one of the active elements, and an insulating layer on the chiplet substrate and the conductor, where the insulating layer leaves at least a portion of the connection pad exposed.
[0034] In some embodiments, one or more test pads, a plurality of electrically conductive tethers, and anchors may be provided on the substrate. Each anchor may be located over and in contact with the patterned sacrificial layer and having a tether connecting the anchor to one of the integrated circuit chiplets. The tether may electrically connect active elements in the one of the integrated circuit chiplets to one or more exposed electrical test pads in the anchor.
[0035] According to yet further embodiments of the present invention, a method of fabricating transferrable integrated circuit chiplets includes providing a substrate, forming a sacrificial layer on the substrate, forming a chiplet substrate layer on the sacrificial layer, forming active elements on or in the chiplet substrate layer, forming a connection pad on a surface of the chiplet substrate layer, forming chiplet wires on or in the chiplet substrate electrically connecting the active elements and the connection pad, forming a conductor electrically separate from the connection pad on the surface of the chiplet substrate layer, where the conductor is electrically connected to a chiplet wire or active element, forming an insulating layer over the chiplet substrate and the conductor, leaving at least a portion of the connection pad exposed, and patterning the chiplet substrate layer and the sacrificial layer to form separate chiplet substrates detached from the substrate.
[0036] In some embodiments, a protective layer may be formed on the insulating layer and the connection pad. The protective layer may be a bi-layer, and each layer of the bi-layer may include a different material. For example, the protective bi-layer may include a silicon dioxide layer and an amorphous silicon layer.
[0037] According to yet other embodiments of the present invention, a backplane includes a backplane substrate and a plurality of integrated circuits located on the backplane substrate. Each integrated circuit includes a separate chiplet substrate having a surface, active elements formed on or in the chiplet substrate, a connection pad formed on the surface of the chiplet substrate, chiplet wires formed on or in the chiplet substrate electrically connecting the active elements and the connection pad, a conductor electrically separate from the connection pad formed on the surface of the chiplet substrate, the conductor electrically connected to a chiplet wire or active element, and an insulating layer formed over the chiplet substrate and the conductor, leaving at least a portion of the connection pad exposed. Electrically conductive wires are formed in a single layer over the backplane substrate, where the connection pad of each of the plurality of integrated circuits is connected to an electrically conductive wire.
[0038] According to still yet other embodiments of the present invention, a method of making a backplane having integrated circuits includes providing a backplane substrate, and providing a plurality of integrated circuits located on the backplane substrate. Each integrated circuit includes a separate chiplet substrate having a surface, active elements formed on or in the chiplet substrate, a connection pad formed on the surface of the chiplet substrate, chiplet wires formed on or in the chiplet substrate electrically connecting the active elements and the connection pad, a conductor electrically separate from the connection pad formed on the surface of the chiplet substrate and electrically connected to a chiplet wire or active element, and an insulating layer formed over the chiplet substrate and the conductor, leaving at least a portion of the connection pad exposed. The integrated circuits are located on the backplane substrate, and electrically conductive wires are formed in a single layer over the backplane substrate. The connection pad of each of the plurality of integrated circuits is connected to an electrically conductive wire.
[0039] Other methods and/or devices according to some embodiments will become apparent to one with skill in the art upon review of the following drawings and detailed description. It is intended that all such additional embodiments, in addition to any and all combinations of the above embodiments, be included within this description, be within the scope of the invention, and be protected by the accompanying claims.
[0040] Embodiments of the present invention provide advantages such as improved electrical performance and density in integrated circuits transfer-printed over large substrates. Embodiments of the invention also reduce the number of large-area photolithographic steps, reduce alignment tolerance requirements, and are compatible with wafer testing and a high-yield release process for the transfer-printed integrated circuits.
Brief Description of the Drawings
[0041] FIG. 1A is a cross section illustrating an integrated circuit according to some embodiments of the present invention;
[0042] FIG. 1B is a cross section illustrating a backplane arrangement including integrated circuits thereon according to some embodiments of the present invention;
[0043] FIG. 1C is a cross section illustrating a backplane having integrated circuits according to some embodiments of the present invention;
[0044] FIG. 2 is a cross section of a chiplet according to some embodiments of the present invention;
[0045] FIGS. 3A-3P are cross sections illustrating sequential stages in the fabrication and application of chiplets to a backplane according to some embodiments of the present invention;
[0046] FIGS. 4A-4C are cross sections illustrating misalignment of a chiplet having a large connection pad on a backplane;
[0047] FIGS. 5A-5C are cross sections illustrating misalignment of a chiplet having small connection pads on a backplane;
[0048] FIGS. 6A-6C are cross sections illustrating a chiplet on a backplane according to some embodiments of the present invention that addresses the misalignment illustrated in FIGS. 5A-5C ;
[0049] FIG. 7 is a perspective of a wafer having chiplets according to some embodiments of the present invention;
[0050] FIG. 8 is a perspective of a backplane having chiplets and wires according to some embodiments of the present invention;
[0051] FIG. 9 is a flowchart illustrating methods of fabricating a chiplet according to some embodiments of the present invention;
[0052] FIG. 10 is a flowchart illustrating methods of fabricating integrated circuits on a source wafer according to some embodiments of the present invention;
[0053] FIG. 11 is a flowchart illustrating the formation of a backplane according to some embodiments of the present invention;
[0054] FIGS. 12A and 12B are cross sections illustrating the fabrication of a backplane according to some embodiments of the present invention;
[0055] FIGS. 13A-13D are cross sections illustrating the fabrication of a backplane according to further embodiments of the present invention;
[0056] FIGS. 14A-14C are cross sections illustrating the fabrication of a backplane according to other embodiments of the present invention; and
[0057] FIG. 15 is a cross section illustrating a protective bi-layer according to other embodiments of the present invention.
[0058] The figures are not drawn to scale since the individual elements of the drawings have too great a size variation to permit depiction to scale.
Detailed Description of Embodiments of the Invention
[0059] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.
[0060] It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
[0061] It will also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.
[0062] Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, can therefore, encompasses both an orientation of “lower” and “upper,” depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
[0063] The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
[0064] Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
[0065] Unless otherwise defined, all terms used in disclosing embodiments of the invention, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, and are not necessarily limited to the specific definitions known at the time of the present invention being described. Accordingly, these terms can include equivalent terms that are created after such time. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the present specification and in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entireties.
[0066] Some embodiments of the present invention may be used in the fabrication of advanced display backplanes, for example, by assembling thousands of tiny integrated circuits onto glass substrates using transfer-printing. In particular, once circuits are printed onto a backplane or other target substrate, it may be necessary to form electrical interconnections. However, while the printing process may provide a high degree of accuracy, the chips may still be misplaced or misaligned on the order of 2-3 microns. Thus, interconnection processes may need to take such possible misalignment into consideration.
[0067] One interconnection approach towards addressing such misalignment is to form contact pads in the circuits that are large enough to account for both the transfer-printing accuracy and also the misalignment and size of the via to be formed down to the metal pad. In practice, such metal contact pads were relatively large, typically about 20 microns×20 microns in size.
[0068] In some embodiments of the present invention, a smaller contact pad can be formed in the circuit, for example, about 5 micrometers (μm)×5 μM, with a comparatively small via, for example, about 2 μm×2 μm, formed above the metal contact. As described in greater detail below, this process may be performed during the fabrication of the integrated circuit wafer, so the related design rules may be of reduced importance. Using the integrated-circuit vias according to some embodiments, the metal contact pad is reduced in size, and thus the design rules for the interconnection via to be formed on the large target substrate may be relaxed. Embodiments of the present invention may therefore provide improved electrical performance, fewer large-area photolithographic steps, improved yields, improved testability, increased density, and improved alignment tolerances for electrical circuit devices transferred from a source substrate to a destination substrate.
[0069] Referring to FIG. 1A , an integrated circuit according to embodiments of the present invention comprises a chiplet substrate 55 having a surface 58. Active elements 82, 83, 84 are formed on or in the chiplet substrate 55. The chiplet substrate 55 can include an active layer 54 in which the active elements 82, 83, 84 can be formed. The active layer 54 can include the entire chiplet substrate 55 or only a portion of the chiplet substrate 55 and can be doped or patterned to form the active elements 82, 83, 84. The active elements 82, 83, 84 can be integrated circuit elements. A connection pad 24 is formed on the surface 58 of the chiplet substrate 55. Chiplet wires 80 electrically connect the active elements 82, 83, 84 and the connection pad 24. Conductor elements 26, 26′ that are electrically separate from the connection pad 24 are formed on the surface 58 of the chiplet substrate 55. The conductors 26, 26′ are spatially separated by a distance X from the connection pad 24. The conductors 26, 26′ are electrically connected to a chiplet wire 80 or active element 82, 83, 84. An insulating layer 28 is formed over the surface 58 of the chiplet substrate 55 and over the conductor 26, 26′ leaving at least a portion of the connection pad 24 exposed, for example through the chiplet via 32 formed in the insulating layer 28. The connection pad 24 can be partially covered by the insulating layer 28. The integrated circuit can be a chiplet 20. As described herein, a “chiplet” may refer to a small integrated circuit that can be transferred to a backplane substrate 10 using a stamp as described below.
[0070] Referring to FIG. 1B , in some embodiments of the present invention, two chiplets 20 are located on the backplane 10 in desired design locations 21 and are covered with a planarization layer 30. Backplane vias 33 are formed in the planarization layer 30 in alignment with the connection pads 24 of the chiplets 20. Backplane wires 40 are formed in a single layer over the backplane 10 and insulating layer 28 and contact the connection pads 24 on the chiplets 20. Backplane vias 33 and backplane wires 40 are typically formed in separate masking steps from the location of the chiplets 20 and should be closely aligned with the chiplets 20 to ensure good electrical connections between the connection pads 24 and backplane wires 40. In a practical system, however, it can be difficult to align the chiplets 20 with the backplane 10 and the backplane masks used to form backplane vias 33 and backplane wires 40.
[0071] Referring to FIG. 1C , in some embodiments of the present invention, two chiplets 20′, 20″ are located on the backplane 10 and are covered with a planarization layer 30. The chiplet 20′ is located in the design location 21 while, because of manufacturing tolerances, the chiplet 20″ is mis-located or misaligned on the backplane 10 by a distance X (e.g., the same distance that is between the connection pad 24 and the conductor 26) away from the desired design location 21′. A backplane via 33 is formed in the planarization layer 30 in alignment with the connection pads 24 of the chiplets 20 according to the desired design location 21 thereof. The backplane via 33 may define an opening that is wider than the distance X between the connection pad 24 and the conductor 26. Backplane wires 40 are formed in a single layer over the backplane 10 and insulating layer 28 and contact the connection pads 24 on the chiplets 20. In this example, the exposed portion of the connection pad 24 is smaller than the area of the backplane via 33 in plan view. Because the chiplet 20″ is misaligned or otherwise not properly located relative to the desired design location 21′ on the backplane 10, the backplane via 33 is not well aligned with the connection pad 24 on the chiplet 20″, which is spaced a distance Y from the desired design location 21′ (where Y is greater than or equal to X). However, since the insulating layer 28 insulates the backplane wires 40 from the conductors 26, the backplane wires 40 still provide a connection to the connection pads 24 and not to the conductors 26.
[0072] The chiplet substrate 55 can be a semiconductor layer, for example silicon, GaAs, and/or other III-V compound semiconductors. The chiplet substrate 55 can be crystalline, amorphous, polycrystalline, or microcrystalline and can have multiple patterned or unpatterned layers of different materials, including electrically insulating layers such as some oxides and nitrides, e.g. silicon dioxide and silicon nitride. The active layer 54 can be a doped semiconductor or otherwise be processed to enable the formation of active elements 82, 83, 84. The active elements 82, 83, 84 can include electrical elements such as transistors, capacitors, resistors, and/or wires or electro-optical elements such as photo-sensors and/or light-emitting diodes, or both. The term “integrated circuit” may refer to a substrate that has been processed to form circuits integrated into a substrate, for example by photo-lithographic processes, to form optical, electrical, or electro-optic circuits that transform, process, and/or conduct electrical or optical energy. A “chiplet” can refer to a small integrated circuit, for example an integrated circuit that may be too small to be packaged and used in an electrical circuit using conventional pick-and place, surface mount, or flip-chip methods. For example, chiplets as described herein can have substrates that are 5-10 microns thick, 10-20 microns thick, 20-50 microns thick, or 50-100 microns thick. Chiplets can be 10-100 microns wide and 20-500 microns long, for example. The chiplets can have different sizes or areas, for example, 1000 square microns or 10,000 square microns, 100,000 square microns, or 1 square mm, or larger, and can have variable aspect ratios, for example 2:1, 5:1, or 10:1. Although embodiments of the present invention are described herein with reference to small chiplet integrated circuit devices, is the present invention is not limited thereto. Thus, the term “chiplet” should not be used for purposes of limitation, but may be used to distinguish integrated circuit elements of different sizes from one another.
[0073] The active elements described herein can be constructed in a source wafer using conventional photo-lithographic processes. The source wafer can be a crystalline semiconductor with very good electrical performance. The chiplet wires 80 can be made of metal, for example aluminum, in layers, for example metal layer 1, metal layer 2, metal layer 3, and so forth, as is done in the integrated circuit design and layout arts. The chiplet wires 80 in the various layers are used to electrically interconnect the active elements 82, 83, 84 to form electrical circuits. The top metal layer can be formed on the surface 58 of the chiplet substrate 55 to provide a connection pad 24 to which control or power signals external to the chiplet 20 can be electrically connected. The conductor 26 can be formed from a same layer and in a common processing step with the connection pad 24, for example a patterned metal layer. The conductor element 26 can be a metal interconnect such as a chiplet wire 80 or can be or include an active element 82, 83, 84 or a portion of an active element 82, 83, 84. The conductor 26 conducts or otherwise controls electrical current and is isolated from the connection pad 24 so that the conductor 26 and connection pads 24 are electrically separate and distinct. For example, the conductor 26 can be a connection pad separate from connection pad 24. A patterned insulating layer can be located in a layer beneath the conductors 26, 26′ and connection pad 24 and semiconductor layers in the active layer 54 to reduce and/or prevent unwanted electrical conduction.
[0074] The insulating layer 28 is located at least partly over the conductors 26, 26′ and connection pad 24 and is electrically insulating. The insulating layer 28 can be made of a variety of materials and perform multiple functions. The insulating layer 28 can be, for example a passivation or planarization layer and can comprise, for example, an oxide layer, a nitride layer, and/or a polymer layer, such as a resin (for example a curable resin). The insulating layer 28 does not necessarily cover the entire chiplet substrate 55, active layer 54, and conductors 26, 26′, but covers at least a portion of each of the chiplet substrate 55, active layer 54, and conductors 26, 26′.
[0075] The connection pad 24 can be formed of patterned metal, for example aluminum, silver, titanium, tungsten, metal alloys, and/or layers of metals. The connection pad 24 can be exposed through the insulating layer 28 by forming a via 32 through the insulating layer 28. Vias can be formed by coating a photo-curable resin over the surface, pattern-wise curing the resin to define the via, and then etching the resin and the insulating layer 28 beneath the resin to form the via 32 and removing the resin. Methods of coating photo-curable resins, pattern-wise exposing (e.g. with ultra-violet light though a mask) and pattern-etching the resin and layers beneath the resin to form vias are used in the art. Additionally or alternatively, the coated resin can form the insulating layer 28 and/or a portion thereof. Referring to FIG. 2 , the via 32 can have a larger area at the side of the insulating layer 28 opposite the chiplet substrate 55 (having a linear dimension 39) than the area on the connection pad 24 (having a linear dimension 38). In other words, the via 32 may narrow as it extends through the insulating layer 28.
[0076] In the integrated circuit design arts, it is desirable to provide as much circuitry in an integrated circuit as possible, in light of increasing demands for device functionality. Large and complex circuits can be difficult to route by providing electrical wire connections between the various elements of the circuit. Hence, it is often helpful to have many layers of interconnections. As such, it may be desirable to reduce the size or surface area the connection pads 24 so that other areas of the surface 58 of the chiplet substrate 55 and active layer 54 can be used for routing wires to other active elements 82, 83, 84 with conductors 26 independently of the connection pad 24. To enable this, the conductor 26 is not directly electrically connected to the connection pad 24. As illustrated in FIG. 1 , conductor 26′ directly electrically connects active element 84 to active element 83 and is electrically isolated from the connection pad 24. Two elements are directly electrically connected when a single electrically conductive wire contacts both elements so that electrical current can flow directly from one element to the other without passing through any other intervening elements, such as electrically controlling or processing elements.
[0077] As shown in FIG. 8 , when located over or printed on a backplane, chiplets of the present invention provide high-performance electrical or optical devices that can be electrically connected using lower-resolution, and thus lower-cost, wiring methods and materials. The backplane can include heterogeneous components distributed over the backplane, either regularly or irregularly. Backplane substrates can be glass, polymer, metal, and/or semiconductor, for example silicon, GaAs, or other III-V materials. The chiplets can respond to external controllers located on the backplane and/or externally to the backplane.
[0078] In various embodiments of the present invention, the backplane of the present invention can be used, for example, to form an active-matrix backplane where the chiplets are organized into an array controlling a corresponding array of elements, for example pixels in a display or a digital radiographic plate. In another example, the chiplets can be light-emitters, for example light-emitting diodes or LEDs, or a vertical cavity side-emission laser (e.g. edge laser). In yet another example, the chiplets can serve to convert incident light into electricity, forming a photovoltaic device, for example with photo-diodes. In cases where it is desirable to collect or emit light efficiently, the contacts or any metal layers formed beneath the active layer can reflect incident light that passes through the active component back through the active component. In cases where a chiplet serves to convert light to electrical current, this reflection can allow for improved absorption of light by the chiplet. In the case where the chiplet emits light, or controls the emission of light by other layers, the reflection can provide improved emission of light.
[0079] Referring to FIGS. 3A-3P , a backplane according to some embodiments of the present invention can be constructed as described below. Referring now to FIG. 3A , a source substrate 50, for example a wafer, has a sacrificial layer 52 formed thereon. The sacrificial layer 52 can be, for example, an oxide such as silicon dioxide and can be deposited by sputtering. A chiplet substrate 55 is formed over the sacrificial layer 52 and can also be deposited by sputtering. Active layer 54 can be formed by pattern-wise doping the chiplet substrate 55. The chiplet substrate 55 is processed to form active elements in the active layer 54. The chiplet substrate 55 and active layer 54 serve as the substrate of a small integrated circuit and can include additional layers and materials and can be annealed or otherwise processed to improve its characteristics, for example electron mobility. Active elements 82 (FIG. 1 ) can be formed within the active layer 54. In particular, the active layer 54 can include metal interconnect layers, doped material layers, and/or other layers used in the integrated circuit arts for forming active elements, such as electrical or electro-optic elements, e.g. transistors, photo-sensors, photo-voltaic elements, light-emitting diodes, etc.
[0080] Referring to FIG. 3B , connection pads 24 and conductors 26, for example formed in a patterned metallization layer, are formed on the surface (element 58 in FIG. 1 ) of the source substrate 50 and electrically connect the active elements in the active layer 54. The conductors 26 are not directly electrically connected to the connection pad 24. In some embodiments of the present invention, multiple connection pads 24 and conductors 26 are formed on a single chiplet. As discussed further below, the connection pads 24 can be spatially separated from each other and the conductors 26 can be located between connection pads 24 in some embodiments. Each set of active elements, connection pads 24, and conductors 26 form an integrated circuit chiplet 20.
[0081] Referring to FIG. 3C , once the connection pads 24 and conductors 26 are formed, the substrate surface, connection pads 24, and conductors 26 are coated with an insulating layer 28. The insulating layer 28 is electrically insulating and can comprise a variety of suitable materials, for example planarizing or passivation layers made of insulating material such as silicon oxides, silicon nitrides, and/or polymer resins. The insulating layer can be deposited by a variety of methods, for example by sputtering, spin coating, or curtain coating.
[0082] Referring to FIG. 3D , once coated, the insulating layer 28 can be patterned to expose at least a portion of the connection pad 24 and to cover over at least a portion of a conductor 26. In some embodiments of the present invention, the insulating layer 28 covers all, or most of, the conductor 26, as shown in FIG. 3D . The insulating layer 28 can also be patterned to expose the active layer 54 or chiplet substrate 55 between integrated circuit chiplets 20. Each wafer substrate 50 can have a plurality of integrated circuit chiplets 20 formed thereon.
[0083] In some embodiments of the present invention, wafer-scale testing can be applied at this stage. While conventional testing probes could be applied to the chiplet structures shown in FIG. 3B , the smaller connection pads are more difficult to contact with an electrical probe and a probe directed to one connection pad 24 can be shorted to neighboring connection pads 26. In contrast, when applied to the structure of FIG. 3D , an electrical probe directed to connection pad 24 cannot be shorted to other connection pads 26 due to the presence of the insulating layer 28.
[0084] In some embodiments of the present invention as shown in FIG. 3E , a protective layer 29 is formed over the insulating layer 28 and connection pads 24. The protective layer 29 can be deposited by maskless sputtering or coating. The protective layer 29 can be amorphous silicon in some embodiments; however, amorphous silicon can have undesirable interactions with the conductive materials that may be used in the connection pads, such as metals and, particularly, aluminum. Therefore, in some embodiments of the present invention as illustrated in FIG. 15 , the protective layer 29 can be a bi-layer 29A and 29B having different material in each layer of the bi-layer. Layer 29A can be selected and/or optimized to protect the connection pad material, for example silicon dioxide, while layer 29B compatible with layer 29A, for example amorphous silicon, can be selected and/or optimized for protection against subsequent processing steps described below, such as etching with hydrofluoric acid. Since both layers 29A and 29B are blanket coated, they can be deposited and removed (e.g. by sputtering and then etching) without further patterning process steps. Hence, the use of an additional protective layer can improve process compatibility with the release process used to fabricate printable chiplets described below.
[0085] Trenches 34 are formed, as shown in FIG. 3F and also in the top view of FIG. 7 , between and around each chiplet 20 through the active layer 54 to expose the sacrificial layer 52, leaving tethers 35 (FIG. 7 ) attaching the chiplets 20 to anchors 36 that form areas attached to the source substrate 50. The anchors 36 can be areas over the source substrate 50 and above the sacrificial layer 52 between the chiplets 20. The trenches 34 define and separate the chiplets 20 from each other and from the anchors 36. As shown in FIG. 7 , the anchors 36 can include active elements and test pads (not shown) accessible to external test probes, and a plurality of electrically conductive tethers 35. Each anchor is located over and in contact with the patterned sacrificial layer 52, 52′, and has a tether 35 connecting the anchor 36 to an integrated circuit chiplet 20. The tethers 35 electrically connect active elements in the integrated circuit chiplet 20 to one or more exposed electrical test pads formed in the anchor 36.
[0086] In a further process, the bi-layer of FIG. 15 can be formed in two separate steps and may involve a different etching process. After the first step (deposition of layer 29A), the trenches 34 can be etched through one or more, but not all, of the layers above the sacrificial layer 52. The second protective layer (29B) can be deposited before etching the sacrificial layer 52. By providing the protective layers 29A and 29B in two separate steps and etching different layers with different protective layers, the protective layers and etchants can be separately selected and/or optimized to provide improved results, for example better yields.
[0087] As shown in FIG. 3G , the sacrificial layer 52 is removed from beneath the chiplets 20, leaving an open location or void 52′ (where the sacrificial layer was) such that the chiplets 20 are suspended by the tethers 35 (FIG. 7 ) over the source substrate 50. The anchors 36 are not separated from the source substrate 50 by the etching (e.g., the sacrificial layer 52 remains beneath the anchors 36), so that the chiplets 20 are still connected (through the tethers 35 and anchors 36) to the source substrate 50. The anchors 36 are shown smaller than the chiplets 20 for clarity; in practice the anchors 36 can be larger in at least one dimension than the chiplets 20 so that the chiplets 20 can be released by etching from the source substrate 50 before the anchors 36 are released. For example, by stopping the etching process at an appropriate time, the chiplets 20 can be released while the anchors 36 are not released.
[0088] FIG. 3G corresponds to the cross section indicated by A-A′ in FIG. 7 . Patterned etching of insulation layers, forming trenches in active layers and active element layers, and removing sacrificial layers are process steps used in semiconductor device fabrication. For example, the active layer 54 can be crystalline silicon and the sacrificial layer 52 can be an oxide, such as silicon dioxide. The sacrificial layer 52 can be etched with hydrofluoric acid. The protective layer 29 protects the other elements from chemical attack by the etchants used to form the trenches 34 and remove the sacrificial layer 52. The protective layer can be, for example amorphous silicon, and can be blanket coated over the chiplets to protect the chiplet elements against attack by etchants such as hydrofluoric acid. Once the trenches 34 are formed and the sacrificial layer 52 removed, the protective layer 29 can be removed, again without requiring a mask step, as shown in FIG. 3H . Once the protective layer 29 is removed, electrical testing can be performed, in addition to or rather than at the earlier stage before the protective layer 29 is applied at the step illustrated in FIG. 3E , as noted above. In other embodiments, the protective layer 29 can be removed at a later process step, as described below.
[0089] The chiplets and the processes described herein can include additional layers and process steps. Furthermore, the process steps can be performed in various different orders, depending on the materials and process capabilities. For example, the insulating layer etch that exposes the connection pad (shown in FIG. 3D ) can be performed after the trench formation and sacrificial layer exposure, or after the removal of the sacrificial layer.
[0090] Referring to FIG. 3I , a stamp 60, for example an elastomeric or PDMS stamp, having protrusions shaped and sized to match the chiplets 20 can be pressed against the chiplets 20, breaking the tethers and adhering the chiplets 20 to the stamp 60 as the stamp 60 is removed (FIG. 3J ). Not every chiplet 20 need be removed from the source substrate 50, and the stamping process can be repeated one or multiple times with different chiplets applied to different locations on the backplane substrate.
[0091] The adhered chiplets 20 on the stamp 60 are pressed against a destination backplane 10 (FIG. 3K ) including an adhesive layer 72 to adhere the chiplets 20 to the backplane 10. The backplane 10 provides a target or receiving substrate on which an active device can be constructed. The adhesive layer 72 can cover only a relatively small portion of the backplane 10 so that patterned wires can be formed largely on the backplane 10, or the adhesive layer 72 can extend over much of the backplane 10 so that any patterned wires are formed largely on the adhesive layer 72. The stamp 60 can be removed and the adhesive layer 72 cured (FIG. 3L ). As shown in FIG. 3M , the stamping process can be repeated to locate multiple chiplets over the backplane 10 in multiple locations. By laterally translating the stamp 60 relative to the backplane 10 between each stamping operation, a sparse array of chiplets can be adhered to the backplane 10. However, as noted with respect to FIG. 1 , because of manufacturing process and tool limitations, a chiplet 20″ can be mis-located or misaligned with respect to a desired design location 21′. The mis-location or misalignment can be random or have a random distribution and can differ from one chiplet to another so that the relative locations of the chiplets differ with respect to the desired design locations.
[0092] The protective layer (29 in FIG. 3G ) can be removed at this step rather than at the step corresponding to FIG. 3H in some embodiments. Removing the protective layer at this point in the process allows the protective layer to protect the chiplets through the stamping process (FIGS. 3I-3K ). As noted above, the removal of the protective layer can be a maskless process.
[0093] Referring to FIG. 3N , a planarization layer 30 is coated over the backplane 10 and chiplets 20′, 20″. The coating can be local to each chiplet 20′, 20″ or can be uniformly coated over the backplane 10. As shown in FIG. 3O , the planarization layer 30 is then processed to form a backplane via 33″ over at least a portion of the exposed connection pad 24 associated with chiplet 20″ and a backplane via 33′ over at least a portion of the exposed connection pad 24 associated with chiplet 20′. An etchant used to form the backplane vias 33″ may be selective to the insulating layer 28. In some embodiments of the present invention, the protective layer (29 in FIG. 3G ) can then be removed at this step rather than at FIG. 3H . Removing the protective layer at this point in the process allows the protective layer to protect the chiplets through the stamping and planarization process (FIGS. 3I-3N ). As noted above, the removal of the protective layer (if present) can be a maskless process, although in this case the protective layer may only be removed in the via area since the planarization layer 30 covers the remainder of the chiplet area (see FIGS. 13A-13C and FIGS. 14A-14C discussed below).
[0094] As shown in FIG. 3O , the via 33″ is misaligned with respect to the chiplet 20″ so that the via 33″ exposes a portion (e.g., less than an entirety) of the connection pad 24 and chiplet via 32 and exposes at least a portion of the insulating layer 28. Such a misalignment can occur by mis-locating or misaligning the chiplet 20″ on the backplane 10, the backplane 10, or by mis-locating or misaligning the process elements, e.g. masks, used to form the via 33″ or to form a backplane interconnection. Note that the misalignment is between the location of the chiplet connection pad and any connecting backplane elements. Chiplet 20′ and backplane via 33′ are properly aligned. As shown in FIG. 3P , a backplane wire 40 is formed over the planarization layer 30 in contact with the connection pads 24 in the backplane vias 33″ and 33′. Because the insulating layer 28 is formed over the conductors 26, the backplane wire 40 does not electrically connect the connection pad 24 to the conductors 26, and does not, therefore, electrically short the connection pad 24 and conductor 26.
[0095] The planarization layer 30 can comprise, for example, a curable resin, and can be patterned to form a via using photo-sensitive resins, masks, and light exposure through the masks. In embodiments illustrated in FIG. 12A , the planarization layer 30 can be removed from the surface of the chiplet 20 exposing the integrated circuit chiplet and the backplane wires formed directly on the chiplet 20 and insulating layer 28 (FIG. 12B ).
[0096] Referring to FIG. 13A , the chiplet 20 is blanket coated with a protective layer 29 (for example a passivation layer) before it is removed from the wafer source substrate. The chiplet is then located on the backplane 10 (FIG. 13B ) and coated with planarization layer 30, and a backplane via 33 formed in the planarization layer 30 (FIG. 13C ) and the protective layer 29 removed (FIG. 13D ) in the via 33 before the formation of any interconnections. The protective layer 29 removal does not require patterning and can be performed after the planarization layer is processed.
[0097] Referring to FIGS. 14A-14C , the process illustrated in FIGS. 12A and 12B can also be employed with the blanket-coated protection layer of FIGS. 13A-13D . In these embodiments, the entire protective layer 29 is removed from the surface of the chiplet 20. Referring to FIG. 14A , the chiplets 20 on the backplane 10 have a protective layer 29 (formed as in FIG. 13A ) and the backplane 10 has a blanket-coated planarization layer (as in FIG. 13B ). Referring to FIG. 14B , the planarization layer 30 is removed to below the surface of the chiplet 20 (as in FIG. 12A ) exposing the protective layer 29. The protective layer 29 is then removed from the surface of the chiplet 20 and the chiplet via 32 and the insulating layer 28 are exposed. The steps of reducing the planarization layer 30 and removing the protective layer 29 are maskless. Hence, in FIGS. 14A-14C , the only process step after the chiplet construction that requires a mask is the formation of the chiplet via 32 on the wafer source substrate. Moreover, if the process of FIGS. 14A-14C is employed, no mask step at all may be required for backplane processing if the etching process is carefully controlled to expose the connection pads. Metal interconnects, such as those of FIG. 12B , can then be formed using either masked patterning or micro-deposition (such as inkjet) of conductive material. Thus, embodiments of the present invention enable backplane interconnection methods that require fewer large-area photolithographic processes, particularly patterning processes.
[0098] For clarity of illustration, FIGS. 12A-B , 13B-D, and 14A-C show only a single chiplet 20 on the backplane 10. However, the present invention includes backplanes having two or more chiplets 20 thereon. In one embodiment, the backplane of the present invention includes an array of chiplets 20 as illustrated in FIG. 8 .
[0099] The present invention can provide a chiplet structure that is robust in the presence of manufacturing process faults that may create relative mis-alignments between features on a chiplet and features on the backplane, even when using relatively small features on the chiplet, e.g. the connection pad. The small features can provide additional space within the chiplets for active elements or wiring, thereby increasing the functionality of the chiplets an enabling improved electrical performance. Specifically, embodiments of the present invention can enable smaller connection pads that do not require as much space on a chiplet substrate surface. Therefore, chiplets can have a greater functionality or, alternatively, smaller chiplets can be employed. For example, in embodiments of the present invention, chiplet location tolerances of 10 microns can be used, whereas, conventional tolerances can be 5 microns, 2 microns, or 1 micron. Thus interconnection methods that have greater margins of error can be applied to transfer-printed substrates. Hence, embodiments of the present invention can provide higher manufacturing yields and lower costs in the presence of manufacturing variability and can employ lower-cost tools to manufacture backplanes.
[0100] Embodiments of the present invention can provide advantages of improved electrical performance and density in integrated circuits transfer-printed over large substrates. Aspects of the invention can also reduce the number of large-area photolithographic steps, reduce alignment tolerance requirements, and are compatible with wafer testing and high-yield release processes for the transfer-printed integrated circuits.
[0101] Some advantages of the present invention will now be described in greater detail with reference to FIGS. 4A to 4C and FIGS. 5A to 5C . Referring first to FIGS. 4A-4C , a chiplet 20 with a relatively large connection pad 22 is located on a backplane 10 with a planarizing layer 30 and corresponding backplane via 33. As shown in FIG. 4A , if the backplane via 33 is properly aligned with the chiplet 20 large connection pad 22, a wire formed over the planarizing layer 30 can contact the large connection pad 22. If the backplane via 33 is not properly aligned with the chiplet 20 large connection pad 22, as shown in FIG. 4B , a wire formed over the planarizing layer 30 can still contact the large connection pad 22 without difficulty because the surface of the large connection pad 22 extends far enough along the chiplet 20 surface to compensate for some relative mis-alignment between the backplane 10 and the chiplet 20. Thus, a backplane wire 40 formed over the planarizing layer 30 can still contact the large connection pad 22, as shown in FIG. 4C . However, the large connection pad 22 occupies a relatively large amount of space on the surface of the chiplet 20, thereby reducing the potential functionality of the chiplet.
[0102] Referring to FIGS. 5A-5C , a chiplet 20 with a relatively small connection pad 24 and relatively small conductors 26 are located on a backplane 10 with a planarizing layer 30 and corresponding backplane via 33. Because smaller connection pads and conductors are used, compared to those in FIGS. 4A-4C , the chiplet 20 can have increased functionality by employing the space otherwise used by a large connection pad for additional circuitry and circuit connections. As shown in FIG. 5A , if the backplane via 33 is properly aligned with the chiplet 20 small connection pad 24, a wire formed over the planarizing layer 30 can contact the small connection pad 24 without difficulty. If the backplane via 33 is not properly aligned with the chiplet 20 small connection pad 24, as shown in FIG. 5B , a wire formed over the planarizing layer 30 can contact not only the small connection pad 24 but also the conductor 26. Thus, a backplane wire 40 formed over the planarizing layer 30 can form an electrical short circuit 42 between the small connection pad 24 and the conductor 26, as shown in FIG. 5C .
[0103] Referring to FIGS. 6A-6C , according to some embodiments of the present invention, a chiplet 20 with a small connection pad 24, small conductors 26, insulating layer 28, and chiplet via 32 is located on a backplane 10 having a planarizing layer 30 and corresponding backplane via 33. As shown in FIG. 6A , if the backplane via 33 is properly aligned with the small connection pad 24 and chiplet via 32, a wire formed over the planarizing layer 33 can contact the small connection pad 24 without difficulty. As shown in FIG. 6B , if the backplane via 33 is not properly aligned with the small connection pad 24 and chiplet via 32, the backplane via 33 can expose at least a portion of the connection pad 24 and the insulating layer 28 over the conductor 26. A backplane wire 40 formed over the planarizing layer 30 therefore contacts only the small connection pad 24 and does not contact the conductor 26 because of the insulating layer 28, as shown in FIG. 6C . Hence, a wire that electrically connects a chiplet mis-aligned with respect to the backplane 10 does not cause short circuits on the chiplet surface and still allows the use of space-conserving small connection pads 24 and additional, high-density conductors 26 for interconnecting active elements in the integrated circuit chiplet 20.
[0104] In some embodiments, multiple connection pads 24 on a single chiplet 20 can be spaced apart from one another as far as is practical so that any mis-alignment between the chiplet 20 and backplane 10 will not result in short circuits between two connection pads 24 on the same chiplet 20. In particular, because each of the connection pads 24 will have an exposed portion, connection pads 24 that are too close together can be short circuited by wires 40. Therefore, in some embodiments, one or more of the conductors 26 may be arranged between adjacent connection pads 24 to separate the connection pads 24 so far as is practical.
[0105] As illustrated in FIG. 9 and FIGS. 3A-3F , an integrated circuit according to various embodiments of the present invention can be made by providing a chiplet substrate in step 200, forming active elements on or in the chiplet substrate in step 205, forming chiplet wires electrically connecting the active elements and the connection pad in step 210, forming a connection pad on a surface of the chiplet substrate in step 215, forming one or more conductors electrically separate from the connection pad on the surface of the chiplet substrate in step 220, the conductors electrically connected to a chiplet wire or active element, and forming an insulating layer over the chiplet substrate and the conductor in step 225, leaving at least a portion of the connection pad exposed. The connection pad can be exposed with vias by photo-lithographically patterned etching of the insulating layer to pattern-wise expose the connection pad in step 230. An optional first protective layer (as discussed with reference to FIG. 15 ) can be formed over the insulating layer and the exposed connection pads in step 235.
[0106] As illustrated in FIG. 10 and FIGS. 3A-3H , a wafer having integrated circuits according to various embodiments of the present invention can be made by providing a wafer substrate in step 300, forming a sacrificial layer over the wafer substrate in step 305, forming an active layer over the sacrificial layer in step 310, and forming a plurality of integrated circuits on or in the active layer in step 315. Each integrated circuit can include active elements formed on or in the active layer, a connection pad formed on a surface of the active layer, chiplet wires electrically connecting the active elements and the connection pad, a conductor electrically separate from the connection pad formed on the surface of the active layer and electrically connected to a chiplet wire or active element, and an insulating layer formed over the active layer and the conductor, leaving at least a portion of the connection pad exposed. The integrated circuit chiplets can be made according to the methods described in FIG. 9 . The integrated circuits can be released from the wafer as described in FIGS. 3A-30 in step 320 and the protective layer, if formed in step 235 (FIG. 9 ), can be removed in step 325.
[0107] According to embodiments of the present invention illustrated in FIG. 11 and FIGS. 3A-3P , a method of making a backplane having integrated circuits includes the steps of providing a backplane substrate in step 400 and providing a plurality of integrated circuits located on the backplane in step 405. The integrated circuits can be located on the backplane in step 410, for example, using a transfer printing process. Each integrated circuit can include a chiplet substrate, active elements formed on or in the chiplet substrate, a connection pad formed on a surface of the chiplet substrate, chiplet wires electrically connecting the active elements and the connection pad, a conductor electrically separate from the connection pad formed on the surface of the chiplet substrate and electrically connected to a chiplet wire or active element, and an insulating layer formed over the chiplet substrate and the conductor, leaving at least a portion of the connection pad exposed. The integrated circuit chiplets can be made according to the methods described in FIG. 9 in some embodiments. A protective layer can optionally be formed over the insulating layer and exposed connection pad in step 235. If the protective layer was formed (step 235 FIG. 9 ) and not removed in step 325 (FIG. 10 ), it can be removed in step 415 before electrical connections are made in a single layer to the connection pads in step 420.
[0108] Referring to FIG. 3G and FIG. 7 , according to some embodiments of the present invention, a structured substrate having transferrable integrated circuit chiplets, includes a substrate 50, a patterned sacrificial layer 52, 52′ formed on the substrate 50, and a plurality of integrated circuit chiplets 20 formed on the patterned sacrificial layer 52, 52′. Each integrated circuit chiplet 20 includes a separate chiplet substrate 55 having a surface, where the separate chiplet substrate 55 detached from the substrate 50 by the pattern of the sacrificial layer 52, 52′. Active elements are formed on or in the chiplet substrate 55, a connection pad 24 is formed on the surface of the chiplet substrate 55, and chiplet wires are formed on or in the chiplet substrate 55 electrically connecting the active elements and the connection pad 24. A conductor 26 electrically separate from the connection pad 24 is formed on the surface of the chiplet substrate 55, where the conductor 26 electrically connected to a chiplet wire or active element. A patterned insulating layer 28 is formed over the chiplet substrate 55 and the conductor 26, leaving at least a portion of the connection pad exposed 24.
[0109] According to other embodiments of the present invention, a method of fabricating a structured substrate having transferrable integrated circuit chiplets includes the steps of providing a substrate, forming a sacrificial layer on the substrate, forming a chiplet substrate layer on the sacrificial layer, the chiplet substrate layer having a surface, forming active elements on or in the chiplet substrate layer, forming a connection pad on the surface, forming chiplet wires on or in the chiplet substrate electrically connecting the active elements and the connection pad, forming a conductor electrically separate from the connection pad on the surface, the conductor electrically connected to a chiplet wire or active element, forming an insulating layer over the chiplet substrate and the conductor, leaving at least a portion of the connection pad exposed, and patterning the chiplet substrate layer and the sacrificial layer to form separate chiplet substrates detached from the substrate.
[0110] In comparison to other thin-film manufacturing methods, using densely populated source substrates and transferring chiplets to a backplane substrate that requires only a sparse array of active components located thereon need not waste or require active layer material on a backplane substrate. Embodiments of the present invention can be used in transferring chiplets made with crystalline semiconductor materials that have much higher performance than thin-film active components. Furthermore, the flatness, smoothness, chemical stability, and heat stability requirements for a backplane substrate used in embodiments of the present invention can be greatly reduced because the adhesion and transfer process is not significantly limited by the backplane substrate material properties. Manufacturing and material costs can also reduced because of higher utilization rates of expensive materials (e.g. the active substrate) and reduced material and processing requirements for the backplane substrate. Embodiments of the present invention can also provide improved circuit density in small integrated circuits while reducing alignment and tolerance requirements for chiplets placed on a backplane. Thus, performance can be increased and costs can be reduced for active integrated circuits distributed over backplanes.
[0111] Furthermore, embodiments of the present invention can provide a reduction in masking steps on the backplane improving yields and reducing costs, can provide reduced connection pad size improving device functionality, and can provide less stringent tolerance requirements thereby improving yields and reducing processing costs.
[0112] The present invention has been described in detail with particular reference to certain embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention. This application also incorporates the disclosure of U.S. Pat. No. 7,622,367, which is entitled Methods and Devices for Fabricating and Assembling Printable Semiconductor Elements, by reference. The disclosures of U.S. patent application Ser. No. 12/732,868 entitled Methods of Forming Printable Integrated Circuit Devices and Devices Formed Thereby, U.S. Provisional Patent Application No. 61/371,467 entitled Materials And Processes for Releasing Printable Compound Semiconductor Devices, U.S. Provisional Patent Application No. 61/318,508 entitled Selective Transfer of Active Components, and U.S. Provisional Patent Application No. 61/377,131 entitled Structures And Methods for Testing Printable Integrated Circuits are also incorporated by reference herein.
[0113] Many different embodiments have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious and obfuscating to literally describe and illustrate every combination and subcombination of these embodiments. Accordingly, the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.
[0114] In the specification, there have been disclosed embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation. Hence, it is intended that the above embodiments and all of such variations and modifications be included within the scope and spirit of the invention as defined by the claims that follow.
Claims
That which is claimed:
1. An electronic component array, comprising:
a backplane substrate;
a plurality of integrated circuit elements disposed on the backplane substrate, each of the integrated circuit elements comprising a chiplet substrate, a connection pad disposed on a surface of the chiplet substrate, and a conductor element disposed on the surface of the chiplet substrate, wherein the connection pad and the conductor element are physically and electrically separated by an insulating layer that exposes at least a portion of the connection pad and is in contact with and covers the conductor element, and wherein at least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon at a distance from the desired position that is greater than or equal to a distance between the conductor element and the connection pad; and
a plurality of conductive wires on the backplane substrate that each extend over and in contact with the insulating layer, wherein the connection pad of each of the plurality of integrated circuit elements is electrically connected to a respective one of the conductive wires and the conductor element is insulated from each of the plurality of conductive wires by the insulating layer, notwithstanding that the at least one of the integrated circuit elements is misaligned on the backplane substrate.
2. The array of claim 1, further comprising an adhesive layer between the chiplet substrate of each of the plurality of integrated circuit elements and the backplane substrate, wherein the adhesive layer adheres the chiplet substrate of each of the plurality of integrated circuit elements to the backplane substrate.
3. The array of claim 1, further comprising a planarization layer comprising via openings disposed on the backplane substrate, and wherein each of the conductive wires extends into a respective via opening such that the conductive wires electrically contact the connection pad of each of the integrated circuit elements.
4. The array of claim 3, wherein respective positions of the via openings in the planarization layer are based on respective desired positions of the integrated circuit elements on the backplane substrate, and wherein at least one of the via openings exposes a portion of the connection pad and a portion of the insulating layer covering the conductor element of the at least one of the integrated circuit element that is misaligned on the receiving substrate.
5. The array of claim 4, wherein the exposed portion of the connection pad is smaller than a dimension of the at least one via opening.
6. The array of claim 1, wherein the connection pad of each of the plurality of integrated circuit elements is coupled to an active element therein, wherein the conductive wires provide an electrical connection between respective active elements of each chiplet substrate, and wherein the conductor element of each of the integrated circuit elements provides an electrical connection between respective active elements of a same chiplet substrate.
7. The array of claim 6, wherein each chiplet substrate of the plurality of integrated circuit elements comprises a plurality of connection pads and a plurality of conductor elements, and wherein at least one of the plurality of conductor elements is disposed between adjacent ones of the plurality of connection pads on the surface of the chiplet substrate.
8. The array of claim 1, wherein the plurality of integrated circuit elements comprise transfer-printed elements each comprising a broken tether.
9. The array of claim 1, wherein, for each of the plurality of integrated circuit elements, the conductor element and the connection pad on the chiplet substrate are portions of a same metal layer.
10. A structure for printing transferrable integrated circuit chiplets, comprising:
a source substrate;
a patterned sacrificial layer on the source substrate; and
a plurality of integrated circuit chiplets disposed on the patterned sacrificial layer, wherein each of the plurality of integrated circuit chiplets comprises:
a separate chiplet substrate detached from the source substrate by a pattern of the sacrificial layer;
a tether connecting the separate chiplet substrate to an anchor disposed on the source substrate;
active elements disposed on or in the chiplet substrate;
a connection pad disposed on a surface of the chiplet substrate;
chiplet wires disposed on or in the chiplet substrate electrically connecting the active elements and the connection pad;
a conductor element physically and electrically separate from the connection pad disposed on the surface of the chiplet substrate, the conductor element electrically connected to at least one of a chiplet wire and one of the active elements; and
an insulating layer disposed on the chiplet substrate and the conductor element, the insulating layer (i) leaving at least a portion of the connection pad exposed and (ii) in contact with and covering the conductor element.
11. The structure of claim 10, further comprising one or more exposed electrical test pads, each disposed in an anchor, wherein the tethers are electrically conductive tethers, each anchor is located over and in contact with the patterned sacrificial layer and has an electrically conductive tether connecting the anchor to one of the plurality of integrated circuit chiplets and one or more of the one or more exposed electrical test pads disposed in the anchor, and wherein the tethers electrically connect active elements in the one of the plurality of integrated circuit chiplets to the one or more of the one or more exposed electrical test pads disposed in the anchor.
12. A structure for printing transferrable integrated circuit chiplets, comprising:
a substrate;
a patterned sacrificial layer on the substrate; and
a plurality of integrated circuit chiplets disposed on the patterned sacrificial layer, wherein each of the plurality of integrated circuit chiplets comprises:
a separate chiplet substrate detached from the substrate by a pattern of the sacrificial layer;
active elements disposed on or in the chiplet substrate;
a connection pad disposed on a surface of the chiplet substrate;
chiplet wires disposed on or in the chiplet substrate electrically connecting the active elements and the connection pad;
a conductor electrically-separate from the connection pad on the surface of the chiplet substrate, the conductor electrically connected to at least one of a chiplet wire and one of the active elements; and
an insulating layer disposed on the chiplet substrate and the conductor, the insulating layer leaving at least a portion of the connection pad exposed, and
further comprising one or more exposed electrical test pads, a plurality of electrically conductive tethers, and anchors disposed on the substrate, each anchor located over and in contact with the patterned sacrificial layer and having a tether of the plurality of electrically conductive tethers connecting the anchor to one of the plurality of integrated circuit chiplets and one or more of the one or more exposed electrical test pads disposed in the anchor, wherein the tether electrically connects active elements in the one of the plurality of integrated circuit chiplets to the one or more exposed electrical test pads disposed in the anchor.
Patent Citations (289)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4322735(A) | 1982-03-01 | Sadamasa et al. | Applicant |
| US4330329(A) | 1982-05-01 | Hayashi et al. | Applicant |
| US4591659(A) | 1986-05-01 | Leibowitz | Applicant |
| US5173759(A) | 1992-12-01 | Anzaki et al. | Applicant |
| US5550066(A) | 1996-08-01 | Tang et al. | Applicant |
| US5563470(A) | 1996-10-01 | Li | Applicant |
| US5621555(A) | 1997-04-01 | Park | Applicant |
| US5625202(A) | 1997-04-01 | Chai | Applicant |
| US5629132(A) | 1997-05-01 | Suzuki et al. | Applicant |
| US5686790(A) | 1997-11-01 | Curtin et al. | Applicant |
| US5739800(A) | 1998-04-01 | Lebby et al. | Applicant |
| US5748161(A) | 1998-05-01 | Lebby et al. | Applicant |
| US5780933(A) | 1998-07-01 | Ohmori et al. | Applicant |
| US5815303(A) | 1998-09-01 | Berlin | Applicant |
| US5821571(A) | 1998-10-01 | Lebby et al. | Applicant |
| US5994722(A) | 1999-11-01 | Averbeck et al. | Applicant |
| US6025730(A) | 2000-02-01 | Akram et al. | Applicant |
| US6084579(A) | 2000-07-01 | Hirano | Applicant |
| US6087680(A) | 2000-07-01 | Gramann et al. | Applicant |
| US6142358(A) | 2000-11-01 | Cohn et al. | Applicant |
| US6143672(A) | 2000-11-01 | Ngo et al. | Applicant |
| US6169294(B1) | 2001-01-01 | Biing-Jye et al. | Applicant |
| US6184477(B1) | 2001-02-01 | Tanahashi | Applicant |
| US6278242(B1) | 2001-08-01 | Cok et al. | Applicant |
| US6392292(B1) | 2002-05-01 | Morishita | Examiner |
| US6392340(B2) | 2002-05-01 | Yoneda et al. | Applicant |
| US6403985(B1) | 2002-06-01 | Fan et al. | Applicant |
| US6410942(B1) | 2002-06-01 | Thibeault et al. | Applicant |
| US6422716(B2) | 2002-07-01 | Henrici et al. | Applicant |
| US6424028(B1) | 2002-07-01 | Dickinson | Applicant |
| US6466281(B1) | 2002-10-01 | Huang et al. | Applicant |
| US6504180(B1) | 2003-01-01 | Heremans et al. | Applicant |
| US6577367(B2) | 2003-06-01 | Kim | Applicant |
| US6660457(B1) | 2003-12-01 | Imai et al. | Applicant |
| US6703780(B2) | 2004-03-01 | Shiang et al. | Applicant |
| US6717560(B2) | 2004-04-01 | Cok et al. | Applicant |
| US6756576(B1) | 2004-06-01 | McElroy et al. | Applicant |
| US6812637(B2) | 2004-11-01 | Cok et al. | Applicant |
| US6825559(B2) | 2004-11-01 | Mishra et al. | Applicant |
| US6828724(B2) | 2004-12-01 | Burroughes | Applicant |
| US6853411(B2) | 2005-02-01 | Freidhoff et al. | Applicant |
| US6897855(B1) | 2005-05-01 | Matthies et al. | Applicant |
| US6933532(B2) | 2005-08-01 | Arnold et al. | Applicant |
| US6936855(B1) | 2005-08-01 | Harrah | Applicant |
| US6969624(B2) | 2005-11-01 | Iwafuchi et al. | Applicant |
| US6975369(B1) | 2005-12-01 | Burkholder | Applicant |
| US7009220(B2) | 2006-03-01 | Oohata | Applicant |
| US7012382(B2) | 2006-03-01 | Cheang et al. | Applicant |
| US7091523(B2) | 2006-08-01 | Cok et al. | Applicant |
| US7098589(B2) | 2006-08-01 | Erchak et al. | Applicant |
| US7127810(B2) | 2006-10-01 | Kasuga et al. | Applicant |
| US7129457(B2) | 2006-10-01 | McElroy et al. | Applicant |
| US7169652(B2) | 2007-01-01 | Kimura | Applicant |
| US7195733(B2) | 2007-03-01 | Rogers et al. | Applicant |
| US7259391(B2) | 2007-08-01 | Liu et al. | Applicant |
| US7288753(B2) | 2007-10-01 | Cok | Applicant |
| US7394194(B2) | 2008-07-01 | Cok | Applicant |
| US7402951(B2) | 2008-07-01 | Cok | Applicant |
| US7420221(B2) | 2008-09-01 | Nagai | Applicant |
| US7466075(B2) | 2008-12-01 | Cok et al. | Applicant |
| US7479731(B2) | 2009-01-01 | Udagawa | Applicant |
| US7521292(B2) | 2009-04-01 | Rogers et al. | Applicant |
| US7557367(B2) | 2009-07-01 | Rogers et al. | Applicant |
| US7586497(B2) | 2009-09-01 | Boroson et al. | Applicant |
| US7605053(B2) | 2009-10-01 | Couillard et al. | Applicant |
| US7605452(B2) | 2009-10-01 | Yamanaka et al. | Applicant |
| US7622367(B1) | 2009-11-01 | Nuzzo et al. | Applicant |
| US7662545(B2) | 2010-02-01 | Nuzzo et al. | Applicant |
| US7687812(B2) | 2010-03-01 | Louwsma et al. | Applicant |
| US7704684(B2) | 2010-04-01 | Rogers et al. | Applicant |
| US7791271(B2) | 2010-09-01 | Cok et al. | Applicant |
| US7799699(B2) | 2010-09-01 | Nuzzo et al. | Applicant |
| US7816856(B2) | 2010-10-01 | Cok et al. | Applicant |
| US7834541(B2) | 2010-11-01 | Cok | Applicant |
| US7893612(B2) | 2011-02-01 | Cok | Applicant |
| US7919342(B2) | 2011-04-01 | Cok | Applicant |
| US7927976(B2) | 2011-04-01 | Menard | Applicant |
| US7932123(B2) | 2011-04-01 | Rogers et al. | Applicant |
| US7943491(B2) | 2011-05-01 | Nuzzo et al. | Applicant |
| US7969085(B2) | 2011-06-01 | Cok | Applicant |
| US7972875(B2) | 2011-07-01 | Rogers et al. | Applicant |
| US7982296(B2) | 2011-07-01 | Nuzzo et al. | Applicant |
| US7990058(B2) | 2011-08-01 | Cok et al. | Applicant |
| US7999454(B2) | 2011-08-01 | Winters et al. | Applicant |
| US8029139(B2) | 2011-10-01 | Ellinger et al. | Applicant |
| US8039847(B2) | 2011-10-01 | Nuzzo et al. | Applicant |
| US8198621(B2) | 2012-06-01 | Rogers et al. | Applicant |
| US8207547(B2) | 2012-06-01 | Lin | Applicant |
| US8243027(B2) | 2012-08-01 | Hotelling et al. | Applicant |
| US8261660(B2) | 2012-09-01 | Menard | Applicant |
| US8288843(B2) | 2012-10-01 | Kojima et al. | Applicant |
| US8334545(B2) | 2012-12-01 | Levermore et al. | Applicant |
| US8394706(B2) | 2013-03-01 | Nuzzo et al. | Applicant |
| US8440546(B2) | 2013-05-01 | Nuzzo et al. | Applicant |
| US8450927(B2) | 2013-05-01 | Lenk et al. | Applicant |
| US8470701(B2) | 2013-06-01 | Rogers et al. | Applicant |
| US8502192(B2) | 2013-08-01 | Kwak et al. | Applicant |
| US8506867(B2) | 2013-08-01 | Menard | Applicant |
| US8519543(B1) | 2013-08-01 | Song et al. | Applicant |
| US8531642(B2) | 2013-09-01 | Kiryuschev et al. | Applicant |
| US8558243(B2) | 2013-10-01 | Bibl et al. | Applicant |
| US8605452(B2) | 2013-12-01 | Tang | Applicant |
| US8664699(B2) | 2014-03-01 | Nuzzo et al. | Applicant |
| US8686447(B2) | 2014-04-01 | Tomoda et al. | Applicant |
| US8722458(B2) | 2014-05-01 | Rogers et al. | Applicant |
| US8735932(B2) | 2014-05-01 | Kim et al. | Applicant |
| US8754396(B2) | 2014-06-01 | Rogers et al. | Applicant |
| US8766970(B2) | 2014-07-01 | Chien et al. | Applicant |
| US8791474(B1) | 2014-07-01 | Bibl et al. | Applicant |
| US8794501(B2) | 2014-08-01 | Bibl et al. | Applicant |
| US8803857(B2) | 2014-08-01 | Cok | Applicant |
| US8817369(B2) | 2014-08-01 | Daiku | Applicant |
| US8835940(B2) | 2014-09-01 | Hu et al. | Applicant |
| US8854294(B2) | 2014-10-01 | Sakariya | Applicant |
| US8860051(B2) | 2014-10-01 | Fellows et al. | Applicant |
| US8877648(B2) | 2014-11-01 | Bower et al. | Applicant |
| US8884844(B2) | 2014-11-01 | Yang et al. | Applicant |
| US8889485(B2) | 2014-11-01 | Bower | Applicant |
| US8895406(B2) | 2014-11-01 | Rogers et al. | Applicant |
| US8902152(B2) | 2014-12-01 | Bai et al. | Applicant |
| US8941215(B2) | 2015-01-01 | Hu et al. | Applicant |
| US8946760(B2) | 2015-02-01 | Kim | Applicant |
| US8987765(B2) | 2015-03-01 | Bibl et al. | Applicant |
| US9105714(B2) | 2015-08-01 | Hu et al. | Applicant |
| US9105813(B1) | 2015-08-01 | Chang | Applicant |
| US9142468(B2) | 2015-09-01 | Bower et al. | Applicant |
| US9153171(B2) | 2015-10-01 | Sakariya et al. | Applicant |
| US9161448(B2) | 2015-10-01 | Menard et al. | Applicant |
| US9166114(B2) | 2015-10-01 | Hu et al. | Applicant |
| US9178123(B2) | 2015-11-01 | Sakariya et al. | Applicant |
| US9202996(B2) | 2015-12-01 | Orsley et al. | Applicant |
| US9217541(B2) | 2015-12-01 | Bathurst et al. | Applicant |
| US9308649(B2) | 2016-04-01 | Golda et al. | Applicant |
| US9355854(B2) | 2016-05-01 | Meitl et al. | Applicant |
| US9358775(B2) | 2016-06-01 | Bower et al. | Applicant |
| US9368683(B1) | 2016-06-01 | Meitl et al. | Applicant |
| US9437782(B2) | 2016-09-01 | Bower et al. | Applicant |
| US9444015(B2) | 2016-09-01 | Bower et al. | Applicant |
| US9478583(B2) | 2016-10-01 | Hu et al. | Applicant |
| US9484504(B2) | 2016-11-01 | Bibl et al. | Applicant |
| US9496155(B2) | 2016-11-01 | Menard et al. | Applicant |
| US9520537(B2) | 2016-12-01 | Bower et al. | Applicant |
| US9537069(B1) | 2017-01-01 | Bower et al. | Applicant |
| US9555644(B2) | 2017-01-01 | Rogers et al. | Applicant |
| US9601356(B2) | 2017-03-01 | Bower et al. | Applicant |
| US9626908(B2) | 2017-04-01 | Sakariya et al. | Applicant |
| US9640715(B2) | 2017-05-01 | Bower et al. | Applicant |
| US9741785(B2) | 2017-08-01 | Bower et al. | Applicant |
| US9761754(B2) | 2017-09-01 | Bower et al. | Applicant |
| US9765934(B2) | 2017-09-01 | Rogers et al. | Applicant |
| US9865832(B2) | 2018-01-01 | Bibl et al. | Applicant |
| US9899329(B2) | 2018-02-01 | Bower | Applicant |
| US9899465(B2) | 2018-02-01 | Bower et al. | Applicant |
| US2001/0022564(A1) | 2001-09-01 | Youngquist et al. | Applicant |
| US2002/0096994(A1) | 2002-07-01 | Iwafuchi et al. | Applicant |
| US2003/0211649(A1) | 2003-11-01 | Hirai et al. | Applicant |
| US2004/0180476(A1) | 2004-09-01 | Kazlas et al. | Applicant |
| US2004/0212296(A1) | 2004-10-01 | Nakamura et al. | Applicant |
| US2004/0227704(A1) | 2004-11-01 | Wang et al. | Applicant |
| US2004/0252933(A1) | 2004-12-01 | Sylvester et al. | Applicant |
| US2005/0006657(A1) | 2005-01-01 | Terashita | Applicant |
| US2005/0012076(A1) | 2005-01-01 | Morioka | Applicant |
| US2005/0116324(A1) | 2005-06-01 | Yamaguchi | Examiner |
| US2005/0116621(A1) | 2005-06-01 | Bellmann et al. | Applicant |
| US2005/0140275(A1) | 2005-06-01 | Park | Applicant |
| US2005/0168987(A1) | 2005-08-01 | Tamaoki et al. | Applicant |
| US2005/0202595(A1) | 2005-09-01 | Yonehara et al. | Applicant |
| US2005/0264472(A1) | 2005-12-01 | Rast | Applicant |
| US2005/0275615(A1) | 2005-12-01 | Kahen et al. | Applicant |
| US2005/0285246(A1) | 2005-12-01 | Haba et al. | Applicant |
| US2006/0051900(A1) | 2006-03-01 | Shizuno | Applicant |
| US2006/0055864(A1) | 2006-03-01 | Matsumura et al. | Applicant |
| US2006/0063309(A1) | 2006-03-01 | Sugiyama et al. | Applicant |
| US2006/0116046(A1) | 2006-06-01 | Morley et al. | Applicant |
| US2007/0035340(A1) | 2007-02-01 | Kimura | Applicant |
| US2007/0077349(A1) | 2007-04-01 | Newman et al. | Applicant |
| US2007/0201056(A1) | 2007-08-01 | Cok et al. | Applicant |
| US2007/0235849(A1) | 2007-10-01 | Othieno et al. | Applicant |
| US2008/0006843(A1) | 2008-01-01 | Dai et al. | Applicant |
| US2008/0211734(A1) | 2008-09-01 | Huitema et al. | Applicant |
| US2008/0224153(A1) | 2008-09-01 | Tomoda | Applicant |
| US2009/0023243(A1) | 2009-01-01 | Koyanagi | Examiner |
| US2009/0053498(A1) | 2009-02-01 | Matsuura et al. | Applicant |
| US2009/0278141(A1) | 2009-11-01 | Coe-Sullivan et al. | Applicant |
| US2009/0278142(A1) | 2009-11-01 | Watanabe et al. | Applicant |
| US2009/0315054(A1) | 2009-12-01 | Kim et al. | Applicant |
| US2010/0060553(A1) | 2010-03-01 | Zimmerman et al. | Applicant |
| US2010/0078670(A1) | 2010-04-01 | Kim et al. | Applicant |
| US2010/0123134(A1) | 2010-05-01 | Nagata | Applicant |
| US2010/0148198(A1) | 2010-06-01 | Sugizaki et al. | Applicant |
| US2010/0186883(A1) | 2010-07-01 | Tomoda | Applicant |
| US2010/0190293(A1) | 2010-07-01 | Maeda et al. | Applicant |
| US2010/0207852(A1) | 2010-08-01 | Cok | Applicant |
| US2010/0214247(A1) | 2010-08-01 | Tang et al. | Applicant |
| US2010/0258710(A1) | 2010-10-01 | Wiese et al. | Applicant |
| US2010/0264816(A1) | 2010-10-01 | Cok | Applicant |
| US2010/0289115(A1) | 2010-11-01 | Akiyama et al. | Applicant |
| US2010/0315319(A1) | 2010-12-01 | Cok et al. | Applicant |
| US2010/0317132(A1) | 2010-12-01 | Rogers et al. | Applicant |
| US2011/0043435(A1) | 2011-02-01 | Hebenstreit et al. | Applicant |
| US2011/0067911(A1) | 2011-03-01 | Ishikawa et al. | Applicant |
| US2011/0108800(A1) | 2011-05-01 | Pan | Applicant |
| US2011/0133324(A1) | 2011-06-01 | Fan et al. | Applicant |
| US2011/0211348(A1) | 2011-09-01 | Kim | Applicant |
| US2011/0244225(A1) | 2011-10-01 | Hattori et al. | Applicant |
| US2012/0009738(A1) | 2012-01-01 | Crawford et al. | Applicant |
| US2012/0080692(A1) | 2012-04-01 | Ohtorii | Applicant |
| US2012/0141799(A1) | 2012-06-01 | Kub et al. | Applicant |
| US2012/0223636(A1) | 2012-09-01 | Shin et al. | Applicant |
| US2012/0223875(A1) | 2012-09-01 | Lau et al. | Applicant |
| US2012/0228669(A1) | 2012-09-01 | Bower et al. | Applicant |
| US2012/0256163(A1) | 2012-10-01 | Yoon et al. | Applicant |
| US2012/0313241(A1) | 2012-12-01 | Bower | Applicant |
| US2012/0314388(A1) | 2012-12-01 | Bower et al. | Applicant |
| US2012/0319563(A1) | 2012-12-01 | Ishihara et al. | Applicant |
| US2013/0015483(A1) | 2013-01-01 | Shimokawa et al. | Applicant |
| US2013/0036928(A1) | 2013-02-01 | Rogers et al. | Applicant |
| US2013/0069275(A1) | 2013-03-01 | Menard et al. | Applicant |
| US2013/0088416(A1) | 2013-04-01 | Smith et al. | Applicant |
| US2013/0207964(A1) | 2013-08-01 | Fleck et al. | Applicant |
| US2013/0309792(A1) | 2013-11-01 | Tischler et al. | Applicant |
| US2013/0328190(A1) | 2013-12-01 | Wu et al. | Applicant |
| US2013/0333094(A1) | 2013-12-01 | Rogers et al. | Applicant |
| US2014/0104243(A1) | 2014-04-01 | Sakariya et al. | Applicant |
| US2014/0138543(A1) | 2014-05-01 | LaVeigne | Applicant |
| US2014/0146273(A1) | 2014-05-01 | Kim et al. | Applicant |
| US2014/0159043(A1) | 2014-06-01 | Sakariya et al. | Applicant |
| US2014/0175498(A1) | 2014-06-01 | Lai | Applicant |
| US2014/0183446(A1) | 2014-07-01 | Nago et al. | Applicant |
| US2014/0217448(A1) | 2014-08-01 | Kim et al. | Applicant |
| US2014/0231839(A1) | 2014-08-01 | Jeon et al. | Applicant |
| US2014/0231851(A1) | 2014-08-01 | Tsai et al. | Applicant |
| US2014/0264763(A1) | 2014-09-01 | Meitl et al. | Applicant |
| US2014/0267683(A1) | 2014-09-01 | Bibl et al. | Applicant |
| US2014/0306248(A1) | 2014-10-01 | Ahn et al. | Applicant |
| US2014/0319486(A1) | 2014-10-01 | Hong | Applicant |
| US2014/0367633(A1) | 2014-12-01 | Bibl et al. | Applicant |
| US2015/0135525(A1) | 2015-05-01 | Bower | Applicant |
| US2015/0137153(A1) | 2015-05-01 | Bibl et al. | Applicant |
| US2015/0169011(A1) | 2015-06-01 | Bibl et al. | Applicant |
| US2015/0263066(A1) | 2015-09-01 | Hu et al. | Applicant |
| US2015/0280066(A1) | 2015-10-01 | Fujimura et al. | Applicant |
| US2015/0280089(A1) | 2015-10-01 | Obata et al. | Applicant |
| US2015/0371585(A1) | 2015-12-01 | Bower et al. | Applicant |
| US2015/0371974(A1) | 2015-12-01 | Bower et al. | Applicant |
| US2015/0372051(A1) | 2015-12-01 | Bower et al. | Applicant |
| US2015/0372187(A1) | 2015-12-01 | Bower et al. | Applicant |
| US2015/0372393(A1) | 2015-12-01 | Bower et al. | Applicant |
| US2016/0005721(A1) | 2016-01-01 | Bower et al. | Applicant |
| US2016/0018094(A1) | 2016-01-01 | Bower et al. | Applicant |
| US2016/0064363(A1) | 2016-03-01 | Bower et al. | Applicant |
| US2016/0066789(A1) | 2016-03-01 | Rogers et al. | Applicant |
| US2016/0086855(A1) | 2016-03-01 | Bower et al. | Applicant |
| US2016/0093600(A1) | 2016-03-01 | Bower et al. | Applicant |
| US2016/0308103(A1) | 2016-10-01 | Hu et al. | Applicant |
| US2017/0025593(A1) | 2017-01-01 | Bower et al. | Applicant |
| US2017/0187976(A1) | 2017-06-01 | Cok | Applicant |
| US2017/0206845(A1) | 2017-07-01 | Sakariya et al. | Applicant |
| US2017/0210117(A1) | 2017-07-01 | Rogers et al. | Applicant |
| US2017/0213803(A1) | 2017-07-01 | Bower | Applicant |
| US2017/0250167(A1) | 2017-08-01 | Bower et al. | Applicant |
| US2017/0256521(A1) | 2017-09-01 | Cok et al. | Applicant |
| US2017/0287789(A1) | 2017-10-01 | Bower et al. | Applicant |
| US2017/0309698(A1) | 2017-10-01 | Bower et al. | Applicant |
| US2017/0338374(A1) | 2017-11-01 | Zou et al. | Applicant |
| US2018/0138071(A1) | 2018-05-01 | Bower et al. | Applicant |
| US2018/0151664(A1) | 2018-05-01 | Bower et al. | Applicant |
| US2018/0226287(A1) | 2018-08-01 | Bower et al. | Applicant |
| US2018/0277504(A1) | 2018-09-01 | Bower | Applicant |
| US2018/0286734(A1) | 2018-10-01 | Meitl et al. | Applicant |
| US2018/0323178(A1) | 2018-11-01 | Meitl et al. | Applicant |
| EP1548571(A1) | 2005-06-01 | Applicant | |
| GB2496183(A) | 2013-05-01 | Applicant | |
| JPH11-142878(A) | 1999-05-01 | Applicant | |
| JP2011066130(A) | 2011-03-01 | Applicant | |
| WO-2006/027730(A1) | 2006-03-01 | Applicant | |
| WO-2006/099741(A1) | 2006-09-01 | Applicant | |
| WO-2008/103931(A2) | 2008-08-01 | Applicant | |
| WO-2010/032603(A1) | 2010-03-01 | Applicant | |
| WO-2010/102310(A2) | 2010-09-01 | Applicant | |
| WO-2010/111601(A2) | 2010-09-01 | Applicant | |
| WO-2010/132552(A1) | 2010-11-01 | Applicant | |
| WO-2013/064800(A1) | 2013-05-01 | Applicant | |
| WO-2013/165124(A1) | 2013-11-01 | Applicant | |
| WO-2014/121635(A1) | 2014-08-01 | Applicant | |
| WO-2014/149864(A1) | 2014-09-01 | Applicant | |
| WO-2016/046283(A2) | 2016-03-01 | Applicant | |
| WO-2017/144573(A1) | 2017-08-01 | Applicant | |
| WO-2018/091459(A1) | 2018-05-01 | Applicant |
Non-Patent Literature (24)
- Chesterfield, R. J. et al., 63.3:Multinozzle Printing: A Cost-effective Process for OLED Display Fabrication, SID 2009 Digest, vol. XL:Book II, 951-954.Applicant
- Choi, H. W. et al., Efficient GaN-based Micro-LED Arrays, Mat. Res. Soc. Symp. Proc. 743:L6.28.1-L6.28.6 (2003).Applicant
- Elenius, Peter, Flip-Chip and Wire-Bond Interconnection Technologies, Chip Scale Review, Jul./Aug.:81-87 (2000).Applicant
- Hamer et al., 63.2: AMOLED Displays Using Transfer-Printed Integrated Circuits, SID 09 Digest, 40(2):947-950 (2009).Applicant
- Lee, M. S. et al., Optimization of copper pillar bump design for fine pitch flip-chip packages, Microsystems, Packaging, Assembly and Circuits Technology Conference 2009, IMPACT 2009, 4th International, pp. 128-131.Applicant
- Lee, S. H. etal, Laser Lift-Off of GaN Thin Film and its Application to the Flexible Light Emitting Diodes, Proc. of SPIE 8460:846011-1-846011-6 (2012).Applicant
- Lu, N. et al., Bio-Integrated Electronics, IEEE International Conference on IC Design & Technology, DOI: 10.1109/ICICDT.2014.6838615, IEEE May 28, 2014, [retrieved on Jun. 17, 2014] pp. 1-5 (2014).Applicant
- Ohno, Y. and Ohzeki, Y., Development of Ultrathin Bonding Wire for Fine Pitch Bonding, Nippon Steel Technical Report 59:1-5 (1993).Applicant
- Poher, V. et al., Micro-LED arrays: a tool for two-dimensional neuron stimulation, J. Phys. D: Appl. Phys. 41:094014 (2008).Applicant
- Roscher, H., VCSEL Arrays with Redundant Pixel Designs for 10Gbits/s 2-D Space-Parallel MMF Transmission, Annual Report, optoelectronics Department, (2005).Applicant
- Yaniv et al., A 640 x 480 Pixel Computer Display Using Pin Diodes with Device Redundancy, 1988 International Display Research Conference, IEEE, CH-2678-1/88:152-154 (1988).Applicant
- Bower, C. A. et al., Transfer Printing: An Approach for Massively Parallel Assembly of Microscale Devices, IEE, Electronic Components and Technology Conference, 2008, pp. 1105-1109.Applicant
- Cok, R. S. et al., 60.3: AMOLED Displays Using Transfer-Printed Integrated Circuits, Society for Information Display, 10:902-904, (2010).Applicant
- Cok, R. S. et al., AMOLED displays with transfer-printed integrated circuits, Journal of the SID, 19(4):335-341, (2011).Applicant
- Cok, R. S. et al., Inorganic light-emitting diode displays using micro-transfer printing, Journal of the SID, 25(10):589-609, (2017).Applicant
- Feng, X. et al., Competing Fracture in Kinetically Controlled Transfer Printing, Langmuir, 23(25):12555-12560, (2007).Applicant
- Gent, A.N., Adhesion and Strength of Viscoelastic Solids. Is There a Relationship between Adhesion and Bulk Properties?, American Chemical Society, Langmuir, 12(19):4492-4496, (1996).Applicant
- Kim, Dae-Hyeong et al., Optimized Structural Designs for Stretchable Silicon Integrated Circuits, Small, 5(24):2841-2847, (2009).Applicant
- Kim, Dae-Hyeong et al., Stretchable and Foldable Silicon Integrated Circuits, Science, 320:507-511, (2008).Applicant
- Kim, S. et al., Microstructured elastomeric surfaces with reversible adhesion and examples of their use in deterministic assembly by transfer printing, PNAS, 107(40):17095-17100, (2010).Applicant
- Kim, T. et al., Kinetically controlled, adhesiveless transfer printing using microstructured stamps, Applied Physics Letters, 94(11):113502-1-113502-3, (2009).Applicant
- Meitl, M. A. et al., Transfer printing by kinetic control of adhesion to an elastomeric stamp, Nature Material, 5:33-38, (2006).Applicant
- Michel, B. et al., Printing meets lithography: Soft approaches to high-resolution patterning, J. Res. & Dev. 45(5):697-708, (2001).Applicant
- Trindade, A.J. et al., Precision transfer printing of ultra-thin AlInGaN micron-size light-emitting diodes, Crown, pp. 217-218, (2012).Applicant