Adaptive control of resonant power converters

[0001] This invention relates to the field of electrical power conversion and more particularly to resonant switching power converters.

[0002] Resonant switching power converters may be used as fixed ratio bus converters in power conversion systems to provide scaling of voltages and currents and optionally galvanic isolation. In non-idealized switching converters, i.e., switches used in the converter have parasitic capacitances and inductances, power may be dissipated in a switch when the switch is being turned ON, giving rise to a “switching loss.” Capacitances, both parasitic and lumped, across a switch if not discharged before the switch is turned ON may be a major contributor to switching loss. One way to reduce switching loss in a switching power converter is to use an inductive current to fully or partially charge and discharge the capacitances associated with a switch before turning it ON to achieve full or partial zero voltage switching (“ZVS”) during an energy recycling interval (“ERI”) (which may also be called a “ZVS” interval). ZVS ideally causes the voltage across the switch to decline to zero volts, essentially eliminating switching loss associated with the capacitive discharge of the switch; however, any significant reduction, e.g. by 50 percent, 80 percent, 90 percent, or more from the peak voltage across the switch, respectively reduces the switching loss during turn ON by approximately 75 percent, 96 percent, 99 percent, or more. Turning switches ON and OFF at times when zero or minimal current is flowing through the switch, called zero current switching (“ZCS”), can also reduce losses and reduce noise.

[0003] One exemplary method of converting power from a source at a source voltage, V_S, via a converter input at an input voltage, V_IN, for delivery to a load via a converter output at a rectified output voltage, V_OUT, where a current drawn by the load, I_L, may vary over a normal operating range from a minimum load current, I_L-MIN, to a maximum load current, I_L-MAX, may include providing a transformer. A resonant circuit including the transformer may be formed having a characteristic resonant frequency and period. Output circuitry may be connected to the transformer for delivering the rectified output voltage to the load. Input circuit circuitry including two or more primary switches may be connected to drive the resonant circuit. A switch controller may be provided to operate the primary switches in a series of converter operating cycles to provide an essentially fixed voltage transformation ratio, K=V_OUT/V_IN, at a load current, each converter operating cycle characterized by (a) two power transfer intervals of essentially equal duration each interval having a duration, T_PTI, less than the characteristic resonant period, during which one or more of the primary switches are ON, a resonant current at the characteristic resonant frequency and a magnetizing current flow through a winding of the transformer, and power is transferred from the input to the output via the transformer; and (b) two energy-recycling intervals, each having a duration during which the primary switches are OFF and currents in the converter are used to charge and discharge capacitances in the converter. A predetermined full duration, T_PTI-FULL, approximately equal one half of the characteristic resonant period may be established for each power transfer interval for conditions in which the load current, I_L, is greater than or equal to a first predetermined threshold, I_L1. A predetermined minimum duration, T_PTI-MIN, may be established for each power transfer interval for conditions in which the load current, I_L, is less than or equal to a second predetermined threshold, I_L2. The duration of each power transfer interval, T_PTI, may be adjusted from the predetermined full duration, T_PTI-FULL, to the predetermined minimum, T_PTI-MIN, as a function of variations in the load current, I_L, between the first threshold, I_L1, and the second threshold, I_L2.

[0004] Another exemplary method of controlling power train switches in a power converter may include providing a gate drive circuit including a gate drive source having a positive terminal and a negative terminal, an inductor having a first end and a second end, a plurality of gate drive switches, including a first, a second, a third, and a fourth gate drive switch, connected to drive the inductor, and a switch controller connected to operate the gate drive switches in a series of driver operating cycles. The driver operating cycles may include a first interval during which the first and fourth gate drive switches are ON and connect the first end of the inductor to the positive terminal and a second end of the inductor to the negative terminal during which an average positive current flows through the inductor; a first transition following the first interval during which the first and fourth gate drive switches are turned OFF and the current flowing in the inductor charges and discharges capacitances coupled to the inductor; a second interval during which the second and third gate drive switches are ON and connect the second end of the inductor to the positive terminal and the first end of the inductor to the negative terminal during which an average negative current flows through the inductor; a second transition following the second interval during which the second and third gate drive switches are turned OFF and the current flowing in the inductor charges and discharges capacitances coupled to the inductor. The driver operating cycles may be characterized by a driver operating period. The switch controller may adjust the duration of the operating period, the duration of the first and second intervals, and the duration of the first and second transitions. At least one of the capacitances coupled to the inductor may include an input capacitance associated with one or more of the power train switches.

[0005] Another exemplary method of controlling power train switches in a power converter may include providing a gate drive circuit including a gate drive source having a positive terminal and a negative terminal, an inductor having a first end connected to a first node and a second end connected to a second node, a plurality of gate drive switches, including a first gate drive switch and a second drive switch connected to the first node, a third drive switch and a fourth gate drive switch connected to the second node, and a switch controller connected to operate the gate drive switches in a series of driver operating cycles. One or more input capacitances associated with the power train switches may be coupled to the inductor. The driver operating cycles, which may be characterized by a driver operating period, may include a first interval during which the first and fourth gate drive switches are ON and connect the first node to the positive terminal and the second node to the negative terminal during which an average positive current flows through the inductor; a first transition following the first interval during which the first and second gate drive switches are OFF and the current flowing in the inductor charges and discharges capacitances coupled to the first node; a second transition following the first interval during which the third and fourth gate drive switches are OFF and the current flowing in the inductor charges and discharges capacitances coupled to the second node; a second interval during which the second and third gate drive switches are ON and connect the second node to the positive terminal and the first node to the negative terminal during which an average negative current flows through the inductor; a third transition following the second interval during which the first and second gate drive switches are OFF and the current flowing in the inductor charges and discharges capacitances coupled to the first node; and a fourth transition following the second interval during which the third and fourth gate drive switches are OFF and the current flowing in the inductor charges and discharges capacitances coupled to the second node. The switch controller may be configured to adjust the following control variables during operation of the power converter: (a) the operating period, (b) the durations of the first and second intervals, (c) the durations of the first, second, third, and fourth transitions, (d) a first delay between the first and second transitions and a second delay between the third and fourth transitions.

[0006] Another exemplary method may include providing a power converter for converting DC power received from a converter input for delivery to a converter output at an essentially fixed voltage transformation ratio, K=Vout/Vin and an output resistance. Circuitry having a first input connected to the converter input for sensing the input voltage, a second input connected to the converter output for sensing the output voltage, may provide a signal proportional to a difference between the output voltage and a scaled replica of the input voltage. The signal may be used to determine the load current.

[0007] Alternate embodiments of the above exemplary methods may include one or more of the following features. The duration of the energy recycling intervals, T_ERI, may be adjusted to vary from a maximum, T_ERI-MAX, at times when the duration of the power transfer interval is set to the predetermined minimum, T_PTI-MIN, and to a minimum, T_ERI-MIN, at times when the duration of the power transfer interval is set to the predetermined maximum, T_PTI-MAX. The first predetermined threshold, I_L1, may be greater than or equal to 33 percent of the maximum load current, I_L-MAX. The first predetermined threshold, I_L1, may be greater than or equal to 50 percent of the maximum load current, I_L-MAX. The first predetermined threshold, I_L1, may be greater than or equal to 65 percent of the maximum load current, I_L-MAX. The second predetermined threshold, I_L2, may be approximately equal to the minimum load current, I_L-MIN. The minimum load, I_L-MIN, current may be zero. The predetermined minimum duration, T_PTI-MIN, may be greater than or equal to 25 percent of the characteristic resonant period. The predetermined minimum duration, T_PTI-MIN, may be in a range between 25 to 35 percent of the characteristic resonant period. The primary switches may be turned ON at times when a voltage across the respective switch, V_SW, is approximately zero. The primary switches may be turned ON at times when a voltage across the respective switch, V_SW, is less than 25 percent of a maximum voltage across the respective switch, V_SW-MAX, in the OFF state during normal operation. A non-isolated power train may be used. The input circuitry and at least a portion of the output circuitry may be connected in series across the source such that an absolute value of the input voltage V_IN applied to the input circuitry is approximately equal to the absolute value of the DC source voltage V_S minus a number N times the absolute value of the output voltage V_OUT, where N is at least 1.

[0008] The resonant circuit may further include a resonant capacitor, and a clamp switch may be provided to clamp the resonant capacitor; and the power transfer intervals may further include (i) first and second resonant intervals, each having a duration less than one half of the characteristic resonant period, during which the resonant current flows at the characteristic resonant frequency and (ii) a clamp interval occurring after the first resonant interval and before the second resonant interval and having a clamp duration during which the clamp switch is ON and provides a low impedance shunt across the resonant capacitor. The switch controller may adjust the clamp duration as a function of power delivered to the load. A predetermined maximum duration, T_PTI-MAX, greater than one half of the characteristic resonant period, may be established for each power transfer interval for conditions in which the load current, I_L, is greater than or equal to a fourth predetermined threshold, I_L4. The duration of each power transfer interval, T_PTI, may be adjusted from the predetermined full duration, T_PTI-FULL, to the predetermined maximum, T_PTI-MAX, as a function of variations in the load current, I_L, between the second threshold, I_L2, and the fourth threshold, I_L4.

[0009] The duration of the energy recycling intervals, T_ERI, may be adjusted as a function of the power delivered to the load. The duration of the energy recycling intervals, T_ERI, may be increased in response to a decrease in the power delivered to the load. The duration of each power transfer interval, T_PTI, may be controlled as a function of a primary current, I_PRI, flowing at the end of each power transfer interval. Circuitry having a first input connected to the input for sensing the input voltage, and a second input connected to the output for sensing the output voltage, may provide a signal proportional to a difference between the output voltage and a scaled replica of the input voltage and the switch controller may use the signal to monitor the load current. The temperature may be sensed and the signal may be adjusted to compensate for variations in an output resistance of the power conversion as a function of the temperature.

[0010] The switch controller may include a gate drive circuit including a gate drive source having a positive terminal and a negative terminal, an inductor having a first end and a second end, a plurality of gate drive switches, including a first, a second, a third, and a fourth gate drive switch, connected to drive the inductor, and a switch controller connected to operate the gate drive switches in a series of driver operating cycles. The driver operating cycles may include a first interval during which the first and fourth gate drive switches are ON and connect the first end of the inductor to the positive terminal and a second end of the inductor to the negative terminal during which an average positive current flows through the inductor; a first transition following the first interval during which the first and fourth gate drive switches are turned OFF and the current flowing in the inductor charges and discharges capacitances coupled to the inductor; a second interval during which the second and third gate drive switches are ON and connect the second end of the inductor to the positive terminal and the first end of the inductor to the negative terminal during which an average negative current flows through the inductor; a second transition following the second interval during which the second and third gate drive switches are turned OFF and the current flowing in the inductor charges and discharges capacitances coupled to the inductor. The driver operating cycles may be characterized by a driver operating period. The switch controller may be configured to adjust the duration of the operating period, the duration of the first and second intervals, and the duration of the first and second transitions. At least one of the capacitances coupled to the inductor may include an input capacitance associated with one or more of the primary switches.

[0011] The output circuitry may include one or more secondary switches and at least one of the capacitances coupled to the first and second ends of the inductor may include an input capacitance associated with one or more of the secondary switches. The output circuitry further may include one or more secondary switches. The inductor may be a transformer having a primary winding and one or more secondary windings coupled to one or more of the power train switches and the capacitances may include one or more input capacitances associated with the one or more power train switches. The driver operating cycle may include a clamp interval during which the second and fourth gate drive switches are ON, the first and second ends of the inductor are both connected to the negative terminal, and current flows through the inductor. A representation of the load current, I_L, may be produced. The controller may adjust the duration of the clamp interval as a function of the representation. The controller may adjust the duration of the driver operating cycle as a function of the representation. The controller may adjust the duration of the first and second intervals as a function of the representation. The controller may adjust the duration of the driver operating cycle, the duration of the first and second intervals, and the duration of the first and second transitions as a function of the representation. The controller may adjust the duration, T_PTI, of each power transfer interval, and the duration of each energy recycling interval as a function of the representation. A current monitor having a first input connected to monitor the input voltage and a second input connected to monitor the output voltage, may perform a scaling function to reduce at least one of the first or second inputs by a predetermined ratio, R, may produce a no-load reference value, may determine a difference value between the first or second input and the no-load reference value, and may scale the difference value to provide the representation of the load current, I_L. The no-load reference value may equal V_IN multiplied by R. The predetermined ratio, R, may be an integer multiple of the voltage transformation ratio, K. Circuitry having a first input connected to the input for sensing the input voltage, a second input connected to the output for sensing the output voltage, may provide a signal proportional to a difference between the output voltage and a scaled replica of the input voltage and the switch controller may use the signal to monitor the load current. The signal may be adjusted to compensate for variations in an output resistance as a function of sensing the temperature.

[0012] Alternate embodiments of the above exemplary methods may include one or more of the following features. The inductor may be a transformer having a primary winding and one or more secondary windings each coupled to one or more power train switches. The capacitances may include one or more input capacitances associated with the one or more power train switches. The driver operating cycle may include a clamp interval during which the second and fourth gate drive switches are ON and the first end and second end of the inductor are both connected to the negative terminal and a current flows through the inductor. A representation of the output current of the power converter may be produced. The controller may adjust the duration of the clamp interval as a function of the representation. The controller may adjust the duration of the operating period as a function of the representation. The controller may adjust the duration of the first and second intervals as a function of the representation. The controller may adjust the duration of the operating period, the duration of the first and second intervals, and the duration of the first and second transitions as a function of the representation. The controller may adjust the converter operating period, the power transfer interval duration, and the energy recycling interval duration in the power converter as a function of the representation.

[0013] Alternate embodiments of the above exemplary methods and apparatus may include one or more of the following features. The temperature of the power converter may be sensed and the signal may be adjusted to compensate for variations in the output resistance as a function of the temperature.

[0022] A DC transformer as defined herein delivers a DC output voltage, Vout, which is a fixed fraction of the voltage, Vin, delivered to its input and optionally provides isolation between its input and its output. The voltage transformation ratio or voltage gain of the DC transformer (defined herein as the ratio, K=Vout/Vin, of its output voltage to its input voltage at a load current) is fixed by design, e.g. by the converter topology, its timing architecture, and the turns ratio of the transformer included within it. A category of DC transformer topologies, called Sine Amplitude Converters (“SACs”), are described in Vinciarelli, Factorized Power Architecture with Point of Load Sine Amplitude Converters, U.S. Pat. No. 6,930,893 issued Aug. 16, 2005; and in Vinciarelli, Point of Load Sine Amplitude Converters and Methods, U.S. Pat. No. 7,145,786 issued on Dec. 5, 2006, each assigned to VLT, Inc. and incorporated herein by reference in their entirety (the “SAC patents”). As disclosed in the SAC patents, a SAC operating cycle comprises two power transfer intervals (“PTI”), during which energy is transferred to the output by means of a substantially sinusoidal current characterized by a resonant frequency determined by component values within the SAC, and two energy recycling intervals, which may also be called “ZVS intervals,” during which a transformer magnetizing current charges and discharges capacitances within the converter, thereby reducing or eliminating the voltage across a switch before it is turned ON, reducing switching losses in the converter. As also disclosed and illustrated in the SAC patents, the waveform of the rectified transformer secondary current in such a converter comprises a series of unidirectional half-sinusoidal pulses separated from one another by a ZVS interval. The amplitude of the half-sinusoidal pulses increases with increasing load. The operating frequency, the duration of each PTI, and thus the peak-to-peak magnetizing current in the converter may be substantially constant.

[0023] A clamped capacitor variation of the SAC topology is described in Vinciarelli, Clamped Capacitor Resonant Power Converter, U.S. Pat. No. 9,325,247 issued on Apr. 26, 2016, assigned to VLT, Inc. and incorporated herein by reference in its entirety (the “CSAC patent”). As described in the CSAC patent, clamp switch circuitry may be connected across the resonant capacitor and operated during a clamp interval to short the resonant capacitor at or near the peak of the resonant current, i.e. between quarter resonant periods in the converter operating cycle. The effect of the clamp interval increases the ON time of the switches, extending the effective duration of the PTI, and reducing the effective series resistance of the converter, for more efficient operation under high load conditions. The peak-to-peak magnetizing current in the CSAC may therefore increase with introduction of the clamp interval. Familiarity with the basic timing architecture of the SAC and CSAC topologies (as described in the SAC patents and the CSAC patent) is assumed in the following description.

[0024] FIGS. 1A and 1B respectively show schematics of an isolated 100 and non-isolated 100B half-bridge Adaptive Sine Amplitude Converter (“ASAC”) configured to reduce power dissipation in the converter while converting power received from source 50 for delivery to load 60 at light to no-load conditions. The ASAC 100, 100B may include a resonant capacitance C_R 112; resonant inductance L_R 114; a transformer T 115 having a primary winding 116 and secondary winding 117, the ratio of the primary turns to secondary turns defining a turns ratio, N, for the transformer; primary switches S1 102, S2 104, connected to drive the primary winding 116, secondary switches SR1 106, SR2 108, connected to rectify current from the secondary winding 117 for delivery to the load 60, each of the primary and secondary switches may include a respective diode 103, 105, 107, 109 (which may be an intrinsic part of the switch, as in a MOSFET, or which may be a discrete diode connected across the switch); input filter capacitors 110, 111 and output filter capacitor 113. The resonant inductor L_R may comprise the leakage inductance of transformer T 115 either alone or in combination with other inductances, e.g. parasitic or component inductors external to the transformer. An ASAC controller 120 controls the timing of the opening and closing of the primary (S1, S2) and secondary (SR1, SR2) switches.

[0025] In operation, the ASAC controller 120 may actively adapt the operating cycle, including the duration of the power transfer intervals, T_PTI, to reduce power dissipation in the ASAC, particularly at light to no load conditions as explained below. FIG. 3A shows an adaptive relationship which may be used by the ASAC controller to vary the duration of the PTI, T_PTI, as a function of load to reduce losses at light or no-load conditions. As shown in FIG. 3A, the ASAC controller may operate the switches to: (a) use a minimum duration PTI, T_PTI-min, for load levels less than or equal to a first threshold, I_L1; (b) use a full duration PTI, T_PTI-Full, for load levels greater than or equal to a second threshold, I_L2; and (c) vary the duration of the PTI between the minimum, T_PTI-min, and the full, T_PTI-Full, durations as the load varies between the first threshold, I_L1, and the second threshold, I_L2. The preferred ranges for T_PTI-Full, T_PTI-min, I_L1, and I_L2 will be described in greater detail below.

[0026] Steady-state waveforms for the current, I_PRI, flowing in the primary winding 116 of the ASAC topology of FIGS. 1A and 1B operating at a constant load are shown for three different load levels in FIGS. 2A through 2C (the input voltage is assumed to be constant for all three examples). Note that FIGS. 2A through 2C are intended to show generalized approximations of actual behavior and as such are not intended to reflect, nor should they be interpreted to represent, unnecessary detail. FIG. 2A shows the current, I_PRI, at a high load level, e.g. I_Load greater than or equal to a second threshold load current, I_L2 (I_Load≥I_L2). FIG. 2B shows the current, I_PRI, at an intermediate load level, e.g. I_Load greater than a first threshold load current, I_L1, and less than the second threshold load current, I_L2, (I_L1<I_Load<I_L2). And FIG. 2C shows the current, I_PRI, at a low load level, e.g. I_Load less than the first threshold load current, I_L1 (I_Load≤I_L1). As shown, the peak current, I_pk-a, in FIG. 2A is greater than the peak current, I_pk-b, in FIG. 2B, which in turn is greater than the peak current, I_pk-c, in FIG. 2C illustrating the relative load conditions.

[0027] In FIGS. 2A through 2C, each converter operating cycle is shown having a respective duration, T_OP, beginning at time t₀, and includes two half-cycles, each beginning respectively at time t₀ and at respective time t₃, and each including a PTI and an ERI. Just prior to t₀, all switches are OFF and the primary current I_PRI is substantially equal to the peak negative value of the magnetizing current, I_PRI(t₀)=(the magnetizing current, I_MAG(t) or I_M is illustrated by the dashed current waveform in FIGS. 2A and 2B and by the solid line in FIG. 2C). During each PTI the primary current is the sum of the load dependent resonant current reflected to the primary, I_O(t)/N, which rings up sinusoidally at the characteristic resonant frequency, f_R=1/(2*π*sqrt(L_R*C_R)), of the resonant circuit, and the magnetizing current, I_M: I_PRI(t)=I_O(t)/N+I_MAG(t). Suffixes a, b, and c, have been added to time notations, e.g. t_3a, t_3b, and t_3c, in FIGS. 2A, 2B, and 2C, to indicate analogous points in the waveforms and may be referenced generically in the following description by omitting the letter suffix, e.g. respective time t₃.

[0028] In the example shown in FIGS. 1A, 1B, and 2A-C, primary switch S1 102 and secondary switch SR1 106 are ON during the first PTIs (the PTIs starting at t0) and primary switch S2 104 and secondary switch SR2 108 are ON during the second PTIs (the PTIs starting at T3). The start of each ERI, begins when the primary switch that was ON during the immediately preceding PTI is turned OFF. The current flowing in the primary winding during the ERI, e.g. the magnetizing current, I_M, charges and discharges capacitances associated with the primary switching node, VS, reducing the voltage across the other primary switch before it is turned ON in the immediately succeeding PTI for full or partial ZVS turn ON. If the combination of magnetizing energy and the ERI duration are sufficient, the capacitances associated with each switch may be substantially charged and discharged enabling each to be turned ON at substantially zero volts without switching losses associated with discharging of charged circuit capacitances. The ERI, as well as the first half-cycle, may end at time t₃ when switches S2 104 and SR2 108 are turned ON initiating the second half cycle. As shown in FIGS. 2A through 2C, the progression of the second half-cycle between times t₃ and t₆ is the same as the progression of the first half-cycle, the difference being the polarity of the voltages and currents during the respective intervals. The converter operating cycle ends at time t₆, with the completion of the ZVS interval of the second half-cycle.

[0029] At time t₀ primary switch S1 may be turned ON initiating a PTI. As shown in FIGS. 2A, 2B, the primary current during each PTI is the sum of the (a) primary-reflected secondary current, I_O(t)/N, and (b) magnetizing current, I_MAG (shown as a dashed line): I_P(t)=I_O(t)/N+I_MAG(t). With the primary switch S1 102 ON, one half of the input voltage, V_IN, is impressed across the series circuit including C_R 112, L_R 114, and primary winding 116, causing: the output current I_O(t) and thus the primary-reflected output current, I_O(t)/N, to ring up sinusoidally at the characteristic resonant frequency f_R=1/(2*π*sqrt(L_R*C_R)); and current to build in the magnetizing inductance of the transformer, I_M, during the PTI, increasing (or decreasing) from its approximate negative (or positive) peak at the beginning of the PTI to its approximate positive (or negative) peak at the end of the PTI. As shown in FIGS. 2A and 2B, at time t₁, e.g. t_1a, t_1b, the resonant portion of the primary current I_O(t)/N reaches a peak, the value of which increases with the magnitude of the average current drawn by the load 60, at a time which essentially coincides with the magnetizing current passing through zero. The primary current in the examples of FIG. 2A and FIG. 2B reaches peak values of I_pk-a, −I_pk-a, and I_pk-b, −I_pk-b, respectively which also represent the resonant peak current since the magnetizing current, I_MAG, is essentially zero at time T₁. By contrast, the primary current as depicted in FIG. 2C, representing operation of the ASAC at no-load: I_L=0≤I_L1, includes only the magnetizing current component because the load current and thus the primary-reflected load current, are zero. As shown, the magnetizing current reaches its peak, I_M-pk, −I_M-pk, in all three examples after the PTI ends.

[0030] As shown in FIG. 2A representing operation of the ASAC at a high load condition (I_Load≥I_L2: FIG. 3A) that generally coincides with the constant ON time control described in the SAC patents, the ASAC controller operates the switches to establish the power transfer intervals, PTI-A, with a duration, T_PTI-A=T_PTI-Full, which, in a preferred embodiment, is approximately equal to one half of the characteristic resonant period, T_R/2, (T_PTI-A=T_PTI-res=T_R/2) allowing the resonant portion of the primary current to return to substantially zero for ZCS of the secondary switches and near ZCS of the primary switches. Near ZCS because only magnetizing current is flowing when the primary switches are turned ON and OFF. For example, at time t₀, the ASAC controller closes primary switch S1 102 initiating power transfer interval, PTI-A, when the magnitude of I_O is zero and the primary current I_P is substantially equal to the peak negative value of the magnetizing current, I_P(t₀)=−I_M-pk=−I_M-pka. Similarly, the ASAC controller opens switch S1 at time t_2a when the magnitude of I_O is zero and the primary current I_P is substantially equal to the peak positive value of the magnetizing current, I_P(t₀)=+I_M-pk=+I_M-pka, ending PTI-A and beginning ERI-A.

[0031] Operation of the ASAC will now be described in connection with the waveform in FIG. 2B which represents an intermediate load condition (I_L1<I_Load<I_L2: FIG. 3A). The ASAC controller may turn switch S1 102 ON at time t₀ initiating power transfer interval, PTI-B. As shown, the primary current rings up sinusoidally at the characteristic resonant frequency, reaching its peak at the same time, t1, (t_1a=t_1b) as shown in FIG. 2A illustrating the same characteristic resonant frequency. However, as illustrated in FIG. 2B, the ASAC controller turns primary switch S1 102 OFF at time, t_2b, ending power transfer interval PTI-B before the resonant current rings down to zero, resulting in a duration, T_PTI-B, that is shorter than the duration, T_PTI-A, of PTI-A. Turning OFF switch S1 102 earlier than one half of the characteristic resonant period, T_R/2, after the start of the PTI, e.g. at time, to, (T_PTI-B<T_PTI-res=T_R/2), truncates the resonant current before the end of the half-cycle as shown in FIG. 2B at time t_2b, where the primary current is shown abruptly decreasing to the level of the magnetizing current. The resulting loss of ZCS (beyond the level of magnetizing current) with the truncated PTI, may be a worthwhile tradeoff for the resulting reduction in the peak level of the magnetizing current, which in turn can reduce permeable-core losses and conduction losses in the switches and windings, increasing overall efficiency at light loads. Reduced magnetizing current increases ERI-B, the time necessary to charge and discharge the capacitances associated with the switching node VS during the energy recycling intervals, which are accordingly illustrated with a longer duration in FIG. 2B compared to ERI-A in FIG. 2A.

[0032] A low load condition (I_Load<I_L1 in FIG. 3A) may be represented by the primary current waveform shown in FIG. 2C. As described below, FIG. 2C more specifically represents a no-load condition (which also meets the more generalized condition shown in FIG. 3A) in an ASAC having ideal components which results in zero resonant current throughout the power transfer interval, PTI-C: I_RES-PTI-C, =I_O(t)/N=0. The ASAC controller may turn switch S1 102 ON at time t₀ initiating power transfer interval, PTI-C. As shown the primary current ramps up linearly while switch S1 is ON from time t₀ to time t_2c. Because the load is zero and the components are assumed to be ideal, no resonant current flows as shown in FIG. 2C. As illustrated in FIG. 2C, the ASAC controller turns primary switch S1 102 OFF at time, t_2c, ending power transfer interval PTI-C, resulting in a duration, T_PTI-C, that is even shorter than the duration, T_PTI-B, of PTI-B. Turning OFF switch S1 102 even earlier, further reducing the duration of the PTI, further reduces the peak magnetizing current, I_M-pk. As shown, the peak magnetizing current, I_M-pk is at the highest level, I_M-pk-a, in the example of FIG. 2A, the lowest level, I_M-pk-c, in the example of FIG. 2C, and an intermediate level, I_M-pk-b, in the example of FIG. 2B, illustrating the dependency on the duration of the PTI, which is shown as the longest in FIG. 2A, shortest in FIG. 2C, and intermediate duration in FIG. 2B. Note that the waveforms of FIGS. 2A through 2C assume that the input voltage is the same for all three examples.

[0033] The even lower magnetizing current in the example FIG. 2C requires even more time to charge and discharge the capacitances associated with the switching node VS during the energy recycling intervals, thus intervals, ERI-C, are shown with an even longer duration in FIG. 2C (compared to ERI-B in FIG. 2B). The inverse relationship between the PTI duration (and consequent change in magnetizing current) and the ERI duration partially offset each other allowing the converter operating period, T_OP, to remain within a relatively narrow range as illustrated in FIGS. 2A through 2C. In one example, an ASAC having a characteristic resonant period of 100 nS, may be operated at high loads (I_Load≥I_L2: FIG. 3A) with an operating period, T_OP-A=250 nS, (F_OP=4 MHz), a PTI duration, T_PTI-A=96 nS, and an ERI duration, T_ERI-A=29 nS as shown in FIG. 2A; and at light load to no load (I_Load<I_L1: FIG. 3A) with an operating period, T_OP-c=204 nS, (F_OP=5 MHz), a PTI duration, T_PTI-C=59 nS, and an ERI duration, T_ERI-C=44 nS as shown in FIG. 2C. Thus a nearly forty percent reduction in PTI duration may result in only twenty percent reduction in operating period thanks to the increase in ERI duration.

[0034] As described above, terminating the PTIs early reduces the magnetizing current flowing in the transformer, thus reducing power dissipation in the core and in the windings, potentially improving efficiency of the converter, e.g. at reduced loads. Increasing the duration of the ERIs helps maintain the converter operating period within a relatively narrow range even with large reductions in the PTI duration.

[0035] FIG. 3A shows the relationship between load and PTI duration between I_L1 and I_L2 as essentially linear, however any suitable relationship may be used. In a preferred embodiment, the ASAC controller may use the following ranges for the parameters shown in FIG. 3A: (a) the minimum PTI duration, T_PTI-min, may preferably be in the range of 60 to 75 percent of the half resonant period (0.6*T_R/2)≤T_PTI-min≤(0.75 T_R/2), but may be 50 percent or even lower; (b) the full PTI duration, T_PTI-Full, may preferably be in the range of 95 to 100 percent of the half resonant period, (0.95*T_R/2)≤T_PTI-Full≤(T_R/2), but T_PTI may exceed this upper limit with the clamp capacitor methods described in the CSAC patent (e.g. as shown in FIG. 3B and discussed below, T_PTI may vary between T_PTI-Full and T_PTI-max for operation as a CSAC); (c) the lower current threshold, I_L1, may be between 0 and 5 or 10 percent of the full load current, 0≤I_L1≤0.05 to 0.10*(d) the upper current threshold, I_L2, for ASAC operation may be between 20 and 100 percent of the full load current, 0.2*I_L-max≤I_L1≤I_L-max. The ASAC controller may additionally adjust the timing to control the level of current chop in the primary switches over the load range, I_PRI(T_PTI)=I_Chop-set. For example, the controller may adjust the PTI duration to control the level of primary current at the end of the PTI, e.g. turning the primary switches OFF earlier to decrease the level of magnetizing current, I_MAG, and increase the level of resonant current, I_RES, being chopped or later to increase the level of magnetizing current, I_MAG, and decrease the level of resonant current, I_RES, being chopped: Ipri(PTI-end)=Imag(PTI-end)+Ires (PTI-end)=I_Chop-set. The controller may maintain a constant current chop, I_Chop-Set=constant, or ensure that a predetermined maximum current chop is not exceeded, I_Chop-set<maximum. For example, the controller may limit the duration of the PTI even at high loads thus increasing the level of current chopped by turning OFF the primary switches early, e.g. to reduce power loss in the converter.

[0036] Referring to FIGS. 4A and 4B an improved gate-drive circuit 150 for controlling the primary and secondary switches of an ASAC is shown having four gate-drive switches, Q1 121, Q2 122, Q3 123, Q4 124, connected in a full-bridge configuration driving the primary winding 126 of gate-drive transformer 125. Power-train switches not requiring isolation and having a ground-referenced control terminal, such as primary switch S2 in FIG. 1A or secondary switches in non-isolated power trains such as secondary switches SR1 and SR2 in FIG. 1B, may be driven directly by nodes GA and GB of the gate-drive circuit. The remaining power-train switches such as floating switches (e.g. primary switch S1 in FIGS. 1A and 1B) and secondary switches in isolated power trains (e.g. SR1 and SR2 in FIG. 1A) may be driven by a respective secondary winding, e.g. secondary windings 127, 128, and 129 (FIG. 4A) and 127B (FIG. 4B) of the gate-drive transformer 125 (FIG. 4A), 125B (FIG. 4B). For example, in the isolated power train 140 of FIG. 1A using the driver 150 of FIG. 4A, primary switch S1 may be driven by secondary winding 127 signal GFA, ground-referenced primary switch S2 may be driven directly by node GB, secondary switch SR1 may be driven by secondary winding 128 signal GFA, and secondary switch SR2 may be driven by secondary winding 129 signal GFB. In the non-isolated power train 140B of FIG. 1B using the driver 150B of FIG. 4B, primary switch S1 may be driven by secondary winding 127B signal GFA, ground-referenced primary switch S2 and secondary switch SR2 may be driven directly by node 131 signal GB, and ground-referenced secondary switch SR1 may be driven directly by node 130 signal GA. In another non-isolated example, ground-referenced primary switch S2 may also be driven by a secondary winding (not shown in FIG. 4B) for symmetry with floating primary switch S1. Note the driver 150B may be simplified to use a gate-drive transformer 125B having a single secondary winding 127B as shown in FIG. 4B for use with the non-isolated half-bridge ASAC 100B. Power to the full bridge is supplied by the gate-drive bias input, Vg-drv. Note that the polarity and turns ratios of the secondary windings 127, 128, and 129 (FIG. 4A) and 127B (FIG. 4B) may be configured to ensure, and the following discussion assumes, that the switches connected to be controlled by voltages GFA and GFB operate at times that essentially coincide with the timing of switches connected to be controlled directly by voltages GA and GB.

[0037] Pulse blocks U1, U2, U3, and U4 each generate an output pulse having a respective duration, tp1, tp2, tp3, tp4, when triggered by an input signal. The output of each pulse block is connected to the control terminal of a respective gate-drive switch Q1, Q2, Q3, Q4. The respective pulse duration, tp1, tp2, tp3, tp4, of each pulse block may be controlled independently, e.g. by a digital or analog input signal (not shown) to each pulse block. Delay blocks U5, U6, U7, and U8, when triggered by an input signal, each provide an output signal after a respective delay, td5, td6, td7, td8. The delay td5, td6, td7, td8 for each delay block, U5, U6, U7, and U8, may be set independently, e.g. by an analog or digital input signal (not shown) to each delay block. The ON time of each of the gate-drive switches, Q1, Q2, Q3 and Q4 is thus controlled by pulse blocks U1, U2, U3, and U4, i.e. tp1, tp2, tp3, and tp4, respectively. The idealized waveforms, 5A, 5B, 5C, and 5D in FIGS. 5 and 6A, 6B, 6C, and 6D in FIG. 6, are therefore also representative of the respective states of gate-drive switches Q1, Q2, Q3, and Q4, with a high waveform signal representing the ON state and a low waveform signal representing the OFF state.

[0038] Operation of the gate-drive control circuit of FIGS. 4A and 4B will be explained in connection with the waveforms of FIGS. 5 and 6. Referring to waveforms 5A and 5B in FIG. 5, the duration of the operating cycle, Top-A (FIG. 5), Top-B (FIG. 6) of the converter may be set by pulse blocks U2 and U4 and delay blocks U6 and U8. The output of U2 turns OFF at time tx1, triggering delay block U8, which after the delay, td8, at time tx2 (tx2=tx1+td8) triggers pulse block U4, which in turn outputs a pulse having a duration tp4 beginning at time tx2 and ending at time tx5. At time tx5 (tx5=tx2+tp4), the output pulse of U4 ends, triggering delay block U6. After the delay, td6, at time tx6 (tx6=tx5+td6), pulse block U2 outputs a pulse having a duration tp2 beginning at time tx6 and ending after tp2, at time tx9=tx6+tp2=tx1+Top, which marks the end of the cycle and the beginning of the next cycle, e.g. triggering delay block U8, etc. Accordingly, the operating period may be set by the sum of these four time parameters, pulse durations, tp2 and tp4, and delays td6 and td8.

[0039] Referring to FIG. 5, the output of U2 resets at time tx1 turning switch Q2 OFF, and triggering delay blocks U8 and U5 (as shown in FIGS. 4A, 4B, and 5) starting a new operating cycle, and allowing the current that is flowing in primary winding 126 and in the secondary windings to respectively charge node 130 and nodes connected to GFA toward the potential of Vdrv and continue to discharge node 131 toward ground and nodes connected to GFB to their respective minima. At time t0 corresponding with t0 in FIG. 2A-2C, the voltages GFA across windings 127 and 128 (FIG. 4A) and 127B (FIG. 4B) (all corresponding with direct coupled node 130, GA) reach the level Vt necessary to turn ON their respective power-train switches, primary switch S1 and secondary switch SR1 in the isolated example of FIGS. 1A & 4A. With power-train switches S1 and SR1 ON, a power transfer interval in the power train 140 begins with the current, Ipri, (waveform 5G) in the primary winding 116 of transformer 115 (FIG. 1A) and secondary current, Isec, (waveform 5H) in the secondary winding 117 increasing as shown in FIG. 5 (and as discussed above in connection with FIG. 2A). It should be appreciated that the capacitances associated with the control terminals of the power-train switches, e.g. gate capacitance of MOSFETS, being connected to the gate-drive nodes directly (nodes 130, 131) or through transformer windings (nodes GFA, GFB), will be discharged and charged during the transition of voltages GA, GFA and GB, GFB described in connection with FIGS. 4A and 4B.

[0040] After the delay, td8, of delay block U8, i.e. at time tx2 (tx2=tx1+td8), delay block U8 outputs a signal triggering pulse block U4 which turns gate-drive switch Q4 ON, connecting node 131 to ground. Note that FIG. 5 is intended to show generalized approximations of actual behavior and as such is not intended to reflect, nor should they be interpreted to represent, unnecessary detail. For example, time tx2 and time t0 occur close in time as illustrated in FIG. 5, however, the two are not directly correlated in the controller shown in FIGS. 4A and 4B, e.g. tx2 is controlled by td8 while t0 is controlled by many factors including tx1, the threshold Vt, the magnitude of current flowing in the gate drive transformer, and the cumulative capacitance on the gate drive node. Under ideal conditions, node 131 will be discharged to the ground potential (GB=0), allowing gate-drive switch Q4 to be turned ON with zero voltage across it for full ZVS operation at time tx2. After the delay, td5, of delay block U5 at time tx3 (tx3=tx1+td5), delay block U5 outputs a signal triggering pulse block U1 which turns gate-drive switch Q1 ON. Under ideal conditions, node 130 will be charged to the potential of Vdrv (GA=Vdrv), allowing gate-drive switch Q1 to be turned ON with zero voltage across it for full ZVS operation at time tx3. Although shown as substantially different, delays td5 and td8 may be nearly the same, causing tx2 and tx3 to be nearly coincident. With gate-drive switches Q1 and Q4 ON, at time tx3 gate-drive signals GA and GFA are at their maximum (GA=Vdrv) and signals GB and GFB are at their minimum (GB=0). Current flowing through the primary winding of the gate drive transformer reverses direction after tx3.

[0041] The output of U1 resets after the duration, tp1, at time tx4 (tx4=tx3+tp1) turning gate-drive switch Q1 OFF, allowing the current flowing in the primary winding 126 of the gate-drive transformer 125 to discharge node 130, causing the voltage GA to decrease toward ground potential and the current flowing in the secondary windings 127 and 128 to discharge the secondary nodes GFA to decrease toward their respective minima. At time t2a corresponding with t2a in FIG. 2A, the voltages across secondary windings 127 and 128 (FIG. 4A) and 127B (FIG. 4B) (all corresponding with direct coupled node 130, GA) reach the level Vt which turns their respective power-train switches OFF, e.g. S1 and switch SR1 in the isolated example, ending the PTI and beginning the ERI transition of power-train node VS (FIGS. 1A, 1B) for ZVS operation of power-train switch S2. Note that time tx5 and time t2a occur close in time as illustrated in FIG. 5, however, the two are not directly correlated in the controller shown in FIGS. 4A and 4B, e.g. tx5 is controlled by tp4 while t2a is controlled by many factors including tx4, the threshold Vt, the magnitude of current flowing in the gate drive transformer and the cumulative capacitance on the gate-drive node.

[0042] The output of U4 resets after the duration, tp4, at time tx5 (tx5=tx2+tp4), triggering delay blocks U6 and U7 and turning gate-drive switch Q4 OFF, allowing the current flowing in the primary winding 126 of the gate-drive transformer 125 to charge node 131, causing the voltage GB to increase toward its maximum (Vdrv) and the current flowing in the secondary winding 129 to charge the secondary node GFB to increase toward its maximum. At time t3a corresponding with t3a in FIG. 2A, the voltage GB at node 131 reaches the level Vt which turns power-train switch S2 ON (and the voltage GFB reaches a level that turns power-train switch SR2 ON), ending the ERI and beginning the next PTI of the power train (FIGS. 1A and 1B). With power-train switches S2 and SR2 ON, a power transfer interval in the power train begins with the current, Ipri, (waveform 5G) in the primary winding 116 of transformer 115 (FIGS. 1A, 1B) decreasing and secondary current, Isec, (waveform 5H) in the secondary winding 117 increasing as shown in FIG. 5 (and as discussed above in connection with FIG. 2A).

[0043] After the delay, td6, of delay block U6, i.e. at time tx6 (tx6=tx5+td6), delay block U6 outputs a signal triggering pulse block U2 which turns gate-drive switch Q2 ON, connecting node 130 to ground. Note that time tx6 and time t3a occur close in time as illustrated in FIG. 5, however, the two are not directly correlated in the controller shown in FIGS. 4A and 4B, e.g. tx6 is controlled by td6 while t3a is controlled by many factors including tx5, the threshold Vt, the magnitude of current flowing in the gate drive transformer, and the cumulative capacitance on the gate drive node. Under ideal conditions, node 130 will be discharged to the ground potential (GA=0), allowing gate-drive switch Q2 to be turned ON with zero voltage across it for full ZVS operation at time tx6. After the delay, td7, of delay block U7 at time tx7 (tx7=tx5+td7), delay block U7 outputs a signal triggering pulse block U3 which turns gate-drive switch Q3 ON. Under ideal conditions, node 131 will be charged to the potential of Vdrv (GB=Vdrv), allowing gate-drive switch Q3 to be turned ON with zero voltage across it for full ZVS operation at time tx7. Although shown as substantially different, delays td6 and td7 may be nearly the same, causing tx6 and tx7 to be nearly coincident. With gate-drive switches Q2 and Q3 ON, at time tx7 gate-drive signals GB and GFB are at their maximum (GB=Vdrv) and signals GA and GFA are at the minimum (GA=0). Current flowing through the primary winding of the gate drive transformer reverses direction after tx7.

[0044] The output of U3 resets after the duration, tp3, at time tx8 (tx8=tx7+tp3) turning gate-drive switch Q3 OFF, allowing the current flowing in the primary winding 126 of the gate-drive transformer 125 to discharge node 131, causing the voltage GB to decrease toward ground potential and the current flowing in the secondary winding 129 to discharge the secondary node GFB to decrease toward its minimum. At time t5a corresponding with t5a in FIG. 2A, the voltage GB at node 131 reaches the level Vt which turns power-train switch S2 OFF (and the voltage GFB reaches a level that turns power-train switch SR2 OFF), ending the PTI and beginning the ERI transition of power-train node VS (FIGS. 1A, 1B) for ZVS operation of power-train switch S1. The output of U2 resets after the duration, tp2, restarting the operating cycle at time tx1+Top (tx1+Top=tx6+tp2). Note that time tx1 and time t5a occur close in time as illustrated in FIG. 5, however, the two are not directly correlated in the controller shown in FIGS. 4A and 4B, e.g. tx1 is controlled by tp2 while t5a is controlled by a variety of factors including tx8, the threshold Vt, the magnitude of current flowing in the gate drive transformer, and the cumulative capacitance on the gate-drive node.

[0045] To summarize, the PTI duration of the power train, which comprises tp1 and tp3, may be shortened or extended by varying tp1 and tp3 of pulse blocks U1 and U3, respectively, while also varying the parameters of other pulse blocks, U2 and U4, and delay blocks, U5, U6, U7 and U8. The overall operating period of the converter may be controlled using the parameters, tp2, tp4, td6, and td8. The ERI durations in the power train, and its ZVS operation with varying PTI duration, may be controlled using tp1, tp2, tp3, tp4, td5, td6, td7 and td8. However, these eight parameters are not independent of one another since, in steady state operation, symmetry between complementary PTIs and ERIs, causes essential equality between tp1 and tp3, tp2 and tp4, td5 and td7, and tp6 and tp8, thus reducing the number of independent control parameters from eight to four. With its operational timing parameters, the gate-drive control circuits of FIGS. 4A and 4B control the PTI duration of the power train and the ERI duration of the power train, thus controlling the overall operating period of the ASAC topology, as well as the duration of the ZVS transitions of GA and GB. As such, the gate-drive control circuits of FIGS. 4A and 4B enable ZVS operation of the S1, S2, SR1 and SR2 power switches under varying ASAC operating conditions, as well as ZVS operation of the Q1, Q2, Q3 and Q4 gate drive switches. ZVS operation of power train switches and gate drive switches improves efficiency under a broad range of ASAC operating conditions. Timing parameters may be digitally set, and adaptively reset, using look-up tables as a function of converter load.

[0046] Referring to FIG. 6, waveforms 6A through 6H illustrate operation of the gate-drive circuit for controlling the switches in the ASAC for an intermediate load condition (I_L1<I_Load<I_L2: FIG. 3A) in which, consistent with the operation discussed above in FIG. 2B, the primary switch S1 102 is turned OFF at time, t_2b, ending power transfer interval PTI-B before the resonant current rings down to zero, resulting in a duration, T_PTI-B, that is shorter than one half of the characteristic resonant period, T_R/2 (T_PTI-B<T_R/2). As shown in waveforms 6C and 6D of FIG. 6, the durations, tp1 and tp3, of pulse blocks U1 and U3 have been shortened relative to that shown in FIG. 5, turning OFF switches Q1 and Q3 earlier. As a result, gate-drive voltages GA, GFA and GB, GFB begin declining earlier reaching the control voltage, Vt, earlier, and thus turning OFF the respective power-train switches earlier, truncating the PTIs as illustrated in waveforms 6G and 6H. The secondary switches SR1 and SR2 may be turned OFF at the same time as their respective primary switches S1 and S2. In the example shown in FIG. 6, the duration of the energy recycling intervals, ERI-B may also be lengthened, e.g. using the timing parameters, pulse durations, tp1-tp4 and time delays, td5-td8, illustrated in the gate-drive control circuits of FIGS. 4A and 4B, providing flexibility for controlling the various timing relationships of the ASAC power train under different operating conditions. Note that FIG. 6 is intended to show generalized approximations of actual behavior and as such is not intended to reflect, nor should the approximations be interpreted to represent, unnecessary detail. For example, times tx2 and t0, and times tx6 and t3b respectively occur close in time as illustrated but are not directly correlated as explained above in connection with FIG. 5.

[0047] As shown in the examples of FIGS. 5 and 6, the gate drive circuits 150, 150B may control the rise and fall of the gate drive voltages, e.g. GA, GB, independently of each other. In the example of FIG. 5, the voltage GB rises before the voltage GA falls to ground thus reducing the time that the power train switches, e.g. S1 and S2 are both OFF. In the example for FIG. 6, the voltage GB rises after the voltage GA falls to ground thus increasing the time that the power train switches, e.g. S1 and S2 are both OFF. The gate drive circuits 150, 150B of FIGS. 4A and 4B may be further modified to provide clamping of the gate drive transformer for extended periods with the gate drive voltages GA, GB to remain at ground potential. For example a modified gate drive circuit 150C shown schematically in FIG. 4C is similar to the driver 150B in FIG. 4B, but includes additionally circuitry to allow gate drive switches Q2 and Q4 to be operated simultaneously to clamp the gate drive transformer 125B.

[0048] Referring to FIG. 4C, gate drive circuit 150C includes pulse blocks U1, U2, U3, and U4, delay blocks U5, U6, U7, and U8, which function as described above in connection with FIG. 4B. In addition, the gate drive circuit 150C includes AND gates U21 and U22, pulse blocks U11, U13, U16, and U18, delay blocks U12 and U17, and OR gates U9, U10, U14, and U19 to generate timing control signals for implementing the clamp. In FIG. 4C, the clamp timing circuitry (AND gates U21 and U22, pulse blocks U11, U13, U16, and U18, delay blocks U12 and U17, and OR gates U9, U10, U14, and U19) allows driver 150C to operate Q2 and Q4 simultaneously during a driver clamp phase when enabled and subsequently return to the normal timing cycle (as described above in connection with FIGS. 5A and 5B) established by U1, U2, U3, U4, U5, U6, U7, and U8. With the Clamp Enable signal LOW (disabled), the U1-Out and U3-Out signals remain LOW, deactivating U11, U12, U13, U16, U17, and U18, allowing the signals from blocks U2 and U4 to respectively pass through OR gates U9 and U14 and U10 and U19 unchanged, and consequently allowing the gate drive circuit 150C to behave in the same manner as the circuit 150B (FIG. 4B) described above.

[0049] Operation of the gate drive circuit 150C with the Clamp Enable signal HIGH (activated) will be described in connection with the waveforms shown in FIG. 8, in which waveform 8A shows the output of U2, waveform 8B shows the output of U9, waveform 8C shows the output of U4, waveform 8D shows the output of U10, waveform 8E shows the output of U1, waveform 8F shows the output of U3, waveform 8G shows the output of U11, waveform 8H shows the output of U16, waveform 8I shows the output of U14, waveform 8J shows the output of U19, and waveforms 8K and 8L show the voltage at nodes 130 and 131.

[0050] The operating cycle in FIG. 8 is illustrated ending on a normal (not clamped) cycle and beginning at time tx1 operating in the same manner as described in connection with FIGS. 5 and 6 from time tx1 until time tx4. The following description assumes that the Clamp Enable signal (FIG. 4C) is HIGH (enabled) before time tx3, allowing the output of AND gate U21 to follow the output of pulse block U1, i.e. will go HIGH when U1 is triggered at time tx3. The output of pulse block U1 resets after the time, tp1, at time tx4 (tx4=tx3+tp1) turning gate drive switch Q1 OFF, allowing the current flowing in the primary winding 126 of the gate drive transformer 125 to discharge node 130, causing the voltage GA to decrease toward ground potential. The resetting output of pulse block U1 causes AND gate U21 to return to LOW, triggering pulse block U11 and delay block U12 at time tx4 and starting the clamp timing generator circuit in gate driver 150C.

[0051] Pulse block U11 outputs a HIGH signal when triggered at time tx4 keeping the output of OR gate U10 HIGH, which in turn keeps the output of OR gate U19 HIGH, which consequently keeps switch Q4 ON past the end of the U4 pulse, which is assumed to occur after time tx4 and before time tx5a. After the delay, td12, of delay block U12, i.e. at time tx5a (tx5a=tx4+td12), delay block U12 outputs a signal triggering pulse block U13 causing its output to go HIGH, driving the output of OR gate U14 HIGH to turn switch Q2 ON for the duration, tp13, of the U13 pulse. Under ideal conditions, the current flowing in the primary winding 126 of the gate drive transformer 125B will discharge node 130 completely to ground potential (GA=0) by the end of the delay td12 allowing for ZVS turn ON of gate drive switch Q2 at time tx5a. Delay td12 thus provides a ZVS transition of Q2 during the clamp cycle initiated by U1. With both gate drive switches Q2 and Q4 ON during the U11 pulse (from tx4 to tx5b), the primary winding 126 of the gate drive transformer will be clamped, storing energy in the gate drive transformer.

[0052] The duration, tp13, of pulse block U13 may preferably be set to a value greater than the sum of the duration, tp11, of pulse block U11 and delay, td6, of delay block U6 less the delay td12 of delay block U12 to ensure that the output of U13 remains HIGH past time tx6 to keep gate drive switch Q2 ON from time tx4 through time tx6. The duration, tp13, of pulse block U13 should also preferably be set to a value less than the sum of duration, tp11, of pulse block U11, delay, td6, of delay block U6, and duration, tp2, of pulse block U2 to avoid conflicts with the succeeding half cycle. The output of pulse block U13 resets to LOW after the time, tp13, at time tx6b (tx6b=tx5a+tp13), which being after time tx6, keeps the output of OR gate U14 HIGH, and thus gate drive switch Q2 ON until after U2 triggers taking control of switch Q2 until time tx9.

[0053] After the duration, tp11, of pulse block U11, i.e. at time tx5b (tx5b=tx4+tp11), the output of pulse block U11 resets to LOW. Assuming that the output of pulse block U4 has returned to LOW (pulse U4 has ended) before time tx5b (tx5 occurs before tx5b), the LOW signal at the output of U11 causes the output of OR gate U10 to return to LOW, triggering delay blocks U6 and U7 and turning OFF gate drive switch Q4, ending the clamp of the gate drive transformer and allowing the current flowing in the primary winding of the gate drive transformer to begin charging node 131 toward Vdrv. After the delay, td6, of delay block U6, i.e. at time tx6 (tx6=tx5b+td6), delay block U6 triggers pulse block U2 causing its output to be HIGH, causing the output of OR gate U9 to be HIGH, keeping the output of U14 HIGH, and the gate drive switch Q2 ON for the duration of the pulse tp6. After the delay, td7, of delay block U7 at time tx7 (tx7=tx5b+td7), delay block U7 outputs a signal triggering pulse block U3 which outputs a HIGH signal turning gate-drive switch Q3 ON. Under ideal conditions, node 131 will be charged to the potential of Vdrv (GB=Vdrv), allowing gate-drive switch Q3 to be turned ON with zero voltage across it for full ZVS operation at time tx7.

[0054] The following description assumes that the Clamp Enable signal (FIG. 4C) is HIGH (enabled) before time tx7, allowing the output of AND gate U22 to follow the output of pulse block U3, i.e. will go HIGH when U3 is triggered at time tx7. The output of pulse block U3 resets after the time, tp3, at time tx8 (tx8=tx7+tp3) turning gate drive switch Q3 OFF, allowing the current flowing in the primary winding 126 of the gate drive transformer 125 to discharge node 131, causing the voltage GB to decrease toward ground potential. The resetting output of pulse block U3, causes AND gate U22 to return to LOW, triggering pulse block U16 and delay block U17 at time tx8 and starting the clamp timing generator circuit in gate driver 150C for another gate clamp cycle.

[0055] Pulse block U16 outputs a HIGH signal when triggered at time tx8 which keeps the output of OR gate U9 HIGH, which in turn keeps the output of OR gate U14 HIGH, which consequently keeps switch Q2 ON past the end of the U2 pulse at time tx9, which is assumed to occur after time tx8 and before time tx9a. After the delay, td17, of delay block U17, i.e. at time tx9a (tx9a=tx8+td17), delay block U17 outputs a signal triggering pulse block U18 causing the output to go HIGH, driving the output of OR gate U19 HIGH to turn switch Q4 ON for the duration, tp18, of the U18 pulse. Under ideal conditions, the current flowing in the primary winding 126 of the gate drive transformer 125B will discharge node 131 completely to ground potential (GB=0) by the end of the delay td17 allowing for ZVS turn ON of gate drive switch Q4 at time tx9a. Delay td17 thus provides a ZVS transition of Q4 during the clamp cycle initiated by U3. With both gate drive switches Q2 and Q4 ON during the U16 pulse (from tx8 to tx9b), the primary winding 126 of the gate drive transformer will be clamped, storing energy in the gate drive transformer.

[0056] The duration, tp18, of pulse block U18 may be preferably greater than the sum of the duration, tp16, of pulse block U16 and delay, td8, of delay block U8 less delay td17 of delay block U17 to ensure that the output of U18 remains HIGH past time tx2 of the next operating cycle to keep gate drive switch Q4 ON from time tx8 through time tx2. The duration, tp18, of pulse block U18 should however be less than the sum of duration, tp16, of pulse block U16, delay, td8, of delay block U8, and duration, tp4, of pulse block U4 to avoid conflicts with the subsequent half cycle. The output of pulse block U18 resets to LOW after the time, tp18, at time tx2b (tx2b=tx9a+tp18), which keeps the output of OR gate U19 HIGH, and thus gate drive switch Q4 ON at least until after tx2b.

[0057] After the duration, tp16, of pulse block U16, i.e. at time tx9b (tx9b=tx8+tp16), the output of pulse block U16 resets to LOW. Assuming that the output of pulse block U2 has returned to LOW (pulse U2 has ended at time tx9) before time tx9b, the LOW signal at the output of U16 causes the output of OR gate U9 to return to LOW, triggering delay blocks U8 and U5 and turning OFF gate drive switch Q2, ending the clamp of the gate drive transformer and allowing the current flowing in the primary winding of the gate drive transformer to begin charging node 130 toward Vdrv. After the delay, td8, of delay block U8, i.e. at time tx2 (tx2=tx9b+td8), delay block U8 triggers pulse block U4 causing its output to be HIGH, causing the output of OR gate U10 to be HIGH, keeping the output of U19 HIGH and the gate drive switch Q4 ON. After the delay, td5, of delay block U5 at time tx3 (tx3=tx9b+td5), delay block U5 outputs a signal triggering pulse block U1 which outputs a HIGH signal turning gate-drive switch Q1 ON. Under ideal conditions, node 130 will be charged to the potential of Vdrv (GA=Vdrv), allowing gate-drive switch Q1 to be turned ON with zero voltage across it for full ZVS operation at time tx3. The operating cycle of the gate driver continues in the manner described above until the Clamp Enable signal is set to LOW (disabled) and the driver is allowed to return to normal (unclamped) operation as described above in connection with FIGS. 5 and 6.

[0058] The duration of the clamp of the gate drive transformer may be set by duration tp11 less delay td12 and duration tp14 less delay t17. The delays td12 and td17 of delay blocks U12 and U17 establish time for the voltage at respective nodes 130 and 131 to transition toward ground potential before turning ON the respective gate drive switches Q2 and Q4 for ZVS operation. Note that FIG. 8 is intended to show generalized approximations of actual behavior and as such is not intended to reflect, nor should the approximations be interpreted to represent, unnecessary detail. For example, the duration of the ZVS and clamp intervals may be exaggerated in FIG. 8 for the purpose of illustrating the operation of the driver.

[0059] The ASAC controller 120 may monitor the output current of the power train 140B and adjust the PTI and ERI durations and the converter operating frequency using the ASAC timing architecture described above and preferably using the gate-drive circuit shown in FIGS. 4A and 4B to maximize efficiency of the converter under various operating conditions. Referring to FIG. 7, the ASAC power train may be controlled as a function of load current by current monitoring circuit 160 having a first input connected to the input voltage (node 141) and a second input connected to sense the output voltage (node 142) of the non-isolated power train 140B (FIG. 1B). The example shown assumes a fixed ratio converter, such as an ASAC, having an essentially constant voltage gain K=Vout/Vin at a load current, where Vin is the input source voltage and Vout is the rectified output voltage across the load and an essentially constant output resistance, Rout, above a load current (e.g., IL2 in FIG. 3A). A voltage divider network including R1 163 and R2 162 provide scaling for the input voltage (assuming Vin>Vout) that matches the conversion ration K=Vout/Vin. Difference amplifier 161 amplifies the difference between the scaled input voltage (K*Vin) and the output voltage, Vout, and provides an output to the switch controller 120 which may then adjust operation of the ASAC as described above. In this way, the current monitor circuit 160 produces an output signal that represents the power-train output current without incurring losses in a sense resistance. The controller may additionally monitor the temperature of the converter and adjust for any temperature dependencies in the output resistance of the converter to improve the accuracy of the current monitor 160.

[0060] A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, although a half-bridge primary configuration is shown in FIGS. 1A and 1B, any of the alternate SAC configurations may be used to implement the ASAC topology. In non-isolated applications, the power train 140B of FIG. 1B may preferably use one of the optimized series-connected topologies described in Vinciarelli, et al., Power Distribution Architecture With Series-Connected Bus Converter, U.S. patent application Ser. No. 13/933,252 filed Jul. 29, 2013. Optionally, the clamped capacitor circuitry and control techniques described in the CSAC patent may be implemented in an ASAC for operation at higher loads to incorporate optional clamp intervals to extend the ON time of the switches beyond T_PTI-Full, shown in FIG. 2A and FIG. 5, i.e. longer than one half of the characteristic resonant period, for operation with increased efficiency at even higher loads. For example transfer function as shown in FIG. 3B for load currents greater than a lower threshold, I_L3, and less than an upper threshold, I_L4, I_L4>I_LOAD>I_L3, the controller may add clamp intervals to extend the PTI duration from the half-resonant period, T_PTI-Full up to a maximum duration, T_PTI-max. Although the threshold I_L3 is shown greater than I_L2 in FIG. 3, it may be set equal to I_L2. Furthermore the slope of the lines, I_LOAD>I_L3 and I_LOAD<I_L2, may be nearly the same or different. As a further example, the combination of pulse blocks, delay blocks, and logic gates shown in FIGS. 4A, 4B, and 4C may be replaced by a different combination of pulse blocks and delay blocks, or by equivalent functions implemented using analog or digital control techniques.

[0061] Accordingly, other embodiments are within the scope of the following claims.