The invention relates to electrical circuit arrangements. More particularly, it relates to circuit arrangements responsive to an input signal having a frequency anywhere within a predetermined range of frequencies for producing an output frequency having a predetermined and substantially constant means frequency; such a circuit arrangement may, for example, be used in a system for measuring the degree of modulation of a modulated signal (whether modulated by amplitude modulation or by frequency modulation).
According to the invention, there is provided an electrical circuit arrangement responsive to an input signal whose frequency lies within a predetermined range and for converting the input signal to a predetermined mean frequency, comprising mixing means for mixing the input signal with a variable frequency signal so as to produce an intermediate signal whose frequency is algebraically dependent on the two mixed frequencies, discriminator means responsive to the frequency of the intermediate signal to produce a control signal whose magnitude is dependent on the frequency of the intermediate signal, integrator means responsive to the control signal for comparing it with the magnitude of a reference signal so as to produce an error signal dependent on the difference therebetween and integrating the error signal, and frequency control means responsive to the integrated error signal for controlling the variable frequency signal in such a direction as to bring the mean frequency of the said intermediate signal to a value represented by the reference magnitude.
According to the invention, there is further provided a modulation measurement circuit arrangement for measuring the degree of amplitude or frequency modulation of a modulated input signal, comprising means responsive to an input signal carrying the modulation to be measured to produce therefrom an intermediate signal having a controlled and predetermined mean frequency and level but in which the said amplitude or frequency modulation is preserved, and means operative to measure the envelope amplitude or frequency variations of the intermediate signal due to the modulation to be measured.
According to the invention, there is also provided a modulation measurement circuit arrangement responsive to an input signal for measuring the degree of amplitude and/or frequency modulation thereof, comprising a sampling mixer connected to receive the input signal and operative at a frequency determined by controllable-frequency oscillating means to repeatedly sample and temporarily store the amplitude of the input signal whereby to produce an intermediate signal having a mean frequency dependent on the difference between the frequency of the input signal and some multiple of the frequency of the oscillating means, means for comparing the means frequency of the said intermediate signal with a reference representing a predetermined frequency value whereby to produce a first error signal, means responsive to the error signal to adjust the frequency of the oscillating means in such a direction as to tend to hold the mean value of the frequency of the intermediate signal at the predetermined frequency value while preserving therein variations in amplitude and/or frequency due to amplitude and/or frequency modulation, means responsive to the controlled intermediate signal from the mixer to detect changes in its mean level from a predetermined reference level whereby to produce a second error signal, level changing means responsive to the second error signal to adjust the mean level of the intermediate signal from the mixer in a direction tending to reduce the second error signal to zero whereby to produce an output signal whose mean frequency and level are substantially constant at predetermined values but in which are preserved the amplitude and/or frequency variations due to amplitude and/or frequency modulation in the input signal, and selectively controllable measuring means for detecting the amplitude or frequency modulation in the output signal and measuring the levels thereof.
Electrical circuit arrangements embodying the invention and for measuring the degree of amplitude or frequency modulation of a modulated input signal will now be described, by way of example only, with reference to the accompanying drawings in which:
FIG. 1 is a schematic circuit diagram of one form of the arrangement;
FIG. 2 is a schematic circuit diagram of a type of mixer which may be used in the circuit arrangement of FIG. 1;
FIG. 3 shows waveforms occurring in the mixer of FIG. 2;
FIGS. 4A & 4B are schematic circuit diagrams of another of the circuit arrangements; and
FIG. 5 shows waveforms occurring in the circuit arrangement of FIGS. 4A & 4B.
Basically, the circuit arrangements to be described accept a modulated input signal whose modulation depth (if amplitude modulated) or frequency deviation (if frequency modulated) is to be determined, uses a "sample and hold" mixing technique to produce a predetermined low frequency i.f. signal carrying the modulation information, controls the average level of the i.f. signal, and then measures the degree of modulation of the so-controlled signal.
The circuit arrangement of FIG. 1 has two alternative inputs, a high level input 5 and a low level input 6. The latter is connected directly to one input of a mixer 8, while the input 5 is connected to the mixer 8 through an attenuator 10 giving a fixed degree (20 dB) of attenuation.
In the mixer 8, the input signal is mixed with an output derived from a variable-frequency oscillator 12, and in a manner to be described, the frequency of the oscillator 12 is controlled so that the mixer output, on a line 14, has a predetermined, low, intermediate frequency (i.f.).
The output of the oscillator 12 is fed to a second input of the mixer 8 through a buffer amplifier 16, a frequency divider 18 (dividing the frequency by 2), then converted into narrow pulses in a pulse generator 20, and finally applied to the mixer 8.
The mixer 8 operates according to a sample and hold technique. In accordance with this technique, the input waveform F.sub.1 (FIG. 3) is repeatedly sampled at the pulse frequency (F.sub.2). FIG. 2 shows, somewhat simplified, one form which the mixer 8 can take. Each sampled amplitude of the input frequency F.sub.1 is temporarily stored on a capacitor 24, and the stored level therefore varies according to the difference in frequency between F.sub.1 and F.sub.2. The result is the production of a low frequency i.f. output signal F.sub.0 (where F.sub.0 =F.sub.1 -nF.sub.2, n being an integer) whose idealised shape is shown in FIG. 3 and which is applied via an amplifier 26 (FIG. 1) to feed an output line 14. The signal F.sub.0 is then passed via an output line 27 to level control circuitry to be described later.
The system includes circuitry 28 for tuning the oscillator 12 so as to maintain the i.f. signal at a constant frequency (as far as average variations are concerned--variations due to frequency modulation are not corrected for and thus appear on the i.f. output as will be explained). The circuitry 28 receives the i.f. signal F.sub.0 via the line 14 and includes a low pass filter 30, an amplifier 32, a limiter circuit 34 which removes amplitude information from the i.f. signal, and a discriminator circuit 36 which produces an output voltage on a line 38 proportional to the frequency of the i.f. signal.
The voltage on the line 38 is fed into one input of an integrator circuit 40 which also receives a reference voltage on a line 42 representing a predetermined value (in this case, 500 kHz) at which it is desired to control the average frequency of the i.f. signal. The output voltage of the integrator 40, on a line 44, tunes the oscillator 12 and is an integrated error signal which varies according to the difference between the voltages on the lines 38 and 42. If the i.f. frequency is drifting upwards, for example, then the voltage on line 38 will also increase. This will cause the output of the integrator 40 to fall slowly, thus decreasing the frequency of the local oscillator 12 and bringing the i.f. frequency back to the predetermined value. If the i.f. frequency drifts downwards, then the reverse action takes place.
It will be appreciated that the action of the integrator 40 is such that the circuitry 28 cannot follow rapid changes in frequency of the input due to frequency modulation, and the f.m. information is therefore not removed and exists on .[.the comparator 50 generates a second error signal which activates a sweep control means in the form of a hunt generator 52. By means.]. line 27. This means, however, that the system as so far described, cannot react quickly to an input when it is first applied. In order to deal with this point, the system includes a voltage comparator 50 which compares the voltage levels on the lines 38 and 42. When the voltage difference is such as to indicate that the frequency of the i.f. signal is substantially different from the predetermined value, the comparator 50 .[.activates.]. generates a second error signal which activates a sweep control means in the form of a hunt generator 52. By means of a line 54, the latter so controls the output of the integrator 40 that, independently of the values of its inputs on the lines 38 and 42 at that time, it sweeps the frequency of the oscillator 12 through its range. When the voltage comparator 50 determines that the changing i.f. frequency approaches the predetermined value, it switches off the hunt generator 52 which then allows the integrator 40 to take over control in the manner explained above.
The hunt generator 52 can consist of two transistors connected to produce, when switched on, positive and negative currents, for driving the integrator 40 in the upward and downward directions, respectively, together with a control circuit responsive to the sign of the output of the voltage comparator 50 for switching one or other of the two transistors on.
The circuitry also includes a hunt detector 56. The hunt detector monitors the output of the integrator 40 and incorporates level detecting circuitry for detecting when the integrator output reaches predetermined upper or lower limits. If the integrator output is detected as reaching the predetermined upper limits, the hunt detector activates the hunt generator 52 to reset the output of the integrator to a low level and then to sweep it upwardly therefrom. Again, if the oscillator output is detected as reaching the predetermined lower limit, the hunt detector activates the hunt generator to sweep the integrator output upwards until the correct lock point is reached. The integrator output may reach the upper or lower limit due for example to the oscillator output having overshot the control point or to a sudden change in the frequency of the input signal. In either case the hunt detector 52 helps the integrator to re-assume control.
As a result of the control action of the circuitry 28, therefore, the i.f. signal on the line 27 has a predetermined frequency but still carries the original modulation information (whether amplitude modulation or frequency modulation). This signal is applied to level changing means in the form of level control circuitry 62.
The circuitry 62 includes a low pass filter 64, a controllable gain amplifier 66, a band pass filter 68, and an i.f. amplifier 70. The amplified output from the amplifier 70 is applied on a line 72 to an amplitude modulation detector 74. In the a.m. detector 74, changes in the envelope of the amplified output signal on the line 72 are detected and output on a line 76. In addition, however, the average envelope amplitude is compared with a reference voltage on a line 78, and any changes produce variations in a control signal on a line 80 which adjusts the gain of the amplifier 66 in an offsetting direction. In this way, the average level of the signal on the line 72 is held constant though variations due to amplitude modulation (if any) are not removed and remain present on line 72.
The signal on the line 72 is also applied to a limiter circuit 82, which removes the amplitude information and the resultant signal is then applied to an f.m. detector 84 which produces an output voltage on a line 86 dependent on the value of the frequency modulation (if any). There thus respectively appear, at terminals 88 and 90, the amplitude and frequency modulation of the original input signal.
By means of a switch 92, either the amplitude or the frequency modulation can be applied to a measuring circuit 94. The measuring circuit includes an audio frequency amplifier 96 and a low pass filter 98. The output of the filter 98 can either be applied directly to an adjustable audio frequency filter 100 or, under control of a switch 102, applied thereto via an inverting amplifier 104. The filtered output is then applied through a range selecting adjusting attenuator circuit 106 (controlled by a range selecting switch 108) and thence through an audio frequency amplifier 110 and a peak detector 112 to a meter 114. The latter therefore indicates the extent of the amplitude or frequency modulation on the original input signal, according to the setting of the switch 92.
An output line 116 renders the signal on the line 72 externally available for extra processing if desired. Similarly, a line 118 renders the measured modulation externally available for recording purposes, for example.
The switch 102 enables the inverting amplifier 104 to be switched into the circuit, thus causing the meter 114 to display a measurement of the trough of amplitude modulation, instead of the peak, or to display the negative peak deviation of frequency modulation instead of the positive peak deviation. This facility enables the symmetry of the modulation to be assessed.
In order to indicate correct functioning of the system, the circuity includes a multivibrator 120 which drives a light emitting diode 122 under control of an AND gate 124. The diode 122 therefore flashes until the three inputs of the gate 124 are present and then is illuminated continuously.
The first of the gate inputs is taken from a low level detector circuit 126 which monitors the level of the i.f. signal. Only when the input signal level is sufficiently high to enable satisfactory measurement to be made does the low level detector 126 switch on its output to the gate 124.
The second input of the gate 124 is taken from the hunt generator 52 and is held off while the hunt generator 52 is sweeping the oscillator 12 through its frequency range. When the hunt generator 52 ceases operation so as to put the circuitry 28 under control of the integrator 40, then the output from the hunt generator 52 to the gate 124 is switched on.
The third input to the gate 124 is taken from the gain controlled amplifier 66 and is switched on only when the i.f. level is below a predetermined high level.
Therefore, when the input lies above the level set by the detector 126 and below the level set in the amplifier 66, and the frequency control circuit 28 is operating normally, the gate 124 switches off the multivibrator and thus illuminates the diode 122 continuously.
If desired, the circuitry can include means for driving the mixer 8 from an external controllable oscillator instead of the oscillator 12. Switching can be provided to render the local oscillator 12 and its control circuitry inoperative in such cases, and to enable the output of the discriminator 36 to be temporarily displayed on the meter 114 for assisting the tuning of the external oscillator.
In the circuit arrangement of FIGS. 4A & 4B, parts coresponding to parts in FIG. 1 are similarly referenced. As will be apparent, the circuit arrangement of FIG. 4A differs from that of FIG. 1 in that it uses a divide-by-10 divider 200 instead of the divide-by-two divider 18 of FIG. 1, and also incorporates a change over switch 201 (shown diagrammatically only in FIG. 4B) in the two lines fed to switch 102 of the measuring circuit 94. More importantly, however, the construction and operation of the tuning circuitry 28 differs from that of FIG. 1 as will now be explained in more detail.
As shown in FIG. 4A, the tuning circuitry 28 comprises a low pass filter 202, an amplifier 204, and a limiter 206, which correspond to the filter 30, the amplifier 32, and the limiter 34 of FIG. 1. The ouput of the limiter 206 therefore comprises a rectangular waveform from which amplitude information has been removed. The limiter output is fed into a divide-by-two circuit 208.
The purpose of the divider 208 is to convert into a waveform having a 1:1 mark/space ratio any input signal which does not have such a mark/space ratio. For example, waveform 210 in FIG. 5 shows an output from the limiter 208 having a mark/space ratio differing from 1:1. The effect of the divider 208 is to produce the waveform 212 which has the desired mark/space ratio. The divider 208 can be omitted if it is ensured that input signals to be handled always have a 1:1 mark/space ratio.
The output from the divider 208 is then fed into a time delay circuit 214 which delays the signal by a predetermined time and then passes it to one input of a gate 216. In addition, the output of the divider 208 is fed by means of a line 218 to one input of an electronic change-over switch 220 whose operational form is shown diagrammatically for explanation purposes. The second input of the change-over switch 220 is received from the divider 208 on a line 224 and is an inverted version of the signal on the line 218. In cases where the divider 208 is omitted, an inverter would be incorporated to provide the signal on the line 224. The output of the switch 220, which carries the signal on either the input line 218 or the input line 224, according to the setting of the switch, is fed to the second input of the gate 216.
The output of the gate 216 is then fed into an integrator circuit 226. The effective circuit of the integrator 226 consists of a resistor 228 and a capacitor 230, and the output from the integrator is taken across the capacitor on a line 232 and used as a control signal for the local oscillator 12. A discharge circuit consisting of a constant current generator 233 provides a constant current discharge path for the capacitor.
The operation of the tuning circuitry 28 as so far described will now be explained.
As explained in connection with FIG. 1, the purpose of the circuitry 28 is to tune the oscillator 12 so as to maintain the i.f. signal on the line 14 at a constant mean frequency.
Waveform 234 in FIG. 5 shows the output of the time delay circuit 214, the time delay being indicated by T. Assuming that the change-over switch 220 is set in the manner indicated, the gate 216 will therefore receive the waveforms 212 and 234. Gate 216 is operative to produce an output only when the output of the time delay 214 is negative and the output from the switch 220 is positive. Gate 216 will consequently produce a succession of pulses 236 which are thus applied to the integrator circuit 228 and charge up the capacitor 230.
The time delay T of the time delay circuit 214 is so set that, provided the intermediate frequency on the line 14 (and thus the frequency of the waveform 212) is at the desired value, each pulse of the pulse train 236 will occupy a fixed proportion (say, 90.degree.) of each cycle of the repetition frequency of pulse train 236. Therefore, the average charge input into the capacitor 230 will have a predetermined value. Taking into account the fixed discharge current from the capacitor 230, therefore, the result is that there will be produced on the line 232 a d.c. level which will hold the output frequency of the oscillator 12 constant at a frequency which produces the desired intermediate frequency on the line 14.
If any change in the value of the intermediate frequency takes place (as a result, for example, of a change in the input frequency of the circuit arrangement), then the frequency of the pulses 236 will increase or decrease correspondingly. The result will be that the mean charge fed into the capacitor 230 will increase or decrease and produce an integrated error signal in the form of a change in the d.c. level on the line 232 which will adjust the output frequency oscillator 12 in such a direction as to bring the intermediate frequency on the line 14 back to the predetermined value. The output frequency of the oscillator 12 will therefore change correspondingly and in a direction such as to bring the intermediate frequency on the line 14 back to the desired value.
As with the tuning circuitry 28 of FIG. 1, the action of the integrator 226 is such that the circuitry cannot follow rapid changes in the frequency of the input due to frequency modulation, and the f.m. information is therefore not removed and exists on the line 27.
In order to improve the response to the circuitry 28 to the condition when the intermediate frequency is substantially different from the desired value, the system includes a differential d.c. amplifier 240 which is connected to measure the voltage developed across the resistor 228 which is in turn dependent on the control action being exerted on the local oscillator.
The amplifier 240 has a high input impedance so as to avoid imposing substantially any current loading on the integrator circuit.
The output of the amplifier 240 is therefore a second error signal that controls a current generator 242 which feeds additional or augmenting charge into the capacitor 230 in dependence on the magnitude of the control action being exerted on the oscillator 12 by the integrator circuit. The result is that the control action exerted on the oscillator 12 is given a non-linear characteristic, with the additional current from the current generator 242 being large when the d.c. output from the gate 216 is demanding a large change in oscillator frequency and reducing as the demanded change decreases.
It will be appreciated that the amplifier 240 and the current generator 242 are particularly effective when an input signal is first applied to the circuit arrangement if its value is such that initially the intermediate frequency produced by the mixer 8 on the line 14 is substantially different from the desired value.
The tuning circuitry 28 also includes a level detector circuit 244 which is responsive to the output of an amplifier 246. When the level detector circuit 244 detects that the voltage on the line 232 (as received via amplifier 246) is such that the integrator output is reaching a predetermined upper or lower limit, it changes over the setting of the switch 220. The result is that waveform 212 in FIG. 5 becomes inverted. The control action therefore reverses. Thus, if the integrator output is approaching the upper or lower limit due for example to the oscillator output having overshot the control point or to a change in the frequency of the input signal, the reverse control action enables the integrator to re-assume control. Change over of the switch 220 produces a 180.degree. phase shift in the signal on the line 27. In order to compensate for this, the changeover switch 201 is also operated by the signal from the level detector 244 but only provided that a sensor 250 detects that the switch 92 is set to select frequency modulation. If the switch 92 is set to select amplitude modulation, the sensor 250 prevents switch 201 from changing over, since such change over is not required.
The remainder of the circuit of FIG. 4B and its operation are the same as described and illustrated with respect to FIGS. 1 to 3 and will not be further described.
The tuning circuitry 28 of FIG. 4A is particularly advantageous where the input applied to the circuit arrangement comprises more than one signal at different levels and different frequencies. The tuning circuitry 28 of FIG. 4A is better able to select the correct (that is, the largest) input signal in such a case than is the tuning circuitry 28 of FIG. 1.
Power supplies for the circuit arrangements are not shown but can be taken from a mains supply unit and/or from a battery supply which may be provided with its own charging arrangement.