Apparatus and Method for Reading and Writing Text Characters in a Graphics Display

1. Field of the Invention

This invention relates to display systems and, more particularly, to a system for reading and writing text characters in a color graphics raster scan, all points addressable video display.

2. Discussion of the Prior Art

A video display typically provides an interface between a data processing machine and a user. Generally, a video image may comprise either strings of characters or of graphics, each of which requires different storage and, heretofore, processing requirements. Because of these differing requirements, many prior art video display systems do not permit the combining of text and graphic data on the same screen. However, many applications of graphic displays would be greatly enhanced by the provision of character data, such as legends on charts or graphs.

U.S. Pat. No. 4,149,145 describes a video display permitting the placement of character data within the region of display of graphic information. This is done by combining both graphic and character data in a video register. Each of the graphic and character data are separately developed, with a character generator providing the character image components and a graphic generator providing the graphic image components. These two components are merged or superimposed to provide a composite video signal. However, in the system of U.S. Pat. No. 4,149,145, there is no provision for reading text characters from the composite signal, and unnecessary complexity is required by the use of separate text character and graphics generators.

The invention provides apparatus and method for writing text characters to a raster scan video display operated in the graphics mode, and for reading characters thus written.

The apparatus of the invention includes a graphic video display buffer operable in an all points addressable mode for refreshing the display with graphics data, and a processor for loading the graphic data into said graphics video display buffer. The improvement comprises programmable control means referenced by said processor for writing by selecting and loading into said graphics video display buffer a text character dot pattern from main storage, and for reading by comparing dot patterns read from said display buffer with dot patterns in said main storage.

According to the method of the invention, text characters are written to a raster scan, all points addressable video display by retrieving from storage the graphic dot image of a selected character, expanding the graphic dot image to a selected pixel and color format, and storing the expanded dot image in a graphics video display buffer. Text characters are read by retrieving from the display buffer expanded dot images, restoring the expanded dot image to its original form, and comparing the restored dot image with graphic dot images selected from storage.

FIG. 1 is a logic schematic illustrating the video display control apparatus of the invention.

FIG. 2 is a schematic illustration of the relationships between pixel display and storage locations.

FIG. 3 is a schematic illustration of a segmented display screen for use in describing the scrolling features of the invention.

FIGS. 4-6 are logic flow diagrams of the graphics write steps of the method of the invention.

FIGS. 7-9 are logic flow diagrams of the graphics read steps of the invention.

FIGS. 10-11 are logic flow diagrams of the graphics scroll up steps of the invention.

FIGS. 12-13 are logic flow diagrams of the graphics scroll down steps of the invention.

Referring now to FIG. 1, a description will be given of the apparatus of the invention for reading and writing text characters in a color graphics display.

The display of the invention is particularly suited for use in connection with a microcomputer including microprocessor 20, dynamic storage 25, read only storage 27, display 50, and keyboard 60. In this embodiment, microprocessor 20 may comprise an Intel 8088 CPU, which utilizes the same 16-bit internal architecture as the Intel 8086 CPU but has an external 8-bit data bus 22. For a description of the Intel 8086, and consequently of the 8086 instruction set used in the microprogram assembly language descriptions of the invention set forth hereafter, reference is made to Stephan P. Morse, The 8086 Primer, Hayden Book Company Inc., Rochelle Park, N.J., copyright 1980, Library of Congress classification QA76.8.1292M67 001.6'4'04 79-23932 ISBN 0-8104-5165-4, the teachings of which are herein incorporated by reference.

Processor 20 communicates with devices external to its integrated circuit chip via status and control line 21, data bus 22, and address bus 23. Such external devices include dynamic storage 25 (for example, Texas Instruments 4116 RAM) with refresh control 24 (for example, an Intel 8237 DMA driven by an Intel 8253 Timer); and, connected by drivers/receivers 26 (for example, a TTL standard part 74LS245), read only storage 27 (for example, a MOSTEK 36000), direct storage access (or DMA) chip 28 (for example, and Intel 8237 DMA), timer 29 (for example, an Intel 8253 Timer implemented as described in "Refresh Circuit for Dynamic Memory of Data Processor Employing a Direct Memory Access Controller," by James A. Brewer, et al, U.S. patent application Ser. No. 292,075, filed Aug. 12, 1981) and keyboard attachment 66 with keyboard 67.

Input/Output slots 30 provide for the attachment of a further plurality of external devices, one of which, the color graphic display attachment 31 is illustrated. Color graphics display adapter 31 attaches one or more of a wide variety of TV frequency monitor 50, 51 and TV sets 52, with an RF modulator 49 required for attaching a TV via antenna 53. Adapter 31 is capable of operating in black and white or color, and herein provides these video interfaces: a composite video port on line 48, which may be directly attached to display monitor 51 or to RF modulator 49, and a direct drive port comprising lines 39 and 46.

Herein, display buffer 34 (such as an Intel 2118 RAM) resides in the address space of controller 20 starting at address X`B8000`. It provides in 16K bytes of dynamic RAM storage a raster scan bit map. A dual-ported implementation allows CPU 20 and graphics control unit 37 to access buffer 34.

An APA mode, two resolution modes will be described: APA color 320.times.200 (320 pixels per row, 200 rows per screen) mode and APA black and white 640.times.200 mode. In 320.times.200 mode, each pixel may have one of four colors. The background color (color 00) may be any of the sixteen possible colors. The remaining three colors come from one of two palettes in palette 42 selected by microprocessor 20 under control of read only storage 27 program: one palette containing red (color 01), green (color 10), and yellow (color 11), and the other palette containing cyan (color 01), magenta (color 10), and white (color 11). The 640.times.200 mode is, in the embodiment described, available only in two colors, such as black and white, since the full 16KB of storage in display buffer 34 is used to define the pixels on or off state.

In A/N mode, characters are formed from ROS character generator 43, which herein may contain dot patterns for 254 characters. These are serialized by alpha serializer 44 into color encoder 41 for output to port lines 46 or via lines 48 to composite color generator 48 for output to composite video line 48.

Display adapter 31 includes a CRT control module 37, which provides the necessary interface to processor 20 to drive a raster scan CRT 50-52. Herein, CRT control module 37 comprises a Motorola MC6845 CRT controller (CRTC) which provides video timing on horizontal/vertical line 39 and refresh display buffer addressing on lines 38. The Motorola MC6845 CRTC is described in MC6845 MOS (N-channel, Silicon-Gate) CRT controller, Motorola Simiconductor's publication ADI-465, copyright Motorola, Inc., 1977.

As shown in FIG. 1, the primary function of CRTC 37 is to generate refresh addresses (MA0-MA13) on line 38, row selects (RAO-RA4) on line 54, video monitor timing (HSYNC, VSYNC) on line 39, and display enable (not shown). Other functions include an internal cursor register which generates a cursor output (not shown) when its content compares to the current refresh address 38. A light-pen strobe input signal (not shown) allows capture of refresh address in an internal light pen register.

All timing in CRTC 37 is derived from a clock input (not shown). Processor 20 communicates with CRTC 37 through buffered 8-bit data bus 32 by reading/writing into an 18-register file of CRTC 37.

The refresh memory 34 address is multiplexed between processor 20 and CRTC 37. Data appears on a secondary bus 32 which is buffered from the processor primary bus 22. A number of approaches are possible for solving contentions for display buffer 34:

(1) Processor 20 always gets priority.

(2) Processor 20 gets priority access any time, but can be synchronized by an interrupt to perform accesses only during horizontal and vertical retrace times.

(3) Synchronize process by memory wait cycles.

(4) Synchronize processor 20 to character rate.

The secondary data bus concept in no way precludes using the display buffer 34 for other purposes. It looks like any other RAM to processor 20. For example, using approach 4, a 64K RAM buffer 34 could perform refresh and program storage functions transparently.

CRTC 37 interfaces to processor 20 on bidirectional data bus 32 (DO-D7) using Intel 8088 CS, RS, E, and R/W control lines 21 for control signals.

The bidirectional data lines 32 (DO-D7) allow data transfers between the CRTC 37 internal register file and processor 20.

The enable (E) signal on lines 21 is a high impedance TTL/MOS compatible input which enables the data bus input/output buffers and clocks data to and from CRTC 37. This signal is usually derived from the processor 20 clock.

The chip select (CS) line 21 is a high impedance TTL/MOS compatible input which selects CRTC 37 when low to read or write the CRTC 37 internal register file. This signal should only be active when there is a valid stable address being decoded on bus 33 from processor 20.

The register select (RS) line 21 is a high impedance TTL/MOS compatible input which selects either the address register (RS=`0`) or one of the data registers (RS=`1`) of the internal register file of CRTC 37.

The read/write (R/W) line is a high impedance TTL/MOS compatible input which determines whether the internal register file in CRTC 37 gets written or read. A write is active low (`0`).

CRTC 37 provides horizontal sync (HS/vertical sync (VS) signals on lines 39, and display enable signals.

Vertical sync is a TTL compatible output providing an active high signal which drives monitor 50 directly or is fed to video processing logic 45 for composite generation. This signal determines the vertical position of the displayed text.

Horizontal sync is a TTL compatible output providing an active high signal which drives monitor 50 directly or is fed to video processing logic 45 for composite generation. This signal determines the horizontal position of the displayed text.

Display enable is a TTL compatible output providing an active high signal which indicates CRTC 37 is providing addressing in the active display area of buffer 34.

CRTC 37 provides memory address 38 (MA0-MA13) to scan display buffer 34. Also provided are raster addresses (RA0-RA4) for the character ROM.

Refresh memory 34 address (MA0-MA13) provides 14 outputs used to refresh the CRT screen 50-52 with pages of data located within a 16K block of refresh memory 34.

Raster addresses 54 (RA0-RA4) provides 5 outputs from the internal raster counter to address the character ROM 43 for the row of a character.

Palette/overscan 42 and mode select 47 are implemented as a general purpose programmable I/O register. Its function in attachment 31 is to provide mode selection and color selection in the medium resolution color graphics mode.

Time control 47 further generates the timing signals used by CRT controller 37 and by dynamic RAM 34. It also resolves the CPU 20 graphic controller 37 contentions for accessing display buffer 34.

An A/N mode, attachment 31 utilizes ROS (for example, a MOSTEK 36000 ROS) character generator 43, which consists of 8K bytes of storage which cannot be read/written under software control. The output of character generator is fed to alpha serializer 44 (such as a standard 74 LS 166 shift register), and thence to color encoder 41. As elements 43, 44 are included only for completeness, they are not utilized in the invention and will not be further described.

The output of display buffer 34 is alternatively fed for every other display row in a ping pong manner through data latches 35, 36 to graphics serializer 40, and thence to color encoder 41. Data latches 35, 36 may be implemented as standard TTL 74 LS 244 latches, graphics serializer 40 as a standard TTL 74 LS 166 shift register. Color encoder 41 may be implemented in logic such as is described in M. A. Dean, et al, "Composite Video Color Signal Generator From Digital Color Signals", assignees Ser. No. 292,074, 8-1981, of common assignee as the present invention. Composite color generator 45 provides logic for generating composite video 48, which is base band video color information.

The organization of display buffer 34 to support the 200.times.320 color graphics mode is illustrated in FIG. 2 for generating, by way of example, a capital A in the upper left-hand position 50a of monitor 50. Read only storage 27 stores for each character displayable in graphics mode an eight byte code, shown at 27a as sixteen hexidecimal digits 3078CCCCFCCCCCOO. In FIG. 2, these are organized in pairs, each pair describing one row of an 8.times.8 matrix on display 50a. In display 50a, an "X" in a pixel location denotes display of the foreground color (herein, code 11) and a "." denotes display of the background color (code 00).

When the character "A" is to be displayed, the sixteen digit hex code from read only storage 27 (or, equivalently, from dynamic storage 25) is, in effect converted to binary. Thus, the first 8 pixel row, 30 hex, becomes 00110000, in binary. This eight bit binary code is then expanded to specify color, with each "0" becoming "00" to represent the background color, and each "1" becoming 10, 01, or 11 to specify one of the three foreground colors from the selected palette. In FIG. 2, each "1" in the binary representation of the character code from storage 27 becomes "11" (which for palette two represents yellow; see below). Thus, the hex 30 representation of the first 8-pixel row of character "A", is expanded to 00 00 11 11 00 00 00 00 in display buffer 34a, shown at location `0` (in hexidecimal notation, denoted as x `0`). Graphics storage 34 is organized in two banks of 8000 bytes each, as illustrated in Table 1, where address x `0000` contains the pixel information (301-304) for the upper left corner of the display area, and address x `2000` contains the pixel information for the first four pixels (311-314) of thesecond row of the display (in this case, the first 8 bit byte of the two byte binary expansion 00 11 11 11 11 00 00 00 of hex 78).

For the 200.times.640 mode (black and white), addressing and mapping of display buffer 34 to display 50 is the same as for 200.times.320 color graphics, but the data format is different: each bit in buffer 34 is mapped to a pixel on screen 50 (with a binary 1 indicating, say, black; and binary 0, white).

Color encoder 41 output lines 46I (intensity), R (red), G (green), B (blue), provide the available colors set forth in Table 2:

Referring now to FIGS. 4-9, in connection with the Intel 8086 assembly language (ASM-86) listings embedded in microcode in read only storage 27, executed in microprocessor 20 to control the operation of video attachment 31, and set forth in Tables 3 through 12, a description will be given of the method of the invention for writing text characters to a video screen operating in APA, or graphics mode. The Intel 8086 architecture and ASM-86 language is explained in Morse, The 8088 Primer, supra.

In Table 3 is set forth the preamble and various initialization procedures to the Graphics Read/Write Character microprogram in ROS 27. While the control program, in this embodiment, is shown stored in a read only store 27, it is apparent that such could be stored in a dynamic storage, such as storage 25.

In step 400, a data location in RAM 25 is tested to determine if the system is graphics write mode. If not, and a character is to be written, a branch to normal A/N character mode 402 is taken and the method of the invention bypassed.

Table 4 sets forth the 8086 assembly language listing for the graphics write steps, Table 5 the high resolution (black and white, or 640.times.200) mode thereof, and Table 6 the medium resolution (color, or 320.times.200) mode.

In step 404, lines 53-57 of Table 4, addressability to the display buffer is established: the location in display buffer (REGEN) 34 to receive the write character is determined and loaded into register DI of processor 20. In step 406, lines 58-83, addressability to the stored dot image is established: the location in read only storage (ROM) 27 or dynamic storage (USER RAM) 25 of the dot image of the character to be displayed is determined. After execution of Table 4, line 92, processor 20 registors DS, SI are pointing at the location in ROM 27 or RAM 25 where the character dot image is stored, and DS, SI define addressability of the dot image. At step 408, line 93 the test is made for high resolution (640.times.200) or medium resolution (320.times.200) mode, (JC means jump on carry, and is an old Intel 8080 operation code which is the same as JB/JNAE in ASM-86, which works, amazingly enough, even though JC is not a documented operation code in ASM-86.) In high resolution mode, control passes to step 410, line 95 (Table 5). For medium resolution mode, it passes to step 438, line 124 (Table 6).

For high resolution mode (640.times.200, black and white), the procedure of steps 412-424 (426-430 included, if pertinent) is performed for each of the four bytes required to provide the dot image for a character in graphics mode. Step 410 (line 99) sets the loop counter register DH to four, and in steps 412 (step 101) a dot image byte from ROM 27 or RAM 25 pointed to by processor 20 registers DS, SI is loaded into the processor 20 string. The LODSB and STOSB instructions at lines 101, 120 and 104, 119, etc. perform the following actions:

At step 414 (line 102) a test is made to determine whether or not the application requesting the display of the character wants the character to replace the current display, or to be exclusive OR'd with the current display. In steps 416-422, (lines 104-115) the current display is replaced by storing this and the next dot image bytes in display buffer 34, with the next byte offset or displaced by X`2000` from the location of this byte in buffer 34. In steps 426-430 (lines 117-122), the alternative operation of exclusive ORing those two bytes into display buffer 34 is performed. If more than one identical character is to be written to display screen 50 in this operation, steps 432-434 of FIG. 5 (lines 112-114) condition the procedure for executing steps 410 through 434 for each such character.

Table 6 sets forth the 8086 assembly language listing in ROM 27 executed by processor 20 to control display attachment 31 to display a text character in the medium resolution (320.times.200) mode, and corresponds to steps 438 (FIG. 4) to 460 (FIG. 6).

In steps 438 (lines 128, Table 6, and Table 8) the input color (two bits, 01, 10 or 11) is expanded to fill a 16-bit word by repeating the two bit code. In step 440 (line 134), a byte of character code points are loaded into the AL register of processor 20 from storage 25, 27. In step 442, (line 135) each bit in the 1 byte AL register (character code points) is doubled up by calling EXPAND BYTE, Table 9; and the result is AND'd to the expanded input color (at line 136).

In step 444 (lines 142-143) the resulting word (2 bytes) of step 442 is stored in display buffer 34. This is shown, by way of example, at location X`O` in FIG. 2, the stored word comprising fields 301-308. (In FIG. 4, the XOR procedures of Table 6, lines 137-140 and 147-150 are not shown, but are analygous to the XOR procedure of steps 414-430 for the high resolution mode.)

In step 446 (line 144) the next dot image byte is retrieved from storage 25, 27, and at step 448 it is expanded (line 145) and AND'd with color (line 146). In step 450 (lines 152-153) the resulting word is stored in display buffer 34, offset from the word stored at step 444 by x `2000`.

At step 452 (line 154) the display buffer pointer is advanced to the next row of the character to be displayed, and processing returns (step 454, line 156) to complete the character or proceeds (step 456, 458, 460, lines 156-160) to repeat the completed character as many times as required.

Referring now to logic flow diagrams 7-9 in connection with the 8086 assembly language listings of Tables 10-12, an explanation will be given of the graphic read steps of the invention. In this process, a selected character dot image from display buffer 34 is compared against dot image code points retrieved from storage 25, 27, a match indicating that the character in buffer 34 has been identified, or read.

In step 462 it is first determined if video attachment 31 is being operated in the graphics mode. If not, in step 464 the read operation is performed in character mode, and the method of the invention is not involved.

In step 466 (line 171) the location in display buffer 34 to be read is determined by calling procedure POSITION, as set forth in Table 7. In step 468 (line 173) an 8-byte save area is established on a stack within the address space of processor 20.

In step 470 (lines 176-181) the read mode is determined. Control passes to step 482 (Table 11) for medium resolution (color, or 320.times.200) mode. For high resolution (black/white, or 640.times.200 mode, at step 472, line 187) the loop count is set to 4 (there being 4 two-byte words per character), and in steps 474-480 (lines 189-197) eight bytes are retrieved from display buffer 34 and put into the save area reserved on the stack in step 468. For medium resolution mode, at step 482 (line 203), the loop count is set equal to 4, and in steps 484-490 (lines 204-210) the character to be read is retrieved from display buffer 34. The procedure MED READ BYTE called at lines 205, 207 is set forth in Table 12 in connection with FIG. 9.

Referring to FIG. 8, at step 492 (Table 11, line 214) processing continues to compare the character, either high or medium resolution mode, read from display buffer 34 with character code points read from storage 25, 27. In step 492 (line 214) the pointer to the dot image table in ROM 27 is established. (The processing of lines 238-250 is executed if the character is not found in ROM 27 and the search must be extended into dynamic storage 25 where the user supplied second half of the graphic character points table is stored.)

In step 494 (lines 220-224) the character value is initialized to zero (it will be set equal to 1 when a match is found), and the loop count set equal to 256 (line 224 sets DX=128, and this is again, at line 249, reestablished for a total of 256 passes through the loop of steps 496-602, if required).

In step 496 (line 229), the character read from display buffer 34 into the save area is compared with the dot image read from storage 25, 27, and the match tested at step 498 (line 232). Loop control steps 600, 602 (lines 233-236) are executed until a match is found, or until all 256 dot images in storage 25, 27 have been compared with a match. In step 604 (line 255) the save area is released, and in step 606 (line 256) the procedure ends. If a character match has occurred in step 498, the character thus read is located in storage 25, 27 at the location pointed to by register AL. AL=0 if the character was not found (a not unexpected result if a character had been exclusively OR'd into the display buffer 24 at the location being read, such as at steps 426-450).

Referring now to FIG. 9 in connection with Table 12, the procedure MED READ BYTE, called at steps 484 and 486, will be described. This procedure compresses 16 bits previously expanded from eight to encode the color (see step 442) and stored in display buffer 34 (at step 444) back to the original dot image (obtained previously from storage 25, 27 at step 440). Step 608 (lines 330-331) gets two eight-bit bytes, which in step 610 (lines 332-343) is compressed two bits at a time to recover the original dot image. In step 612 (lines 344-346) the results are saved in the area pointed to by register BP.

Referring now to FIG. 3, in connection with FIGS. 10-13 and Table 13, a description will be given of the graphic scrolling facility provided for separate discrete areas 60, 63, 65 of display screen 506. This invention is described and claimed in U.S. patent application Ser. No. 6/292,081, filed Aug. 12, 1981 for "Apparatus and Method for Scrolling Text Characters and Graphic Data in Selected Portions of a Graphic Display", by David J. Bradley. In accordance with this invention, a user may define a plurality of windows on the screen in which graphic information blocks may be scrolled. The designation of a scroll section or window 60 requires address of opposite corners, such as the address of the upper left corner 61 and the lower right corner 62, and the number of lines to scroll. The difference in corner addresses sets the window. The color of the newly blanked line is established by a blanking attribute. Within these parameters, the graphic scrolling procedure of FIGS. 10-13 is performed. By this approach, both text (graphic) and display may be scrolled within separate windows 60, 63, and 65.

In Table 13, certain 8086 assembly language parameters are initialized. (Reference to graphics R/W dot does not pertain to the present invention.)

In Tables 14 and 15, the scroll up assembly language statements corresponding to FIGS. 10 and 11 are set forth. (The line numbers of Tables 13-19 overlap those of previous tables, but the step numbers of the figures do not.)

In step 614 (line 161) the pointer to the display buffer 34 location corresponding to upper left corner 61 of the display window 60 to be scrolled is placed in processor 20 register AX. In step 616 (lines 169-174) is determined the number of rows and columns in window 60. In step 618 (lines 178-179) the mode is determined, and if 320.times.200 mode is detected, in step 620 (lines 182-183) the number of columns in the window is adjusted to handle two bytes per character.

In step 622 (lines 185-200 of Table 15), the source pointer is established equal to upper left (UL) pointer plus the number of rows (from register AL) to scroll, the result placed in register S1.

In steps 624, 626 (line 203) a call is made to procedure ROW MOVE (Table 18) to move a row from source (pointed to by SI) to destination (pointed to by DI). Line 314 performs the move of step 624, line 322 of step 626, and lines 317-318 adjust the pointers (note line 17, Table 13--ODD FLD is equal to X`2000`).

In step 628 (lines 204-205), the source (SI) and destination (DI) pointers are advanced to the next row of the screen window. In step 630 (lines 206-207) the row count is decremented and, if the process is not complete, the procedure of steps 624-630 repeated.

In step 632 (FIG. 11; line 213) procedure ROW CLEAR (Table 19) is called to clear a row by filling it with the fill value for blanked lines specified in processor 20 register BH and transferred to the AL register at line 211. The REP STOSB instruction at lines 333, 338 stores the byte contained in AL into the byte whose offset is contained in DI, increments DI, and repeats to fill every byte of the row with the blanking attribute (which may be the screen background color, for example.)

In step 634 (line 214) destination pointer DI is advanced to the next row, and in step 636 (lines 215, 216) the number BL of rows to scroll is decremented, and the loop of steps 632-636 executed for each row to be scrolled.

The procedure for scroll down is set forth in FIGS. 12 and 13, in connection with the 8086 assembly language source code instructions of Tables 16-19. The procedure is analogous to that for scroll up, wherever step 638 corresponds to lines 239-242, step 640 to lines 250-256, step 642 to lines 257-261, step 644 to lines 263-265, step 646 to lines 267-283, steps 648 and 650 to line 286, step 652 to lines 287-288, step 654 to lines 289-290, step 656 to line 296, step 658 to line 297, step 660 to lines 298, 299 and step 662 to line 301.

The assembly language code listings of Tables 3 through 19 are Copyrighted by IBM Corporation, 1981, and are reproduced herein by consent of IBM. ##SPC1##

While the invention has been described with respect to preferred embodiments thereof, it is to be understood that the foregoing and other modifications and variations may be made without departing from the scope and spirit thereof.