Lumped Element Digital Phase Shifter Bit

This invention relates to the field of integrated circuit electronic networks providing selectable degrees of signal phase shift at microwave operating frequencies.

Phased array radar antennas and other microwave apparatus have need of digitally selectable phase delaying networks which are both low in fabrication cost and of the smallest possible physical size. For operating frequencies above ten gigahertz the use of distributed components in these phase shifting networks has become an accepted design practice in the microwave art. For frequencies below ten gigahertz, however, distributed component phase shifting components such as quarter wavelength microstrip delay lines become prohibitively long in physical size for implementation on an integrated circuit chip. In addition to the difficulty of containing these large phase shifting network components in an electronic apparatus--an apparatus which is almost always limited in physical size--the cost of fabricating these unduly large sized networks is found to be directly related to the physical size of the integrated circuit chip used to contain the network so that the large size in itself promotes undesirable apparatus cost.

The prior patent art includes several examples of previous phase shifting network practices. Included in these prior patents is the U.S. Pat. No. 4,471,329 of E. C. d'Oro which concerns a microstrip waveguide structure; the U.S. Pat. No. 4,471,330 of Naster et al which shows a conventional digital phase shifting bit that incorporates high frequency transmission lines; the U.S. Pat. No. 4,556,808 of Coats in which integrated lumped element pi-networks replace quarter wavelength transmission lines in a switching circuit arrangement; the U.S. Pat. No. 4,612,520 of Borie et al which describes a wideband 180 degree phase shifter bit that includes both transmission line segments and a pi-network; the U.S. Pat. No. 4,630,010 of Yarman which shows a low pass digital phase shifter for use at extra high frequencies; and the U.S. Pat. No. 4,652,883 of Andricos which concerns a signal phase shifter for use in a phased array radar system. None of these prior patents, however, achieves the advantages of the lumped element digital phase shifter bit of the present invention.

The present invention achieves both a physical size reduction and a fabrication cost reduction in the realization of certain microwave phase shifting elements through the use of lumped electrical elements as a replacement for the distributed elements normally used in such networks. The invention is also related to phase shifting networks in which a digital control signal can be used to alter the achieved degree of phase shift between discrete predetermined values.

It is an object of the invention therefore to provide a phase shifting network arrangement which is of desirable low cost and small physical size.

It is another object of the invention to provide a phase shifting network realization arrangement which is especially advantageous for use in the lower frequency portion of the microwave spectrum.

It is another object of the invention to provide a plurality of alternate phase shifting network circuit configurations which may be embodied in discrete or lumped element integrated circuit form.

It is another object of the invention to provide discrete component or lumped element integrated circuit phase shifting networks in which a binary control signal and switching transistor elements are selective of different network frequency response characteristics.

It is another object of the invention to provide lumped element phase shifting networks which may be readily configured to a plurality of different phase shift values.

Additional objects and features of the invention will be understood from the following description and the accompanying drawings.

These and other objects of the invention are achieved by integrated circuit digital phase shifter apparatus for use at microwave signal frequencies below ten gigahertz which includes the combination of; an integrated circuit die member having a semiconductor body portion and an upward facing planar surface; a plurality of discrete electrical inductance elements disposed in predetermined physical location array across said die member upward facing planar surface; a plurality of discrete electrical capacitance elements disposed in predetermined physical location array across said upward facing planar surface of said die member in predetermined phase shifting electrical network interconnection with said electrical inductance elements.

FIG. 1 shows a plurality of electrical networks which may be used in the present lumped element phase shift invention.

FIG. 2 shows an integrated circuit realization of one FIG. 1 network configuration 108 herein, as arranged for one specific degree of phase shift (11.25.degree.).

FIG. 3 shows an integrated circuit realization of one FIG. 1 network as arranged for a second degree of phase shift (22.5.degree.).

FIG. 4 shows an integrated circuit realization of one FIG. 1 network as arranged for a third degree of phase shift (45.degree.).

FIG. 5 shows a two path pi-configured phase shifting network including a pair of path selecting transistor switching arrays.

FIG. 6 shows a lumped element integrated circuit embodiment of the FIG. 5 network as arranged for 90 degrees of phase shift.

FIG. 7 shows a lumped element integrated circuit embodiment of the FIG. 5 network arranged for 180 degrees of phase shift.

FIG. 8 shows a simplified phase shift bit circuit which is useful at low values of phase shift.

FIG. 9 shows an alternate phase shift network arrangement which may be realized according to the present invention.

FIG. 10 shows a table of values for embodying one arrangement of the FIG. 1 network circuits as integrated circuit devices.

FIG. 11 shows a table of values for embodying the network of FIG. 5 as an integrated circuit.

FIG. 1 in the drawings shows a collection of seven tee and pi configured electrical networks which may be embodied as microwave phase shifting devices using the lumped element concept of the present invention. Each of the different network configurations 100, 102, 104, 106, 108, 110, and 112 in FIG. 1 employs a plurality of inductive, capacitance, and transistor elements which are provided with selected electrical values in order to achieve a predetermined degree of microwave signal phase shift between the input and output terminals of the network.

In the FIG. 1 drawing the transistor element in each of the different networks are indicated by the circle having an inscribed x as is indicated at 120 and 122 in the network configuration 108, for example. Preferably these transistor are of the field effect type and are fabricated directly onto the surface of the host integrated circuit device using one of the known transistor fabrication technologies. Typically, transistors of this type may have a turned on resistance which is in the range of 0.54 ohm-centimeters, a turned off resistance and capacitance combination of 0.36 ohm-centimeter and 1.72 picofarad per centimeter.

In view of the differing number of s-plane analysis poles and zeros and the otherwise differing electrical configurations of the networks shown in FIG. 1, variations in the change of signal phase delay with frequency can be expected with differing ones of the FIG. 1 configurations. One of the FIG. 1 configurations, the configuration 108, is believed typical and is selected for embodiment in the FIGS. 2-4 illustrated phase shift circuits.

The configuration 108 includes the two transistors 120 and 122 which are connected in shunt with the inductive elements 114 and 116 and this shunt combination as is connected in series with the capacitance elements 124 and 126; the junction between the capacitance elements is connected to the network common terminal by the shunt combination of the inductance 118 and the capacitance 128. A table of values for these and other FIG. 1 inductive and capacitance elements, using the C and L subscripted numeral identifications and the circuit identifications shown in FIG. 1, appears in the Table 1 of FIG. 10 in the drawings. Although the network configuration 108 and indeed all of the network configurations shown in FIG. 1 may be tailored for use at any number of different frequencies, the table of values shown in FIG. 10 presumes use in the "L" band or 1.3 gigahertz frequency range.

As is indicated by the numerical values in the left most column of the table 1 in FIG. 10, varying predetermined amounts of phase shift are to be realized from the use of different values in the network configuration 108. The numbers between 100 and 112 along the top most portion of FIG. 10, of course, identifies the differing network configurations shown in FIG. 1. The column of numbers in the seventh column from the left hand edge in FIG. 10 is particularly applicable to the network configuration 108 in FIG. 1. The shunt capacitor 128 in the network configuration 108 is shown in Table 1 to have a electrical value between 1.0 and 2.2 picofarads according to the desired value of phase shift being ninety or eleven and one quarter or some intermediate number of electrical degrees.

The size or magnitude of the component values recited in Table 1 suggest that the network configuration 108 is one of the more desirable of the configurations shown in FIG. 1 for realization in the form of an integrated circuit network. A comparison of the component values shown in Table 1, for example, shows that indicators in the range of 1.1 to 9.9 nanohenrys are required for phase shifts between 11.25 and 90 degrees and capacitances of 1.6 to 20.5 picofarads are required. For other of the FIG. 1 networks, however, the required inductor sizes may be as large as 33, 43 or even 61 nanohenrys. In a practical environmental it is found that inductances above 20 nanohenrys and capacitances less than 0.1 picofarad are difficult to fabricate as integrated circuit elements. The moderate range of the configuration 108 values recited in Table 1 therefore make this network a desirable choice for the present usage.

By way of including the switching transistor devices 120 and 122 in the network configuration 108 of FIG. 1 this network is provided with the capability of operating as either a series loaded line phase shifter. A loaded line phase shifter serves to periodically load a transmission line with alterable reactances to achieve phase shift. The periodicity of the reactance is nominally a quarter wavelength to properly cancel mismatches introduced by the reactive loads.

In the various configurations in FIG. 1, a single quarter wavelength section is used with reactive loading being located at each end. For this invention, the distributed quarter wavelength transmission line is in fact replaced by a lumped element equivalent circuit which consists of capacitors and inductors (in FIG. 1 these are represented by L.sub.1, L.sub.2, C.sub.1, and C.sub.2). The loading reactance is achieved by the parallel combination of the switching device or switching transistor and a parallel inductor and/or capacitor (in the configurations of FIG. 1 these are represented by L.sub.3 and C.sub.3). The switching device is used to alter the loading reactance and therefore alter the phase through the circuit. The amount of phase shift is proportional to the amount of reactance change.

The switching devices shown in FIG. 1 are preferably embodied as field effect transistors (FETs)--a three terminal device with terminals designated as gate, drain, and source. The FET when operated as a switch uses the gate to modulate the conductance between the source and drain. The conditions for operating the FET as a microwave switch require the source and drain to each have an applied DC potential of zero volts and the gate have an applied DC potential of either zero volts or a negative DC potential. The FET as a switch is considered "on" when the gate potential is zero whereby the microwave signal applied to the drain is passed to the source with minimal alteration. The FET as a switch is considered "off" when the applied gate potential is beyond the device pinchoff voltage (usually -5V) which causes significant microwave signal attenuation when passing from the drain to the source. Since the FET when operated as a switch is bilateral in nature, the microwave signal can be applied to either the drain or the source terminals.

FIGS. 2, 3, and 4 in the drawings show integrated circuit chip embodiments of the network configuration 108 in FIG. 1 with each of these embodiments resulting in a different amount of phase shift to an applied L band microwave signal. The FIG. 4 forty-five degree phase shift embodiment of the network 108 is typical of the FIGS. 2-4 circuit devices and is described in some detail herein along with appropriate references to the other two figures.

In view of the glossy photographic print nature of the FIG. 4 drawing in the present application, document references to individual portions of the FIG. 4 network are accomplished with an array of coordinated reference numbers, the numbers between 402 and 430 in FIG. 4, rather than with the usual number attached to a lead line arrangement. In the FIG. 4 integrated structure, for example, the spiral configured conductors centered at the intersection of the coordinates 402 and 404 represents the inductance L1, 118 in the FIG. 1 drawing. In a similar manner the node at the intersection of the coordinates 402 and 406 in FIG. 4 represents the lower or common conductor 130 in FIG. 1. The capacitor C1 at 128 in FIG. 1 is shown at the intersection of the coordinates 406 and 432 in FIG. 4 while the transistor 120 in FIG. 1 is shown at the intersection of coordinates 416 and 420 and the transistor 122 at the intersection of coordinates 416 and 418 in FIG. 4.

It should be noted that the position of the capacitor C2 at 126 in FIG. 1 and the shunt combination of the inductance 116 and transistor 122 are interchanged in the network embodiment of FIG. 4. As is known in the electrical network art, the interchanging or interposition of series connected electrical components has no effect on the electrical properties of the network. In a similar manner the position of the capacitor C2 at 124 and the inductor 114 and transistor 120 are interchanged in the FIG. 4 circuit arrangement.

Continuing then with the correlation of components in FIGS. 1 and 4, the inductor L3 at 114 in FIG. 1 is shown at the intersection of the coordinates 420 and 422 in FIG. 4 while the inductor L3 at 116 in FIG. 1 resides at the intersection of the coordinates 418 and 422 in FIG. 4. The capacitor C2 at 124 appears at the 404-416 coordinate intersection in FIG. 4 while the capacitor C2 at 126 appears at the coordinate intersection 408-416.

The portions of the FIG. 4 embodiment lying at the coordinate intersections 414-412 and 434-412 comprise electrical resistances which are not shown in the FIG. 1 schematic diagram but which are connected in electrical series with the transistor gate terminals in order to isolate the radio frequency and DC level control signals which exist in the transistors 120 and 122. DC resistance values in the range of 2000 ohms are found appropriate for this isolation. As is indicated in the upper left hand corner of the FIG. 4 embodiment, at the intersection of the coordinates 428 and 430, the phase shifting circuitry of FIG. 4 is intended to provide a phase shift of 45 degrees at L-band operating frequency.

The integrated circuit substrate which is indicated at 400 in FIG. 4 may be fabricated from one of the known semiconductor material, however, gallium arsenide is the preferred material. At 408-410 in FIG. 4 is located a gate control connection by which the digital signals controlling transistor operation is received onto the integrated circuit chip. The output terminals of FIG. 4 network are shown at the extreme left and right edges of the circuit chip in line with the coordinate 416.

Except for electrical values and resulting changes in discrete component physical sizes, the eleven and one quarter degree and twenty two and one half degree phase shifting networks embodied in FIG. 2 and FIG. 3 are similar to the above described FIG. 4 embodiment.

FIG. 5 in the drawings shows a high-pass/low-pass phase shifting network that is combined with a pair of transistorized single pole double throw switches. The transistorized switches are located at the input and output terminals of the FIG. 5 network. In the FIG. 5 circuit the high-pass network is located at 516 in the top arm of the circuit while the low-pass network is at 518 in the lower arm of the network and the input transistor switches is located at 504 and the output switch at 506. The network input terminals 500 is shown coupled to a pair of series pass field effect transistors 508 and 510 and the signal emerging from these series pass transistors is shunted by the two crowbar transistors 512 and 514. A similar transistor switching arrangement is shown at 506 adjacent the output terminal 502.

During operation of the FIG. 5 circuit it is contemplated that two of the series pass transistors such as the transistors 508 and 520 and two of the crowbar transistors such as the transistors 514 and 524 will be maintained in the conducting conditions by application of a suitable voltage at the node 526--in order to make use of the high-pass phase shifting network 516. Alternately, for use of the low-pass network 518 the transistors 510, 522, 512, and 528 will be placed in the conducting condition by a suitable voltage to the node 530.

Underlying the FIG. 5 circuit is the concept that a low-pass filter comprised of series inductors and shunt capacitors provide phase delay to signals passing through it. A high-pass filter comprised of series capacitors and shunt inductors similarly provides phase advance. By arranging switches to permit switching between the low-pass and high-pass configurations, a phase shifter can be made which is smaller than the other types while also achieving good bandwidth characteristics. A table of values for the FIG. 5 circuit operating at L-band frequencies is shown in FIG. 11, Table 2 of the drawings.

By way of acknowledgement, in addition to the lumped element concept of the present invention, certain aspects of FIG. 5 as well as FIGS. 6 and 7 also relate to an invention described in application Ser. No. 07/110,015 by Anthony Jacomb-Hood. Additional aspects of the FIGS. 5, 6, and 7 network are also described in the technical article "Affordable MMIC Designs for Phased Arrays" authored by Ronald J. Naster, Anthony Jacomb-Hood, and Mark R. Lang and published in the March 1977 issue of "Microwave Journal", a publication of Horizon House-Microwave, Inc.

FIG. 7 in the drawings shows a microphotograph of an integrated circuit embodiment of the FIG. 5 phase shifting network--an embodiment using the lumped element components of the present invention. With exception of the transposed locations for the inductor at 711, 712 and the grounding pad at 710, 711 in FIG. 7, the presence of the crowbar transistors at 716, 717 and 717, 718 and presence of the uppermost or low-pass portion of the circuit at 714, the components in the FIG. 7 integrated circuit chip are similarly disposed and identified as was discussed in connection with the FIG. 4 chip above.

The FIG. 7 circuit die represents a 180 degree phase shift embodiment of the high-pass/low-pass network arrangement indicated at 720, 721 in FIG. 7. A ninety degree phase shift arrangement of this high-pass/low-pass phase shift bit is also shown in FIG. 6 of the drawings. The FIG. 6 circuit chip is very similar to the FIG. 7 circuit and differs therefrom principally in size and physical arrangement of the inductance at 602, 603 and the capacitors at 604, 605 and 605, 606.

The high-pass/low-pass circuit arrangement of FIG. 7 (i.e., the 180.degree. bit circuit) is found to have significantly lower process sensitivity then is a high-pass/low-pass circuit arrangement in which switch capacitance is integrated into the filter network. These conventional circuits also require less chip area and have slightly higher insertion losses.

For low values of phase shift, that is, for phase shifts in the order of eleven degrees or less, the single resonated FET bit design shown in FIG. 8 of the drawings may be used. In the FIG. 8 phase shifter, the inherent capacitances of the FET transistor 802 are resonated with the shunting inductance 804 to provide a small value of phase shift. The resonated FET phase shifter of FIG. 8 is found to provide a phase difference that is proportional to frequency, a condition that is acceptable for lower values of phase shift.

FIG. 9 in the drawings shows an other phase shifter bit circuit arrangements which may be used with the present discrete element circuit embodiments and which relate in a plurality of ways to the herebefore described circuit arrangement. In the FIG. 9 drawing is shown an arrangement of the FIG. 5 circuit wherein transistor switches are included in the switched filter sections and in which the off state capacitance of the FET switches is less limiting then in the FIG. 5 circuit 15.

For the ninety degree, forty-five degree, and twenty- two and one-half degree phase shifter bits, the simplified high-pass/low-pass design of FIG. 9 with integrated switches is a desirable circuit approach. This circuit is the least sensitive to process variations and requires the least chip area (except for the twenty-two and one-half degree bit). The twenty-two and one-half degree bit is significantly larger than the series loaded-line design, but its achievable higher processing yield more than outweighs the decrease in unit area yield caused by the larger chip size. The variations in phase angle across the band is also extremely small for these arrangements, as is the difference in insertion loss between states. Furthermore, all the element values required by these circuits are easily realized in monolithic Microwave Integrated Circuit (MMIC) form. For the ninety degree and forty-five degree bits, the conventional high-pass/low-pass approach is slightly more lossy, slightly larger and slightly more process sensitive. The primary eleven and one-quarter degree bit is a simple resonated FET since this circuit has good process variation tolerance and low insertion loss and is small in size. A simplified low-pass/high-pass design is not possible for these bits because of the large inductance values associated with this type of design.

With the lumped element arrangement described herein for the phase shifter bit, significant decreases in physical size, decreases in the range of six to one, can be achieved. In addition to this reduced size and its benefits from the equipment packaging view point the reduced area in such circuits amounts to a significant cost decrease. The reduced area also increases the integrated circuit fabrication yield. These circuits also achieve greater tolerance to process variations and are associated with greater testability and ease of assembly.

While the apparatus and method herein described constitute a preferred embodiment of the invention, it is to be understood that the invention is not limited to this precise form of apparatus or method and that changes may be made therein without departing from the scope of the invention which is defined in the attended claims.