US 9,997,705 B2Grant
Porous SiOx materials for improvement in SiOx switching device performances
Issue Date:2018-06-12
•24 Claims
•16 Drawing Sheets
Abstract
A porous memory device, such as a memory or a switch, may provide a top and bottom electrodes with a memory material layer (e.g. SiOx) positioned between the electrodes. The memory material layer may provide a nanoporous structure. In some embodiments, the nanoporous structure may be formed electrochemically, such as from anodic etching. Electroformation of a filament through the memory material layer may occur internally through the layer rather than at an edge at extremely low electro-forming voltages. The porous memory device may also provide multi-bit storage, high on-off ratios, long high-temperature lifetime, excellent cycling endurance, fast switching, and lower power consumption.
Metadata
Assignee
- William Marsh Rice University
Inventors
- James M. Tour
- Gunuk Wang
- Yang Yang
- Yongsung Ji
Application Information
Application Number:US 15/033,726
Filing Date:2014-11-19
Priority Date:2013-11-19
Art Unit:2813
Classifications
IPC:
H01L45/00B82Y10/00B82Y40/00H01L29/16H01L29/41H01L27/24H01L29/06
Field of Search:
H01L 21/06H01L 27/2436H01L 29/1606H01L 29/413H01L 45/04H01L 45/1253H01L 45/145H01L 45/146H01L 45/1608H01L 45/1641H01L 29/0673B82Y 40/00
Patent Drawings (16 sheets)
Description
Related Applications
[0001] This application claims the benefit of U.S. Provisional Patent Application No. 61/906,011, filed on Nov. 19, 2013, which is incorporated herein by reference.
Statement Regarding Federally Sponsored Research
[0002] This invention was made with government support under Grant No. N00014-09-1-1066 awarded by the U.S. Department of Defense; Grant No. FA9550-12-1-0035 awarded by the U.S. Department of Defense; and Grant No. FA9550-09-1-0581 awarded by the U.S. Department of Defense. The government has certain rights in the invention.
Field of the Invention
[0003] This invention relates to porous memory materials, such as silicon oxide. More particularly, to utilizing porous silicon oxide materials in switching or memory devices.
Background of Invention
[0004] For more than a half century, conventional Si-based complementary metal-oxide-semiconductor (CMOS) transistors have been the mainstay of the electronic memory industry. Furthermore, Si-based flash memory's superior performance and its ease of fabrication compared to competing memory technologies has made it the dominant form of CMOS memory. However, the high standards of next-generation memory driven by rapidly growing demands have revealed the limits of current Si-based flash memory technology in terms of its fundamental scaling limitations, energy consumption, cost, and few microsecond switching speed. Although a wide variety of oxide-based materials and device structures for the replacement of the Si-based flash memories have been extensively investigated, none have adequately addressed future memory projections. Generally, the oxide-based resistive random access memories (RRAMs) can be categorized into unipolar, which can be programmed by the same voltage polarity, and bipolar memories, which can be programmed by reversing the voltage polarity. Many of the unipolar memories have demonstrated operation by nano-scale filamentary switching that allow them to follow an aggressive scaling trend; however, nano-scale metallic filaments can exhibit unstable switching behaviors, and high or unpredictable forming voltages (Vforming) due to the difficulty in controlling their stochastic formation. In contrast, bipolar memory has comparative advantages in the switching stability by an ionic movement or a redox process, with lower Vforming, and a broader range of materials availability. However, these come at the expense of lower switching ON-OFF ratios, limited thermal stability of the materials, or the limits of integration architectures to suppress sneak-currents in high-density crossbar arrays. Both unipolar and bipolar memory fabrications often involve high-temperature processes for materials depositions. Moreover, the devices commonly have a high switching current and need a compliance current (Ic) for preventing an electrical short, which requires an additional resistor on each cell and increases power consumption. To improve future nonvolatile memory, it is desirable to resolve the aforementioned challenges of each oxide-based memory system, such as by eliminating the need for I, or high temperature fabrication processes.
[0005] Nanoporous (NP) metal oxides have been widely used in electronics for energy production and storage. While NP materials have been used as templates for oxide memory applications, they have not yet been used as the active switching medium for resistive nonvolatile memory application.
[0006] The following disclosure discusses porous silicon oxide materials utilized as a unipolar switching medium and methods for fabricating porous silicon oxide materials. This new implementation of a porous oxide material in electronic devices meets the metrics desired for next-generation industrial performance. These new implementations also outperform present unipolar memory systems and can also bring advantages to bipolar memories. These can be used as memristors as well. Using this porous material structure, the stochastic formation of the switching filament may be controlled, which leads to significant improvements in device metrics, and the device can be fabricated at room temperature.
Summary of Invention
[0007] In one embodiment, a method for forming or fabricating a memory device may include the steps of depositing a bottom electrode on a substrate and depositing a material layer on the bottom electrode. The method may further include etching the material layer to form a porous structure and depositing a top electrode. In some embodiments, the porous structure is formed by anodic etching. In some embodiments, the etching may be performed in a HF/ethanol solution. In some embodiments, the method may further include applying a voltage sweep to the porous material layer to form a filament through the layer. In some embodiments, the filament may form internally through the porous material layer.
[0008] In one embodiment, a porous device, such as a memory or a switch, may provide a top and bottom electrodes with a material layer (e.g. SiOx) positioned between the electrodes. The material layer may provide a nanoporous structure. In some embodiments, the nanoporous structure may be formed electrochemically, such as from anodic etching. Electroformation of a filament through the material layer may occur internally through the layer rather than at an edge at extremely low electroforming voltages. The porous memory device may also provide multi-bit storage, high on-off ratios, long high-temperature lifetime, excellent cycling endurance, fast switching, and lower power consumption.
[0009] The foregoing has outlined rather broadly various features of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter.
Brief Description of the Drawings
[0010] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions to be taken in conjunction with the accompanying drawings describing specific embodiments of the disclosure, wherein:
[0011] FIGS. 1A-1G are (a) a nonlimiting schematic illustration of a NP SiOx memory device with a cross-sectional SEM image of a selected cell, (b) SEM image of the NP SiOx film tilted at 45°, (c) TEM image of the NP SiOx film, (d) the reflectance spectra of non-porous and nanoporous (NP) SiOx layers on a Pt-deposited silicon substrate with the numerical fitting curves based on an analytical formula using the measured thickness, (e) and (f) XPS Si2p and O1s spectra of the non-porous and NP SiOx films (x=1.63 to 1.76), respectively, and (g) the representative I-V characteristics of the NP SiOx with the initial I-V sweep (Inset);
[0012] FIGS. 2A-2H show an illustrative embodiment of a fabrication sequence for a NP SiOx memory;
[0013] FIGS. 3A-3B show a top and side view of an illustrative embodiment of a crossbar structure for encapsulated NP SiOx memory;
[0014] FIG. 4 is a table providing a nonlimiting summary of two terminal diode and selector materials (Table 1);
[0015] FIGS. 5A-5B show a top and side view of an illustrative embodiment of a one diode-one resistor (1D-1R) junction structure;
[0016] FIGS. 6A-6B shows a top and side view of an illustrative embodiment of a 1D-1R junction structure, which can be extended to a 3D stackable memory;
[0017] FIG. 7 is a side view of an illustrative embodiment of a stacking 1D-1R junction structure;
[0018] FIGS. 8A-8D are (a) a set of I-V characteristics of a single NP SiOx cell after exposure to different Vpulse(changed from 13 to 4 V with ΔV=1 V), (b) retention tests on a NP SiOx cell after different Vpulse processes during 104 s at 20° C. (top) and 100° C. (bottom), (c) endurance cycling test of an illustrative non-porous and NP SiOx cell for 103 cycles; and (d) endurance cycling test of the NP SiOx cell for 105 cycles (set voltage=5 V, reset voltage=15 V, and read voltage=1 V, ˜500 μs for set, reset, and read voltage pulses);
[0019] FIGS. 9A-9C are (a) a top SEM images show the planar Au/SiOx memory device before (left) and after (right) the breakdown of the Au nanowire with the enlarged via in the inset, (b) schematics of the NP SiOx memory structure before (top) and after (bottom) the breakdown of Au (or Pt) channel though a nanohole, and (c) a plot showing typical I-V switching characteristics of a nanogap device with an Au nanowire width of 60 nm (top figures) with the initial I-V sweep (Inset);
[0020] FIGS. 10A-D are plots of a (a) set current, (b) ON power, (c) Vforming, and (d) ON-OFF ratio corresponding to the number of endurance cycles for the NP SiOx and other reported unipolar memory devices, with the notations of [c], [e], or [T] indicating whether compliance current (Ic), the junction vertical edge, and/or a high temperature process are necessary for achieving desired switching behavior for the respective devices;
[0021] FIGS. 11A-11D show (a) a SEM image of the non-porous SiOx film at 45° tilt mode, (b) TEM image of the non-porous SiOx film, (c) SEM image of the nanoporous SiOx film at 45° tilt mode, and (d) TEM image of the nanoporous SiOx film that shows the voids in the amorphous SiOx;
[0022] FIG. 12 shows investigations on the surface chemical compositions of the SiOx film with different concentration of dilute HF/ethanol solution (0, 1, and 5 vol %);
[0023] FIGS. 13A-13C show (a) schematic diagrams for the non-porous and NP SiOx memory junctions, (b) electroforming process and switching I-V curves of a non-porous SiOx memory device with a vertical junction edge, and (c) electroforming process and switching I-V curve of the non-porous and NP SiOx memory devices without a vertical junction edge;
[0024] FIGS. 14A-14C show (a,b) a breakdown process from the intial I-V sweep in the different NP SiOx memory devices with Au top electrode, where the initial switching state in NP SiOx memory has one of two states ((a) OFF and (b) ON state) after the breakdown process, and (c) the electroforming voltages for non-porous and NP SiOx memory devices;
[0025] FIGS. 15A-15B show (a) a schematic diagram for a NP SiOx memory device using top Pt electrode, and (b) electroforming process and switching I-V curve of the NP SiOx memory device using a top Pt electrode;
[0026] FIG. 16 shows a switching speed test for a NP SiOx memory device (instruments testing limit is 50 ns);
[0027] FIGS. 17A-17B show (a) endurance cycling test of the NP SiOx cell for 4×103 cycles, and (b) endurance cycling test of the NP SiOx cell for 105 cycles after the degradation event;
[0028] FIGS. 18A-18B show (a) the endurance cycling test of the SiOx nanogap device for 2.5×103 cycles, and (b) the SEM image after the breakdown process;
[0029] FIG. 19 shows a table summary (Table 2) of switching parameters of NP SiOx (top two entries) unipolar memory and non-porous (remaining entries) memory, including endurance cycles, ON-OFF ratio, Vforming, Iset, ON power values, indications of whether compliance current, high temperature processes, and vertical junction edge for switching are needed, respectively (The symbol “x” means “not required” and “o” means required).
Detailed Description
[0030] Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.
[0031] Referring to the drawings in general, it will be understood that the illustrations are for the purpose of describing particular implementations of the disclosure and are not intended to be limiting thereto. While most of the terms used herein will be recognizable to those of ordinary skill in the art, it should be understood that when not explicitly defined, terms should be interpreted as adopting a meaning presently accepted by those of ordinary skill in the art.
[0032] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only, and are not restrictive of the invention, as claimed. In this application, the use of the singular includes the plural, the word “a” or “an” means “at least one”, and the use of “or” means “and/or”, unless specifically stated otherwise. Furthermore, the use of the term “including”, as well as other forms, such as “includes” and “included”, is not limiting. Also, terms such as “element” or “component” encompass both elements or components comprising one unit and elements or components that comprise more than one unit unless specifically stated otherwise.
[0033] Oxide-based two-terminal resistive random access memory (RRAM) is considered to be one of the most promising candidates for next-generation nonvolatile memory. Systems and methods forming porous memory material layers in devices, such as memories and switches, are discussed herein. For the purposes of illustration, the following discussion may refer specifically to SiOx memories or layers. However, it will be recognized by one of ordinary skill in the art that concepts applied to the SiOx memories or layers may also be applied other materials. Nonlimiting examples of suitable memory materials may include SiOx (where 0.2≤x≤2).
[0034] SiOx memory may provide several benefits over other unipolar memory, such as beneficial switching currents, on-off ratios, aggressive scaling down the nanoscale, low operating voltages, and operation in atmospheric environments by controlling oxygen content “x” under 0.75 and its bonding configurations. However, despite great switching properties in SiOx unipolar memory, the switching properties have two limitations: (a) few endurance cycles (˜1000 cycles); and (b) high electroforming voltage (>20 V). The above deficiencies can be obviated by using a porous SiOx. New RRAM memory structures employing a nanoporous (NP) silicon oxide (SiOx) material are discussed herein, which enables unipolar switching through an internal vertical-nanogap in the NP silicon oxide rather than an edge. Through the control of the stochastic filament formation at low voltage, the NP SiOx memory exhibited extremely low electroforming voltage (e.g. ˜<5 V) and outstanding performance metrics. These include multi-bit storage ability (e.g. up to 9-bits), high ON-OFF ratio (e.g. up to −107 A), long high-temperature lifetime (e.g. ≥104 s at 100° C.), excellent cycling endurance (e.g. ≥105), fast switching speeds (e.g. sub 50 ns), and low power consumption (e.g. ≤6×10−5 W/bit). The NP silicon oxide material also provides room temperature processability for versatile fabrication without any compliance current (Ic) being needed during electroforming or switching operations. Taken together, these metrics in NP SiOx RRAM provide a route toward easily accessed nonvolatile memory applications.
[0035] FIG. 1A is an illustrative embodiment of a schematic diagram of the NP memory cells along with a cross-sectional scanning electron microscope (SEM) image at the middle of the cell (inset). The NP memory material layer 10 is provided between electrode layers 20 and 30. The NP memory material layer 10 and electrode layers 20 and 30 may be deposited on top of a substrate 40. In some embodiments, the NP memory material layer 10 may be SiOx where 0.2>x>2. The electrode layer 20 and 30 may be made of any suitable electrode material. Nonlimiting examples may include Au, Pt, Cu, Al, ITO, graphene, TiN, highly doped Si, or any other suitable metal, alloy or semiconductor material. In some embodiments, the substrate 40 may be formed of one or more materials, such as, but not limited to, Si, SiOx, or the like. As a nonlimiting example, the NP memory cell shown in FIG. 1A may provide a SiOx NP memory material layer 10, Au or Pt top electrode 20, Pt bottom electrode 30, and Si/SiOx substrate 40.
[0036] In some embodiments, any currently known device arrangement may be modified into device arrangement that provides a porous memory material layer. In some embodiments, any currently known arrangement for silicon oxide-based memory cells may be modified to porous silicon oxide-based memory cells. In some embodiments, a porous unipolar SiOx memory cell adopts a layered structure with the SiOx (0.2≤x≤2) layer sandwiched between the top electrode (TE) and bottom electrode (BE). In some embodiments, after the memory unit is electroformed into a switchable state, a moderate voltage pulse (e.g, equal to or between 3 to 6 V) can set/write the unit into a low-resistance (on) state while a higher voltage pulse (e.g., ≥7 V) can reset/erase the unit to a high-resistance (off) state. These resistance states can serve as the binary code 0 and 1 in digital information. Once programmed, the resistance states (both on and off states) are nonvolatile. In some embodiments, the memory readout shares the same electrode as the programming electrode. In some embodiments, only the memory readout is read at a lower voltage (e.g. ≤3 V). In some embodiments, the memory state can be read nondestructively. Due to the similarity to pure SiOx memory operation, it shall be understood that the memory programming and readout NP SiOx memory discussed herein may operate in the same or similar manner as non-porous SiOx memory.
[0037] Nonlimiting examples of advantages of NP SiOx memory in comparison to non-porous or traditional SiOx memory may include the following:
[0038] (1) In some embodiments, the switching cycles of porous SiOx memory systems can be endured for equal to or greater than 2×103 cycles. In some embodiments, the switching cycles of NP SiOx may be endured for over 104 cycles. In some embodiments, the switching cycles of NP SiOx may be endured for over 100,000 cycles, which is 10 to 100 times more cycles than traditional non-porous SiOx memories (FIGS. 8C-8D ). In some embodiments, the switching cycle endurance may be achieved with 103 on-off ratio.
[0039] (2) Porous SiOx memory systems do not need an edge of the SiOx layer for switching, or in other words, they have a filament or switching path inside of SiOx layer. This advantage permits fabrication of a stacking memory integration structure with an isolation layer. Nonporous SiOx memory requires an edge between electrodes and SiOx layer, which limits the potential stacking memory application. The edge may be added through a series of etching (wet or dry) steps, whereas in the porous system, a simple crossbar address line can be applied to the porous platform without fabricating the edge. This is an enormous advantage for the porous memory systems, as the extra fabrication steps necessary to form this edge are no longer necessary to provide a working device.
[0040] (3) In regard to the electroforming voltage, the porous SiOx memory systems have low voltages required (FIGS. 13B-13C ) to generate a filament or switching path as compared to 15 to 20 V in case of nonporous SiOx. In some embodiments, the electroforming voltage is equal to or less than 10 V. In some embodiments, the electroforming voltage is equal to or less than 5 V. In some embodiments, the electroforming voltage is equal to or less than 2.1 V. In some embodiments, the electroforming voltage is equal to or less than 1.6 V. Hence, the problematic Joule-heating-damage to the surrounding oxide-based memory material itself is mitigated. If not mitigated, the Joule-heating-damage would limit the switching performance and the device yields required for future commercial memory applications.
[0041] Various methods may be utilized to make porous SiOx memory systems. In some embodiments, fabrication procedures for porous SiOx layers may involve one or more of the following steps: (1) A substrate may optionally be prepared for the memory system. As a nonlimiting example, the porous SiOx cells may fabricated on p-type (100) Si wafers (1.5 cm×1.5 cm) covered with thermally grown 300 nm-thick SiO2. (2) A bottom electrode is deposited on the substrate, such as layer of Au, Pt, Cu, Al, ITO, graphene, TiN, highly doped Si, or any other suitable metal, alloy or semiconductor material. As a nonlimiting example, a Pt bottom electrode may be formed on the substrate by sputtering or E-beam evaporation after a typical cleaning process with acetone, isopropyl alcohol, and deionized (DI) water by ultrasonication (bath) for 3 min. (3) Next, the SiOx, layer may be deposited on the bottom electrode. As a nonlimiting example, a SiOx (30-50 nm thick) may be deposited by using PECVD, E-beam evaporation, ALD, or any other suitable method for depositing SiOx. (4) The porous structure may be prepared by an etching process. In some embodiments, a porous structure in the deposited SiOx layer may be formed electrochemically by anodic etching. In some embodiments, a porous structure in the deposited SiOx layer may be formed by E-beam lithography, reactive ion etching (RIE) with nanoparticles, or any other suitable methods for forming a porous structure. As a nonlimiting example, the SiOx layer may be etched in a dilute HF/ethanol solution under a constant current. (5) In some embodiments, the etching solution may be dilute HF/ethanol with the concentration of HF relative to ethanol equal to or between 0.01-10% by volume. In a nonlimiting example, dilute HF/ethanol solutions with concentration of 1, 5, 10 vol % were prepared by diluting HF (48-51 vol %, J. T. Baker) in absolute ethanol (Pharmo). A two-electrode system was used in anodic treatments with SiOx on silicon as the anode and platinum foil as cathode. A constant current density of 6.4 mA/cm2 was applied for 30 s to fabricate the porous structure in the SiOx thin layer. (6) After electrochemical etching, the substrate and porous SiOx layer may be cleaned, rinsed, and dried. For example, after anodic etching, samples were rinsed with DI water and dried under a nitrogen flow. (7) Subsequently, the top electrode may be deposited on the porous SiOx layer. As a nonlimiting example, the top electrode may be deposited on the patterned area using photo-mask or shadow metal mask methods. (8) If necessary, non-active portions of the SiOx layer may be removed. In a nonlimiting example, reactive-ion etching (RIE) was performed to remove the non-active SiOx layer and exposed bottom Pt electrode. Notably, in some embodiments, the various steps of the fabrication process for the porous silicon oxide do not require any high temperature processing, and more particularly, each of the fabrication steps can be performed at room temperature. If desired, in some embodiments, the entire memory chip can be hermetically sealed to limit exposure to oxygen. This could involve the use of epoxy, silicon nitride, parylene, or the like.
[0042] The porous SiOx memory systems can have numerous variations, including the following:
[0043] 1. The thickness of the layers (e.g., SiOx and electrodes) in the structures and the deposition can be varied to obtain optimum performance.
[0044] 2. The concentrations of electrochemical etching solution can be varied to tailor the pore size and porosity of the SiOx layer as desired.
[0045] 3. The applied current density during electrochemical etching can be varied to tailor the pore size and porosity of the SiOx layer as desired. In some embodiments, the NP layer may have pore size equal to or between 0.1 to 100 nm. In some embodiments, the NP layer may have pore size equal to or between 0.1 to 10 nm. In some embodiments, the NP layer may have pore size equal to or between 2-6 nm. In some embodiments the NP layer may have a pore size equal to 1 nm.
[0046] 4. The electrochemical etching duration can be varied to tailor the pore size and porosity of the SiOx layer as desired.
[0047] 5. Chemical and physical treatments on surfaces can be varied to obtain optimum performances for making porous SiOx.
[0048] 6. The x value in SiOx can be varied wherein 0.2≤x≤2 to obtain the optimum performance from the memories.
[0049] 7. The feature size and form of the cells can be varied to obtain optimum performance from the memories. For example, in some embodiments, the line width can be made far smaller. The pores in some of the illustrative embodiments are ˜6 nm in diameter, but in other embodiments, the pores can be made smaller, such as 1 nm using varied anodization parameters, thereby accommodating narrower address lines.
[0050] 8. Multi-bit or multi-level storage capability could be obtained in a porous SiOx memory unit wherein there is more than just a 0 and 1 state stored by a single cell, such as up to 9-bits. In some embodiments, one cell of the porous SiOx memory may provide multi-bit storage of 4-bits or more. In some embodiments, one cell of the porous SiOx memory may provide multi-bit storage of 5-bits or more. In some embodiments, one cell of the porous SiOx memory may provide multi-bit storage of 6-bits or more.
[0051] 9. A multi-stacking structure (e.g., 3D from stacked 2D) can be utilized in a porous SiOx memory for ultra-dense memory arrays.
[0052] 10. Various dilute HF/ethanol solutions can be used to generate SiOx memory systems.
[0053] 11. Fabrication of advanced integration, such as 1D-1R, 1S-1R, 1T-1R, or the like, based on porous SiOx memories and in crossbar architectures are possible.
[0054] 12. Diverse electrical and optical tests can be performed by the SiOx memory systems.
[0055] 13. The porous SiOx memory systems of the present disclosure can be transparent in some embodiments.
[0056] 14. The porous SiOx memory systems of the present disclosure can be flexible in some embodiments.
[0057] 15. The porous SiOx memory systems of the present disclosure can be flexible and transparent in some embodiments.
[0058] The following provides an illustrative embodiment of a fabrication process for a nanoporous silicon oxide memory as shown in FIGS. 2A-2H . (1) Bottom electrode 220 formation on the substrate 210 may occur as shown in FIG. 2A . For example, a Pt/Ti bottom electrode 220 is deposited on SiOx/Si substrate 210. Ti is used as an adhesion layer 3-5 nm. In some embodiments, the electrode may be formed of Au, Pt, Cu, Al, ITO, graphene, TiN, highly doped Si, or any other suitable metal, alloy or semiconductor material. The thickness of the bottom electrode does not affect the switching performances of memory. Further, flexible substrates (e.g., PET and PEN) are available, but the flexible substrate could restrict the integration architectures that require higher temperature processes.
[0059] (2) A material layer 230 may be deposited as shown in FIG. 2B . For example SiOx 230 is deposited on the Pt/Ti electrode 220 that was deposited on the SiOx/Si substrate 210. A 40 nm SiOx layer 230 may be deposited by PECVD or 100 nm SiOx by e-beam evaporation. An atomic ratio “x” between silicon and oxygen can have range from equal to or between 0.2 to 2. Any deposition system such as an e-beam evaporator, sputtering, PECVD, and ALD are suitable. The deposition method used could change the atomic ratio between silicon and oxygen, which results in needed variations of the anodization condition for forming the porous SiOx. Further, the thickness of the SiOx can affect the conditions needed for the anodization process that determines the density of the pores and their sizes.
[0060] (3) Formation of nanoporous layer may occur as shown in FIGS. 2C-2D . FIG. 2C shows the experimental scheme for anodization process. FIG. 2D shows an enlarged view for the anodization process. In an illustrative embodiment, the anodization electrolyte 350 was prepared by mixing 1 vol % HF in ethanol (200 proof, 100%) placed in a container 340 (this was used on SiOx that had been prepared by PECVD at 300° C. for 1 min). A two-electrode system was used in anodic treatments with SiOx on silicon substrates 330 as the anode 310 and Pt foil as cathode 360. In some embodiments, the SiOx on silicon substrate 330 may be wrapped in Al foil 320 and placed in contact with a CU plate as the anode. A constant current density may be provided to the anode 310 and cathode 360 from a voltage or current source 370. For example, a constant current density of 6.4 mA cm−2 was applied for 30 s to fabricate the nanoporous SiOx. After anodic etching, samples were rinsed with DI water and dried under a nitrogen flow. The pore sizes range from equal to or between 2 to 6 nm. In case of SiOx deposited by e-beam evaporation, 0.2 vol % HF was used and an applied current for 10 s. In some embodiments, annealing may be performed for a predetermined amount of time before forming the porous layer. For example, annealing (350° C. for 1 h) before the anodization process can help to increase the yield of memory devices.
[0061] Any method for making nanopores in SiOx that have diameters of a few nm is suitable for the nanoporous memory discussed. For example, standard e-beam lithography and the proper oxidation process can form well-defined single nanopore structures inside the silicon oxide structure (Ref. Nanotechnology 2014, 25, (35), 355302.). Further, Si can change to porous SiOx by anodization treatment. Thus, in some embodiments, Si can be utilized in the deposition step instead of silicon oxide. The anodization treatment can control the density of porosity and the size of pores by modifying the potential and the current. FIG. 2E shows a resulting porous SiOx layer 230 with pores 240.
[0062] (4) The top electrode 250 on the nanoporous SiOx layer 230 and the two-terminal junction structure may be formed as shown in FIG. 2F . For example, using a circular photo-mask or a circular shadow metal mask method, a top electrode 250 (Au or Pt) was deposited on the nanoporous SiOx layer. An etching process may also be performed for removing uncovered nanoporous SiOx layer by RIE.
[0063] (5) The electroforming process or electro-breaking process for formation of the Si-switching channel 270 at the wall of the SiOx nanopore may be performed as shown in FIGS. 2G-2H . After the breaking process of metal by the electromigration process from the initial voltage sweep applied by a voltage or current source 260, the Si-switching channel 270 is formed. Other pore regions may be broken as well, but do not contribute the switching. It is theorized that only one pore having the smallest radius, thereby having the highest potential, provides the switching channel. In the case of the large pores, it is much easier to get larger gap distance between Pt electrodes by the electromigration process, which leads to the reduction of potential for the formation of the final Si switching channel. The gap distance by the electromigration process is dependent on the pore size, the applied voltage, and the temperature.
[0064] Encapsulated crossbar nanoporous silicon oxide memory: A crossbar structure for encapsulated nanoporous SiOx memory is shown in FIGS. 3A-3B . Substrate 410 may provide a bottom electrode 420, SiOx layer 430, and a top electrode 440. As shown in the side view in FIG. 3A , the memory may be formed in a crossbar arrangement. A passivation layer 450, such as SiO2, or epoxy layer to prevent the oxidation of Si channel by the oxygen in air may be utilized. Conversely, the entire active area may be encapsulated using a commercial epoxy (e.g. Su-8 from MicroChem Company). Using e-beam lithography, the word/bit metal lines could be aggressively scaled to a few tens of nanometer scale. The active Si-switching channel is sub-5 nm, thereby indicating that this aggressive scaling is possible. In some embodiments, individual memory cells may be scaled down to 50 nm or less. In some embodiments, individual memory cells may be scaled down to 20 nm or less. In some embodiments, individual memory cells may be scaled down to 10 nm or less.
[0065] Potential Integration Architectures: One Selector (or Diode)-One resistor (1D-1R) (e.g. Using the PN Diode or the Oxide-Based Selector)
[0066] (1) Selector candidates: Table 1 (See FIG. 4 ) provides a nonlimiting summary of two terminal diode and selector materials.
[0067] (2) 1D-1R based on the pn diode and the nanoporous silicon oxide memory: A 1D-1R junction structure may be available to “one layer” for the 1D-1R device as shown in FIGS. 5A-5B . The substrate 510 may provide a diode 520 and silicon oxide memory. Extrapolation to a 3D stackable memory may be difficult due to the doped Si layer. The diode 520 may be composed of P++/N+/N++ Si positioned in contact with electrodes 540 and 570. According to the doping level of Si, the rectification ratio and the current level may be adjusted, and it can be matched to the current level of the memory. An electrode 540, SiOx layer 540, and electrode 550 may be provided for the silicon oxide memory. The SiOx can be formed by Spin-on Glass (SOG) to planarize the rough surface. A passivation layer 560 may be provided to protect the device from environmental conditions. In some embodiments, deposition methods for SiOx might need CMP (chemical mechanical planarization). It can be envision that the 1D-1R crossbar device forms from the well-defined Si diode's rectification property, but this poses scalability issues (<50 nm) due to increases of the leakage current by tunneling at the thin Schottky barrier.
[0068] (3) 1D-1R based on the pn diode and the nanoporous silicon oxide memory: A 1D-1R junction structure as shown in FIGS. 6A-6B can be extended to a 3D stackable memory. Diode fabrication: The bottom electrode 620 (e.g. Ti/Pt/Ti) of the diode device was deposited by an electron beam evaporator or a sputterer onto a SiO2/Si substrate 610. In order to make ohmic contact, the TiO2 (20-30 nm) was deposited by an atomic layer deposition. After, Pt metal was deposited on the TiO2 layer for making of a Schottky barrier 630. SiOx layer 640 and electrode 650 may be provided for the silicon oxide memory in contact with Schottky barrier 630. A passivation layer 660 may be provided to protect the device from environmental conditions. Other oxide-based selectors (threshold switch or diode) can be used in this structure. While the above discusses a specific order of integration, it will be understood by one of ordinary skill in the art that other embodiments may rearrange the order of integration. For example, in some embodiments, the order of integration of the device can be changed, such as to position the memory below the diode or to for a 1R-1D structure.
[0069] 3D stackable 1D-1R device: A stacking 1D-1R junction structure is shown in FIG. 7 . Bottom electrode 720 (e.g. Ti/Pt/Ti) is provided on a substrate 710 (SiO2/Si). A first Schottky barrier 740 (e.g. Pt/TiO2) is provided on top of bottom electrode 720. A first nanoporous silicon oxide memory is provided by SiOx layer 730 and electrode 740. A second Schottky barrier 750 (e.g. TiO2/Pt) is also provided. A second nanoporous silicon oxide memory is provided SiOx layer 730 and electrode 760 in contact with second Schottky barrier 750. A passivation layer 770 may be provided to protect the device from environmental conditions. The second diode layer should be located on the SiOx memory junction in the first layer of 1D-1R. Other embodiments may rearrange the order of integration. For example, in some embodiments, the order of integration of the device can be changed, such as to a 1R-1D structure.
[0070] Experimental Example
[0071] The following example discussed below, as well as other examples, is included to demonstrate particular aspects of the present disclosure. It should be appreciated by those of ordinary skill in the art that the methods described in the examples that follow merely represent illustrative embodiments of the disclosure. Those of ordinary skill in the art should, in light of the present disclosure, appreciate that many changes can be made in the specific embodiments described and still obtain a like or similar result without departing from the spirit and scope of the present disclosure.
[0072] As a nonlimiting example, the NP SiOx structure shown was prepared by anodic galvanostatic etching of SiO2 with 1 vol % HF in ethanol solution to afford a significantly roughened morphology of the deposited SiOx film (e.g. FIGS. 1B and 11A-11D ). Transmission electron microscopy (TEM) micrographs show that nanoscale holes in the SiOx film are approximately randomly distributed with diameters ranging from 2 to 6 nm (FIGS. 1C and 11A-11D ). The average porosity of the NP SiOx film can be defined by its effective refractive index (n) based on the Bruggemann effective medium approximation, which was estimated by the numerical fitting of a visible reflectance spectrum of the NP SiOx film. The optically defined average porosity value of the NP SiOx material was p=25% (FIG. 1D ); the etching process created a substantially nanoporous SiOx material. However, no significant change was made in their composition according to X-ray photoelectron spectroscopy (XPS) of NP SiOx (x=1.63 to 1.76) relative to non-porous SiOx (FIGS. 1E-1F and 12 ). Note that the Pt layer is fully exposed by over-etching when 5 vol % HF is used, which results in no switching behavior (FIG. 12 ). Additional details on the fabrication process, measurements, and porosity calculation for the NP SiOx memory are discuss further below. The top contacts (Au or Pt) were subsequently applied and no further etching of the individual devices is required (FIG. 12 ).
[0073] FIG. 1G shows a typical switching I-V curve of the NP SiOx memory after an electroforming process, where no Ic is applied. All NP SiOx memories showed a unipolar switching behavior similar to that of a non-porous SiOx memory with ION and IOFF controlled by a constant polarity of set and reset voltages. This is a greatly simplified electroforming process relative to non-porous SiOx (FIG. 13A-13C ). Electroforming of the NP SiOx memory can be achieved by a single low-voltage sweep to a breaking voltage (Vbreak=1.4 V) where a current suddenly drops, thus we can define the Vbreak as the Vforming, as shown in the inset of FIG. 1G . In addition, the junction vertical edge of non-porous SiOx memory is essential for the electroforming process and switching. For non-porous SiOx, an exposed vertical edge is often provided between the two electrodes to allow a filament to form during an electroforming process. However, as shown in FIGS. 13B-13C , the vertical edge was not needed for the NP SiOx, exemplifying the marked ease in fabrication demands. The I-V behavior in FIG. 1G (inset) is typical of metal filament breakage, and at that point, the Si nanofilament is likely formed in the metal gap region. The NP SiOx memory with an Au top-electrode required Vforming of only ˜1.6 V on average to form a switching path, compared to the significantly higher Vforming for a non-porous SiOx memory of >20 V (FIGS. 14A-14C ). The low forming voltage and a single sweep for the electroforming process are advantageous in high-density integration of nanoscale memory cells with diodes by avoiding potential breakdowns due to a the high forming voltage and by repeated voltage sweeps. The single low voltage sweep also mitigates the problematic Joule-heating-damage to the surrounding SiOx material, thus reducing the uncertainty in the stochastic formation of the switching filament. The NP SiOx memory using a Pt top-electrode instead shows similar switching behavior with, as expected, a slightly higher Vforming≅2.1 V (FIG. 15A-15B ). Similar switching speeds (sub-50 ns, measurement limit) for the set and reset process were observed in the NP SiOx memory (FIG. 16 ) as compared to that of the non-porous SiOx memory.
[0074] In order to evaluate the sensitivity and stability of the switching filament in the NP SiOx memory, the switching current levels and the retentions at 1.0 V after different voltage pulses (Vpulse) on the same cell of the device were tested. FIG. 8A shows the switching I-V behavior for 9-bits after different Vpulse changed from 13 V to 4 V (with ΔV=1 V). The Au top contact had a 100 μm radius while the NP SiOx was 40 nm thick. FIG. 8B shows current (A) retention results at two different temperatures (20° C. and 100° C.) after the Vpulse. The ON-OFF ratios of each state are varied from ˜2.5 to 107 according to the Vpulse and are maintained for 104 s even at 100° C. When the Vpulse was decreased, the read-current (Iread) at 1.0 V increased while the set voltage (Vset) decreased (FIG. 8A inset), similar to the behavior of the non-porous SiOx memory. It has been suggested that the conducting filament comprising of silicon nanocrystals (Si NCs) can be significantly disrupted by the higher Vpulse, which results in lower Iread. To our knowledge, however, this is the first demonstration of an oxide-based memory device with a 9-bits switching ability with ON-OFF ratio≅107 A, making this device promising as a multi-bit memory system. Moreover, this multi-bit feature, coupled with the 5 nm diameter Si NC filament, makes the RRAM device attractive for aggressive equivalent scaling.
[0075] The switching endurance stability is a crucial factor for the practical application of nonvolatile memory devices, which is one of the main challenges in unipolar memory. In the case of non-porous SiOx, the ON- and OFF-current values became similar after 103 to 104 cycles demonstrating its limited life cycle due to the extensive aggregation of the Si NCs formed in the switching path by accumulated voltage stresses, which causes the indistinctive switching states (FIG. 8C , top). In contrast, the ON-OFF ratio of the NP SiOx memory was significantly less degraded during 103 cycles and shows at least 106 ON-OFF ratio (FIG. 8C , bottom). Interestingly at 2×103 cycles for the NP SiOx, the OFF-current increased and maintained 10−7 A (FIG. 17A ). After that, it was demonstrated an excellent endurance property of 103 ON-OFF ratio during 105 cycles, as shown in FIGS. 8C-8D and 17B .
[0076] To identify the switching mechanism of the NP SiOx memory, a planar model structure of the SiOx memory device was fabricated using an Au nanowire with a width of 60 nm. When an initial voltage sweep was applied to the Au nanowire, an electrical breakdown occurred at 1.25 V by the electromigration of Au and the electrical current suddenly dropped (top and inset of FIG. 9A ), which would be conceptually similar to the occurrence in the vertical NP SiOx memory. The SEM image shows a relatively dark region near the gap indicating the intrinsic post-breakdown of underlying SiOx by the thermal damage induced by electromigration (FIG. 18B ). A subsequent electric potential (>1.25 V) at the local confinement (≤20 nm) could easily change the SiOx to a Si-phase (Si NC or a-Si), as demonstrated previously. The planar model device showed the typical SiOx unipolar switching behavior after this breakdown process (FIG. 9A ), which offers a route to decrease the Vforming without a thermal annealing treatment. The post-breakdown process of SiOx could help to form the switching filament at a low bias, which leads to the extended endurance cycles as well (FIG. 18B ). Note that SiOx memories analogous to this planar model structure have been previously reported, but with various electrode materials including α-carbon, TiN, carbon nanotubes, and graphene, and they all showed a similar breakdown process at an initial I-V sweep. Therefore, it is suggest that the switching mechanism of the NP SiOx can be understood by the breakdown process of Au on the sidewalls of nano-holes through the SiOx film as illustrated in FIG. 9B . Interestingly, the initial switching state of the NP SiOx memory has either an ON or OFF state after the breakdown process, which means that the switching path in the vertical-nanogap is mainly formed by a Si NC or a-Si (FIGS. 14A-14B ). This mechanism, based on the electromigration of a metal wire, can also explain why the Vforming of NP SiOx using the more refractory Pt top-electrode has the slightly higher value than that of the NP SiOx using the Au top-electrode (FIGS. 14A-14C and 15A-15B ).
[0077] The demonstrated RRAM switching parameters of the NP SiOx memory, including the set current, the ON power, the Vforming, and ON-OFF ratio with the endurance cycles, are compared with the reported unipolar memories as well as other types of non-porous SiOx memories using metal electrodes, as shown in FIGS. 10A-10D . In the comparison, the set-current (1.4±0.9×10−5 A), the ON power (6.2±4.0×10−5 W/bit), and Vforming (1.6±0.4 V) are the lowest values while the ON-OFF ratio was slightly higher at the given number of cycles for this NP SiOx memory (see FIG. 19 , Table 2, where the first two are NP SiOx unipolar memory and the remaining entries are non-porous unipolar memory). Importantly, many unipolar memories require Ic(denoted as “[c]” in FIGS. 10A-10D ), junction edge-switching [e], or the high temperature processing [T] for the switching, whereas the NP SiOx devices do not require any of these, which is an important consideration for large-scale fabrication of nonvolatile memory technologies.
[0078] Clearly, the RRAM memory structure using a NP SiOx can show excellent switching behavior far beyond the current unipolar memory systems and enables simpler fabrication and operating procedures than bipolar RRAMs. The switching mechanism can be explained by the breakdown process of an initial metal connection at a low bias regime that can effectively mitigate the undesired Joule-heating-damage of the switching path at Vforming. The results suggest that the NP SiOx memory system could offer a new device paradigm for future memory applications.
[0079] Fabrication of the NP SiOx memory device. The NP SiOx memory devices were fabricated on a p-type (100) Si substrate (15 mm×15 mm) covered with a thermally grown 300 nm-thick SiO2 layer. A Pt bottom-electrode (100 nm) was deposited on the substrate by sputtering or e-beam evaporation after a typical cleaning process with acetone, isopropyl alcohol, and deionized (DI) water by ultrasonication (bath) for 3 min. Then, SiOx (30-50 nm thick) was deposited on the Pt bottom electrode by using e-beam evaporation (at room temperature) or plasma-enhanced chemical vapor deposition (PECVD) (for 1 to 2 min at 300° C.). The NP SiOx devices prepared by e-beam evaporation and PECVD show similar switching behaviors. To electrochemically form a porous structure within the deposited SiOx, we performed an anodic galvanostatic treatment of the samples in a dilute HF/ethanol solution (S1-S3). The dilute HF/ethanol solution with concentrations of 1 and 5 vol % were prepared by diluting HF (48 to 51 vol %, J. T. Baker) in absolute ethanol (Pharmo). A two-electrode system was used in the anodic treatments with the SiOx on a Si substrate as an anode and Pt foil as a cathode. A constant current density of 6.4 mA/cm2 was applied for 30 s to form the NP structure in the SiOx thin layer. After this anodic etching, samples were rinsed with DI water and dried under a nitrogen flow. Using a circular photo-mask or a circular shadow metal mask method, a top electrode (Au or Pt) was deposited on the NP SiOx layer with a radius of ˜100 μm. An example of the resulting device is shown in FIG. 1A .
[0080] Fabrication of the Au—SiOx—Au nanogap memory device. The Au nanowire junctions (˜60 nm wide) were patterned on Si/SiO2 substrates by conventional e-beam lithography (JEOL 6500F SEM) with 950 PMMA resist. The e-beam current was 300 pA at 30 kV acceleration voltage. Patterns were developed in 1:3 methyl isobutyl ketone (MIBK)-isopropyl alcohol (IPA) developer, followed by the sputter deposition of 50 nm thick Au (Denton Desk V Sputter system). After the breaking process of Au nanowire by electromigration, the Au—SiOx—Au nanogap memory device was fabricated. An example of the resulting device is shown in FIG. 9A .
[0081] Optical measurement and porosity calculation. The reflectance spectra of as-deposited and NP SiOx layers on Pt-deposited silicon substrate were measured with a visible spectrometer (USB4000, Ocean Optics) connected to an optical microscope (a numerical aperture of 0.4, Axioskop, Zeiss). A bare Pt film was used for a reflectance reference. The effective refractive index of the NP SiOx layers was calculated by the numerical fitting of the measured reflectance spectra based on an analytical formula and thicknesses information of the SiOx layers from cross-sectional SEM images. Through all numerical calculations, the optical dispersion relation was included for both Pt and silica. The porosity value corresponding to the effective refractive index of the etched SiOx was calculated using the Bruggemann effective medium approximation (S4).
[0082] Scanning electron microscope (SEM) characterization. RRAM structures having unetched or etched SiOx layer were cleaved and characterized by a field emission SEM (JEOL 6500F, 10 kV). All SEM images were taken without additional conduction layer deposition after grounding the Pt bottom-electrode. The changes in thickness and surface morphology due to the etching process were observed from the high resolution SEM images (FIGS. 11A and 11C ).
[0083] Transmission electron microscopy (TEM) characterization. The morphology and porous feature of the SiOx were assessed by bright field images taken at 200 keV on a field emission TEM (JEOL 2100). In order to prepare a sample for the TEM analysis, a NP SiOx film was formed on Ni (20 nm)/SiO2/Si substrate. The SiOx sample was dipped in 1 M HCl solution for 12 h to etch the Ni and was picked up by a TEM grid. The sample was dried overnight after thoroughly removing chemical residues using DI water. See FIGS. 11B and 11D .
[0084] X-ray photoelectron spectroscopy (XPS) analysis. The unetched and etched SiOx films on Pt metal were investigated for their chemical composition by XPS (PHI Quantera XPS, Physical Electronics, USA). All the XPS spectra were calibrated according to the binding energy of the C1s peak at 284.5 eV.
[0085] Electrical measurements. The electrical characterizations were performed under vacuum (<10−3 Ton) (Desert Cryogenics model CPX, Lakeshore Cryotronics, Inc.) using a B 1500 semiconductor parameter analyzer equipped with a pulse generator. All electrical measurements were obtained with the bias voltage applied to the bottom Pt electrode while the top Au (or Pt) electrode on the NP SiOx was grounded.
[0086] Embodiments described herein are included to demonstrate particular aspects of the present disclosure. It should be appreciated by those of skill in the art that the embodiments described herein merely represent exemplary embodiments of the disclosure. Those of ordinary skill in the art should, in light of the present disclosure, appreciate that many changes can be made in the specific embodiments described and still obtain a like or similar result without departing from the spirit and scope of the present disclosure. From the foregoing description, one of ordinary skill in the art can easily ascertain the essential characteristics of this disclosure, and without departing from the spirit and scope thereof, can make various changes and modifications to adapt the disclosure to various usages and conditions. The embodiments described hereinabove are meant to be illustrative only and should not be taken as limiting of the scope of the disclosure.
Claims
What is claimed is:
1. A method for forming a memory device, the method comprising:
(a) depositing a bottom electrode on a substrate;
(b) depositing a memory material layer on the bottom electrode, wherein the memory material layer is SiOx, where 0.2≤x≤2;
(c) etching the memory material layer to form a pore that extends through the memory material layer to the bottom electrode, wherein the pore defines an internal volume within the memory material layer;
(d) depositing a top electrode of electrode material onto the memory layer and into the pore: and then
(e) creating a switching channel of silicon between the electrode material within the pore and the bottom electrode by electroforming the memory material.
2. The method of claim 1, wherein the pore has a size measured perpendicularly to a thickness of the memory material layer, the size being between 0.1 to 10 nanometers (nm).
3. The method of claim 1, wherein the pore is formed by anodic etching, E- beam lithography, or RIE with nanoparticles.
4. The method of claim 3, wherein the anodic etching is performed in a HF/ethanol solution.
5. The method of claim 4, wherein the HF/ethanol solution has a concentration equal to or between 0.01-10%.
6. The method of claim 1, wherein creating the switching channel further comprises electroforming with a single voltage sweep having a peak of less than 5 V.
7. The method of claim 1, wherein the memory device provides cycling endurance equal to greater than 2×103 cycles.
8. The method of claim 1, wherein the memory device provides multi-bit storage in a single cell.
9. The method of claim 1, wherein the memory device provides a power consumption 6×10−5 W/bit or less.
10. The method of claim 1, wherein the memory device is part of a one diode-one resistor (1D-1R), one selector-one resistor (1S-1R), or one transistor-one resistor (1T-1R) junction structure.
11. The method of claim 1, wherein the memory device is a memristor.
12. A memory device comprising:
(a) a bottom electrode;
(b) a top electrode of electrode material;
(c) a memory material disposed between the bottom electrode and the top electrode, wherein the memory material is Siox where 0.2 ≤×≤2;
(d) a pore that extends between the top electrode and the bottom electrode through the memory material, wherein
(i) the pore defines an internal volume within the memory material, and
(ii) the electrode material of the top electrode extends into the internal volume of the pore; and
(e) a switching channel of silicon electrically coupled between the electrode material within the internal volume and the bottom electrode, wherein the switching channel configured to switch between a first resistance and a second resistance higher than the first resistance based on application between the top and bottom electrodes of a voltage.
13. The device of claim 12, wherein the pore has a size measured perpendicularly to a thickness of the memory material, the size being between 0.1 to 10 nanometers (nm).
14. The device of claim 12, wherein the memory device provides cycling endurance equal to or greater than 2×103 cycles.
15. The device of claim 12, wherein the memory device provides multi-bit storage in a single cell.
16. The device of claim 12, wherein the memory device provides a power consumption 6×10−5 W/bit or less.
17. The device of claim 12, wherein the memory device is part of a one diode-one resistor (1D-1R), one selector-one resistor (1S-1R), or one transistor-one resistor (1T-1R) junction structure.
18. The device of claim 12, wherein an electroforming voltage for the memory device is 10 V or less.
19. The device of claim 12, wherein a current lifetime of the memory device is equal to or greater than 104 seconds at 100 ° C.
20. The device of claim 12, wherein the memory device is a memristor.
21. The memory device of claim 12, wherein the switching channel is configured to have the first resistance based on application of between 3 and 6 Volts, inclusive, between the top electrode and the bottom electrode, and the switching element is configured to have the second resistance based on application of 7 Volts or greater between the top electrode and the bottom electrode.
22. The memory device of claim 12, wherein
(a) the switching channel is configured to have the first resistance based on application of a first voltage between the top electrode and the bottom electrode, wherein,
(i) upon application of the first voltage, the switching channel is operable to comprise a conducting filament comprising silicon nanocrystals or a-Si;
(b) the switching element is configured to have the second resistance based on application of a second voltage between the top electrode and the bottom electrode, wherein
(i) upon application of the second voltage, the switching channel is operable to comprise a broken down conducting filament, and
(ii) the first voltage is less than the second voltage.
23. The method of claim 1 further comprising creating a first resistance across the switching channel by applying between 3 and 6 Volts, inclusive, between the top electrode and the bottom electrode, and creating a second resistance of the switching element, the second resistance higher than the first resistance, by applying 7 Volts or greater between the top electrode and the bottom electrode.
24. The method of claim 1 further comprising
(a) creating a first resistance across the switching channel by applying a first voltage
(i) between the top electrode and the bottom electrode, wherein applying the first voltage results in a conducting filament comprising silicon nanocrystals or a-Si positioned between the top electrode and the bottom electrode; and
(b) creating a second resistance of the switching element by applying a second voltage between the top electrode and the bottom electrode, wherein
(i) applying the second voltage results in a breakdown in the conducting filament, and
(b) the first voltage is less than the second voltage.
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