Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure

[0001] This application is related to the following co-pending an commonly assigned patent applications: U.S. application Ser. No. 13/943,157, filed on Jul. 16, 2013 and entitled “Front-to-back bonding with through-substrate via (TSV)”, and U.S. application Ser. No. 13/943,224, filed on Jul. 16, 2013 and entitled “Hybrid bonding with through substrate via (TSV)”, U.S. application Ser. No. 14/752,342, filed on Jun. 26, 2015 and entitled “Hybrid bonding with through substrate via (TSV)”, U.S. application Ser. No. 13/943,401, filed on Jul. 16, 2013 and entitled “Hybrid bonding with through substrate via (TSV)”, and U.S. application Ser. No. 14/488,017, filed on Sep. 16, 2014 and entitled “Hybrid bonding with through substrate via (TSV)”.

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are typically packaged separately, in multi-chip modules, or in other types of packaging, for example.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications.

[0004] Three dimensional integrated circuits (3DICs) are a recent development in semiconductor packaging in which multiple semiconductor dies are stacked upon one another, such as package-on-package (PoP) and system-in-package (SiP) packaging techniques. Some 3DICs are prepared by placing dies over dies on a semiconductor wafer level. 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked dies, as examples. However, there are many challenges related to 3DICs.

[0011] It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the performance of a first process before a second process in the description that follows may include embodiments in which the second process is performed immediately after the first process, and may also include embodiments in which additional processes may be performed between the first and second processes. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. Furthermore, the formation of a first feature over or on a second feature in the description may include embodiments in which the first and second features are formed in direct or indirect contact.

[0012] FIGS. 1A-1E show cross-sectional representations of various stages of forming a semiconductor device in accordance with some embodiments of the disclosure. Referring to FIG. 1A, a cross-sectional representation of a portion of a semiconductor wafer 100 and a portion of another semiconductor wafer 200 are shown in accordance with some embodiments.

[0013] Semiconductor wafer 100 includes a semiconductor substrate 104, which is made of silicon or other semiconductor materials, and has a top surface 104a and a bottom surface 104b in accordance with some embodiments of the disclosure. Alternatively or additionally, semiconductor substrate 104 may include other elementary semiconductor materials such as germanium. In some embodiments, semiconductor substrate 104 is made of a compound semiconductor, such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, semiconductor substrate 104 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, semiconductor substrate 104 includes an epitaxial layer. For example, semiconductor substrate 104 has an epitaxial layer overlying a bulk semiconductor.

[0014] Referring to FIG. 1A, device regions 103 are formed in a front-side 100a of semiconductor wafer 100 in a front-end-of-line (FEOL) process in accordance with some embodiments of the disclosure. Each device region 103 includes a gate structure 109 embedded in a dielectric layer 107, source/drain regions 110, and isolation structures 112, such as shallow trench isolation (STI) structures. Gate structure 109 includes a gate dielectric layer 106, a gate electrode 108, and spacers (not shown). Device regions 103 shown in FIG. 1 are merely examples, and other devices may be formed in device regions 103.

[0015] Device regions 103 may form various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors or memories, and the like, interconnected to perform one or more functions. Other devices, such as capacitors, resistors, diodes, photo-diodes, fuses, and the like may also be formed in substrate 104. The functions of the devices may include memory, processing, sensor, amplifier, power distribution, input/output circuitry, or the like. In some embodiments, device regions 103 are NMOS and/or PMOS transistors.

[0016] An interconnect structure 122 is formed over substrate 104, e.g., over device regions 103. In some embodiments, interconnect structure 122 includes a contact plug 114 and conductive features 124. Conductive features 124 are embedded in an insulating material 126. Interconnect structure 122 is formed in a back-end-of-line (BEOL) process in some embodiments. In some embodiments, contact plug 114 is made of conductive materials, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloys, or combinations thereof. Conductive features 124 are also made of conductive materials, such as copper, copper alloy, aluminum, aluminum alloys, or combinations thereof. Alternatively, other applicable materials may be used. In some embodiments, conductive features 124 include multi-layers made of various materials, such as a plurality of metallization structures.

[0017] In some embodiments, insulating material 126 is made of silicon oxide. In some embodiments, insulating material 126 includes multiple dielectric layers of dielectric materials. In some embodiments, a top dielectric layer of the multiple dielectric layers is made of SiO₂. Interconnect structure 122 shown is merely for illustrative purposes. Interconnect structure 122 may include other configurations and may include one or more conductive lines and via layers.

[0018] A bonding layer 142, which is a dielectric layer, is formed over interconnect structure 122. Bonding layer 142 is made of a silicon-containing dielectric, such as silicon oxide, silicon oxynitride or silane oxide.

[0019] In some embodiments, bonding layer 142 is formed by plasma enhanced chemical vapor deposition (PECVD). In some other embodiments, bonding layer 142 is formed by a spin-on method. In some embodiments, bonding layer 142 has a thickness in a range from about 5 nm to about 800 nm.

[0020] As shown in FIG. 1A, devices, such as transistor including gate structure 109, are formed in front-side 100a of semiconductor wafer 100, while no devices are formed in a backside 100b of semiconductor wafer 100. In addition, the transistor including gate structure 109 is electrically connected to interconnect structure 122.

[0021] Semiconductor wafer 200 includes a substrate 204, which is similar to substrate 104. Substrate 204 has a top surface 204a and a bottom surface 204b. A bonding layer 242, which is a dielectric layer, is formed on bottom surface 204b of substrate 204. Bonding layer 242 is similar to bonding layer 142. No devices are pre-formed in semiconductor wafer 200.

[0022] As shown in FIG. 1A, semiconductor wafer 200 has a height H₁ from top surface 204a to bottom surface 204b of substrate 204 of semiconductor wafer 200 in a range from about 50 μm to about 775 μm.

[0023] Before semiconductor wafers 100 and 200 are bonded together, surfaces of bonding layers 142 and 242 are treated to improve the bonding. Bonding layers 142 and 242 are treated by a dry treatment or a wet treatment. The dry treatment includes a plasma treatment. In some embodiments, the plasma treatment is performed in an inert environment, such as an environment filled with inert gas including N₂, Ar, He, or combinations thereof. Alternatively, other types of treatments may be used. In some embodiments, both of bonding layers 142 and 242 are made of silicon oxide, and a plasma process is performed to bonding layers 142 and 242 to form Si—OH bonds on the surface of bonding layers 142 and 242 prior to bonding.

[0024] Referring to FIG. 1B, semiconductor wafer 100 is boned to semiconductor wafer 200 by bonding dielectric layers 142 and 242 to form a 3DIC stacking structure (die stack) 300 in accordance with some embodiments of the disclosure. As shown in FIG. 1B, when semiconductor wafer 200 is bonded to semiconductor wafer 100, bottom surface 204b of substrate 204 faces top surface 104a of substrate 104. Bonding of bonding layers 142 and 242 of semiconductor wafers 100 and 200 is performed under pressure and heat. In some embodiments, the pressure for bonding is in a range from about 0.7 bar to about 10 bar. In some embodiments, an anneal operation is applied to bond semiconductor wafers 100 and 200 at a temperature in a range from about 20° C. to about 1000° C. The bonding process may be performed in an inert environment, such as an environment containing N₂, Ar, He, or combinations thereof.

[0025] As shown in FIG. 1B, stacking structure 300 includes a bonding structure 150. Bonding structure 150 includes bonding layers 142 and 242 bonded together. Therefore, backside 200b of semiconductor wafer 200 is bonded to front-side 100a of semiconductor wafer 100. If some devices are formed in semiconductor wafer 200 before bonding, semiconductor wafers 100 and 200 have to be precisely aligned before bonding. In contrast, since no devices are pre-formed in semiconductor wafer 200, alignment is not required for bonding of semiconductor wafers 100 and 200.

[0026] After the bonding of semiconductor wafers 100 and 200, a thinning process 11 is performed on top surface 204a of substrate 204 in accordance with some embodiments of the disclosure, referring to FIG. 1C. Thinning process 11 may include a grinding operation and a polishing operation, such as chemical mechanical polishing (CMP). After thinning process 11, a wet etching operation is performed to remove the defects formed on top surface 204a of substrate 204. In some embodiments, after thinning process 11, semiconductor wafer 200 has a height H₂ from top surface 204a′ to bottom surface 204b of substrate 204 of semiconductor wafer 200 in a range from about 0.2 μm to about 10 μm. Height H₂ is smaller than height H₁. In some embodiments, a ratio of height H₂ to height H₁ is in a range from about 0.0002 to about 0.99. After thinning semiconductor wafer 200, device regions 203 are formed in semiconductor wafer 200 in accordance with some embodiments of the disclosure, referring to FIG. 1D. Device regions 203 are formed in a front-side 200a of semiconductor wafer 200 in a front-end-of-line (FEOL) process in some embodiments. Each device regions 203 includes a gate structure 209 embedded in a dielectric layer 207, source/drain regions 210, and isolation structures 212, such as shallow trench isolation (STI) structures. Gate structure 209 includes a gate dielectric layer 206, a gate electrode 208, and spacers (not shown). A contact plug 2142 is formed over device regions 203.

[0027] As shown in FIG. 1D, devices, such as transistors including gate structure 209, are formed in front-side 200a of semiconductor wafer 200, while no devices are formed in backside 200b of semiconductor wafer 200. In addition, backside 200b of semiconductor wafer 200 is bonded to front side 100a of semiconductor wafer 100, and therefore the resulting stacking structure is a front-to-back (face-to-back) stacking structure.

[0028] After device regions 203 are formed, through-substrate via (TSV) 400 is formed through second semiconductor wafer 200. Through-substrate via (TSV) 400 is used to provide electrical connections and for heat dissipation for 3DIC stacking structures. In some embodiments, TSV 400 is electrically connected to conductive feature 124a. Although FIG. 1D only shows one TSV, more than one TSV may be formed to pass through second semiconductor wafer 200.

[0029] TSV 400 includes a liner 410, a diffusion barrier layer 420, and a conductive material 430, in accordance with some embodiments. Liner 410 is made of an insulating material, such as oxides or nitrides. Liner 410 may be formed by using a plasma enhanced chemical vapor deposition (PECVD) process or other applicable processes. In some embodiments, diffusion barrier layer 420 is made of Ta, TaN, Ti, TiN, or CoW. In some embodiments, diffusion barrier layer 420 is formed by a physically vapor deposition (PVD) process or atomic layer deposition (ALD) process. In some embodiments, conductive material 430 is made of copper, copper alloy, aluminum, aluminum alloys, or combinations thereof. In some embodiments, conductive material 430 is formed by plating.

[0030] As shown in FIG. 1D, since the height of substrate 204 is reduced from H₁ to H₂, aspect ratio of TSV 400 is reduced. Therefore, the void problems and the extrusion or diffusion problems resulting from a high aspect ratio of the TSV are resolved or greatly reduced. In addition, the overall package height of 3DIC stacking structure 300 is reduced to meet advanced packaging requirements. Therefore, 3DIC stacking structure 300 achieves small form factor.

[0031] In some embodiments, TSV 400 has a width W₁ in a range from about 0.025 μm to about 4 μm. In some embodiments, TSV 400 has a depth D₁ in a range from about 0.2 μm to about 10 μm. In some embodiments, TSV 400 has an aspect ratio (D₁/W₁) in a range from about 2 to about 15.

[0032] After TSV 400 is formed, an interconnect structure 500 is formed on front-side 200a of second semiconductor wafer 200 in accordance with some embodiments, referring to FIG. 1E. Interconnect structure 500 is electrically connected to conductive features 124a of semiconductor wafer 100 via TSV 400. Interconnect structure 500 includes conductive features 510, such as conductive lines, vias, or conductive pads, formed in an insulating material 520. The metal routings of the conductive features shown in FIG. 1E, are merely examples. Alternatively, other designs of metal routings of conductive features may be used according to actual application. In addition, other processes may also be performed to 3DIC stacking structure 300, and 3DIC stacking structure 300 may be diced to form individual chips afterwards. Referring to FIG. 1F, the TSV 400 directly contacts with a first cap metal layer 125 which is formed over the conductive features 124a.

[0033] FIG. 2 shows an enlarged cross-sectional representation of region R in FIG. 1D in accordance with some embodiments of the disclosure. Region R shows a portion of conductive feature 124. A stop layer 132 is formed over insulating material 126. Conductive feature 124 is formed in insulating material 126, and it is surrounded by a diffusion barrier layer 123. Diffusion barrier layer 123 may be made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or aluminum nitride (AlN). For example, conductive feature 124 is made of copper, and diffusion barrier layer 123 includes TaN/Ta bi-layer.

[0034] In order to eliminate or reduce migration and diffusion of metal of conductive feature 124 into adjacent insulating material 126, a dielectric capping layer 134 is formed over conductive feature 124. In addition, dielectric capping layer 134 is also located over diffusion barrier layer 123, stop layer 132, and insulating material 126. In some embodiments, dielectric capping layer 134 and stop layer 132 are respectively made of dielectric layer, such as silicon nitride (e.g., SiN), silicon oxynitride (e.g., SiON), silicon carbide (e.g., SiC), silicon oxycarbide (e.g., SiOC or SiCO), or silicon carbide nitride (e.g., SiCN). It will be appreciated that the stoichiometry of the respective dielectric layers may be varied according to chemical vapor deposition (CVD) processing variables, including the altering of relative ratios of reactants to achieve a desired compressive stress of the film. Materials of dielectric capping layer 134 may be the same or similar to that of stop layer 132. For example, dielectric capping layer 134 and stop layer 132 are both made of silicon nitride. However, since the material of dielectric capping layer 134 is rigid, some cracks would be formed in dielectric capping layer 134 under high temperature. In addition, the difference of thermal expansions between dielectric capping layer 134 and conductive feature 124 would also lead to the formation of cracks during high temperature processes. Such cracks results in reducing of reliability, and yield is therefore reduced.

[0035] As described previously, devices, such as transistors in device regions 203, are formed in front-side 200a of semiconductor wafer 200, and some fabricating processes for the devices are performed in high temperature operation, such as a rapid thermal process (RTP). For example, the temperature is in a range from about 500° C. to about 1200° C. Therefore, dielectric capping layer 134 is damaged during the high temperature fabrication process.

[0036] In order to solve the cracking problem, a cap metal layer 125 is formed over conductive feature 124 to replace dielectric capping layer 134. In some embodiments, cap metal layer 125 is made of Ni, NiB, NiWB, Co, CoWB, CoWP, or NiReP. Since cap metal layer 125 is made of a relatively soft material and the difference of thermal expansions between cap metal layer 125 and conductive feature 124 is relatively small, cracks are not formed on cap metal layer 125.

[0037] FIGS. 3A-3D show cross-sectional representations of various stages of forming interconnect structure 122 in accordance with some embodiments of the disclosure. Referring to FIG. 3A, interconnect structure 122 includes a single damascene structure used as a first metallization layer M1 (shown in FIG. 3D) in accordance with some embodiments of the disclosure. First metallization layer M1 includes stop layer 132 formed over insulating layer 126 (such as inter-metal dielectric, IMD) and dielectric layer 107. An opening 150 is formed in insulating layer 126 to expose a portion of dielectric layer 107. It is noted that opening 150 is connected to contact plug 114 although it is not shown in FIG. 3A. In some embodiments, opening 150 has a width W₂ in 0.03 μm to about 5 μm. Insulating layer 126 and dielectric layer 107 are described above and detail description are not repeated again for brevity.

[0038] In some embodiments, if the metal (such as copper) of conductive feature 124 formed later is easy to diffuse, a diffusion barrier layer 123 is needed. Referring to FIG. 3B, a diffusion barrier layer 123 is formed on the sidewalls and the bottom of opening 150 in accordance with some embodiments of the disclosure. After forming diffusion barrier layer 123, conductive feature 124 is used to fill opening 150. Conductive feature 124 is described above and detail descriptions are not repeated again for brevity. Conductive feature 124 is surrounded by diffusion barrier layer 123.

[0039] Referring to FIG. 3C, a chemical mechanical polishing (CMP) process 11 is performed to remove the excess portion of diffusion barrier layer 123 and conductive feature 124 outside of opening 150 after conductive feature 124 is formed, in accordance with some embodiments of the disclosure.

[0040] Referring to FIG. 3D, a cap metal layer 125 is formed on conductive feature 124 and diffusion barrier layer 123 to prevent metal diffusion of conductive feature 124, in accordance with some embodiments of the disclosure. In addition, cap metal layer 125 is used to replace dielectric capping layer 134 (shown in FIG. 2) to avoid the crack. In some embodiments, cap metal layer 125 is formed by an electroless method. Therefore, cap metal layer 125 is self-aligned over conductive feature 124 by the electroless method without using a tedious photolithography process. In some embodiments, cap metal layer 125 has a thickness in a range from about 5 Å to about 700 Å.

[0041] A portion of dielectric capping layer 134 must to be removed to expose conductive feature 124 in order to connect another metallization layer (not shown). In contrast, cap metal layer 125 shown in FIG. 3D is conductive. Another metallization layer (not shown) may be directly formed over cap metal layer 125 without excessive etching process.

[0042] FIG. 4 shows a cross-sectional representation of an interconnect structure 122′ in accordance with some embodiments of the disclosure. Interconnect structure 122′ includes a dual damascene structure having a second metallization layer M2 formed over a first metallization layer M1. Second metallization layer M2 is formed by the following operations. An insulating layer 126u is formed over first metallization layer M1. A dual damascene opening includes an upper trench section and a lower via-hole section formed in insulating layer 126u. A diffusion barrier layer 123u is formed to line the sidewalls and the bottom of the dual damascene opening. Afterwards, conductive feature 124u is filled into the dual damascene opening. After conductive feature 124u is formed, a chemical mechanical polishing (CMP) process is performed to remove the excess portion of diffusion barrier layer 123u and conductive feature 124u outside of the dual damascene opening.

[0043] Cap metal layer 125u is used to reduce migration and diffusion of metal of conductive feature 124u into the adjacent insulating material 126u. In addition, cap metal layer 125u is formed on conductive feature 124u and diffusion barrier layer 123u to avoid cracking. As shown in FIG. 4, interconnect structure 122′ includes lower conductive feature 124 and upper conductive feature 124u formed over lower conductive feature 124. In addition, lower metal cap layer 125 is formed between lower conductive feature 124 and upper conductive feature 124u, and upper metal cap layer 125u is formed on upper metal cap layer 125u. Since cap metal layer 125b is conductive, a third metallization layer (not shown) may be directly formed over cap metal layer 125b. In addition, interconnect structure 122′ may further include a number of metallization layers Mn (n is an positive integral) depending on applications.

[0044] In some embodiments, metal cap layer 125 is formed between conductive feature 124a and TSV 400 shown in FIG. 1E. Therefore, TSV 400 may extend from the front-side of semiconductor 200 to cap metal layer 125 on conductive feature 124a and electrically connects conductive features 510 in interconnect structure 150 and conductive feature 124a, as shown in FIG. 1E.

[0045] Embodiments of mechanisms for forming a semiconductor device structure are provided. A front-side of a first semiconductor wafer is bonded to a backside of a second semiconductor wafer to form a front-to-back (face-to-back) stacking structure. An interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer includes a cap metal layer to prevent metal diffusion and reduce cracking.

[0046] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconductor wafer. The semiconductor device also includes a second semiconductor wafer comprising a second transistor formed in a front-side of the second semiconductor wafer, and a backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device further includes a first interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer, and the first interconnect structure comprises a cap metal layer formed over a conductive feature. The first interconnect structure is electrically connected to first transistor, and the first cap metal layer is configured to prevent diffusion and cracking of the first conductive feature.

[0047] In some embodiments, a semiconductor device is provided. The semiconductor device structure includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconductor wafer and a first bonding layer formed over the first transistor. The semiconductor device structure further includes a second semiconductor wafer including a second transistor formed in a front-side of the second semiconductor wafer, and a backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device structure also includes a first interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer, and the first interconnect structure comprises a first cap metal layer formed over a first conductive feature. The first interconnect structure is electrically connected to the first transistor. The semiconductor device structure further includes at least one through substrate via (TSV) extending from the front-side of second semiconductor wafer to the first cap metal layer of the first semiconductor wafer.

[0048] In some embodiments, a method for forming a semiconductor device is provided. The method includes providing a first semiconductor wafer, and forming a first transistor and an interconnect structure over a front-side of the first semiconductor wafer, and the interconnect structure comprises a cap metal layer formed over a conductive feature. The method also includes providing a second semiconductor wafer, wherein no devices are formed in the second semiconductor wafer. The method further includes bonding the front-side of the first semiconductor wafer to a backside of the second semiconductor wafer. The method includes thinning a front-side of the second semiconductor wafer, and forming a second transistor in the front-side of the second semiconductor wafer.

[0049] Although embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.