Method and apparatus for compressing coding unit in high efficiency video coding

[0001] The present application is a continuation application of U.S. patent application Ser. No. 14/527,769, filed on Oct. 30, 2014, which is a divisional application of U.S. patent application Ser. No. 13/272,221, filed on Oct. 13, 2011, entitled “Method and Apparatus for Compressing Coding Unit in High Efficiency Video Coding” (now. U.S. Pat. No. 9,049,452, issued on Jun. 2, 2015), which claims priority to U.S. Provisional Patent Application Ser. No. 61/508,825, filed on Jul. 18, 2011, entitled “Method and syntax for compressing coding units in HEVC”. The present invention is also related to U.S. Non-Provisional patent application Ser. No. 13/012,811, filed Jan. 25, 2011, entitled “Apparatus and Method of Constrained Partition Size for High Efficiency Video Coding”. The U.S. Provisional Patent Application and U.S. Non-Provisional Patent Applications are hereby incorporated by reference in their entireties.

[0002] The present invention relates to video processing. In particular, the present invention relates to method and apparatus for compressing coding units in High Efficiency Video Coding (HEVC).

[0003] HEVC (High Efficiency Video Coding) is an advanced video coding system being developed under the Joint Collaborative Team on Video Coding (JCT-VC) group of video coding experts from ITU-T Study Group. In HEVC, a 2N×2N coding unit can be hierarchically partitioned into a partition type selected from 2N×2N, 2N×N, N×2N and N×N. The coding system uses a criterion to determine the best partition, where RD-rate is often used as the criterion. The N×N partition at level k is evaluated and the same partition, i.e., 2N×2N partition is also evaluated at level k+1. Therefore, N×N partition at level k becomes redundant if 2N×2N partition at level k+1 will be evaluated. In order to eliminate the above redundancy, the allowable partition sizes are constrained according to the method disclosed in U.S. Non-Provisional patent application Ser. No. 13/012,811, filed Jan. 25, 2011, entitled “Apparatus and Method of Constrained Partition Size for High Efficiency Video Coding”. In U.S. Non-Provisional patent application Ser. No. 13/012,811, for each leaf CU larger than the SCU (smallest CU), the partition sizes allowed are 2N×2N, 2N×N and N×2N. In other words, the N×N partition is not allowed for INTER mode if the leaf CU is larger than the SCU. If the leaf CU size is the same as SCU size, all partition sizes, 2N×2N, 2N×N, N×2N, and N×N, are allowed. While the method disclosed in U.S. Non-Provisional patent application Ser. No. 13/012,811 reduces computational complexity at the expense of modest performance loss, it is desirable to develop a method and apparatus that can further reduce the computational complexity with about the same performance. Furthermore, it is desirable to provide flexibility so that either the method and apparatus with further complexity reduction can be selected or an alternative method and apparatus can be selected.

[0004] A method and apparatus for decoding of a video bitstream are disclosed. In one embodiment, a method for decoding of a video bitstream includes receiving coded data for a 2N×2N coding unit (CU) from the video bitstream, selecting one or more first codewords according to whether asymmetric motion partition is disabled or enabled, selecting one or more second codewords when a size of said 2N×2N CU is equal to a smallest CU size, wherein none of said one or more second codewords corresponds to INTER N×N partition when N is 4, determining a CU structure for said 2N×2N CU from the video bitstream using said one or more first codewords or said one or more second codewords, and decoding the video bitstream using the CU structure.

[0005] In another embodiment, a method for processing coding units of video data comprises receiving input data associated with a 2N×2N coding unit (CU), selecting one or more first codewords according to whether asymmetric motion partition is disabled or enabled, selecting one or more second codewords when a size of said 2N×2N CU is equal to a smallest CU size, wherein none of said one or more second codewords corresponds to INTER N×N partition when N is 4, determining a CU structure for said 2N×2N CU, and encoding the CU structure using said one or more first codewords or said one or more second codewords.

[0017] During the encoding process, in order to achieve the best possible performance, the rate-distortion function or other performance criterion usually is evaluated for various coding unit (CU) partitions and prediction unit (PU) partitions. The PU design in the current HEVC development results in some redundancy to cause rate-distortion function or other performance criterion repeatedly evaluated for some PU configuration. For example, redundancy may exist between the configuration of the INTER N×N CU at depth=k and the configuration of the INTER 2N×2N CU at depth=k+1. The redundancy will cause unnecessary processing and waste valuable system resources. A method to alleviate the redundancy is disclosed in U.S. Non-Provisional patent application Ser. No. 13/012,811, filed Jan. 25, 2011, entitled “Apparatus and Method of Constrained Partition Size for High Efficiency Video Coding”, where a constrained CU partition has been developed to eliminate or reduce the redundancy in processing. Nevertheless, it is desired to develop coding unit compression method to further reduce the computational complexity. Also it is desirable to provide flexibility so that either the method and apparatus with further complexity reduction can be selected or an alternative method and apparatus can be selected. Furthermore, it is desired to design necessary syntax to convey the information related to the efficient and flexible partition between an encoder and a decoder.

[0018] In the high efficiency video coding (HEVC) system under development, the fixed-size macroblock of H.264/AVC is replaced by a flexible block, named coding unit (CU). FIG. 1 illustrates an exemplary coding unit partition based on a quadtree. At depth 0, the initial coding unit CU0, 112 consisting of 64×64 pixel, is the largest CU (LCU). The initial coding unit CU0, 112 is subject to quadtree split as shown in block 110. A split flag 0 indicates that the underlying CU is not split and, on the other hand a split flag 1 indicates the underlying CU is split into four smaller coding units CU1, 122 by the quadtree. The resulting four coding units are labeled as 0, 1, 2 and 3 and each resulting coding unit becomes a coding unit for further split in the next depth. The coding units resulted from coding unit CU0, 112 are referred to as CU1, 122. After a coding unit is split by the quadtree, the resulting coding units are subject to further quadtree split unless the coding unit reaches a pre-specified smallest CU (SCU) size. Consequently, at depth 1, the coding unit CU1, 122 is subject to quadtree split as shown in block 120. Again, a split flag 0 indicates the underlying CU is not split and, on the other hand a split flag 1 indicates the underlying CU is split into four smaller coding units CU2, 132 by the quadtree. The coding unit CU2, 132, has a size of 16×16 and the process of the quadtree splitting as shown in block 130 can continue until a pre-specified smallest coding unit is reached. For example, if the smallest coding unit is chosen to be 8×8, the coding unit CU3, 142 at depth 3 will not be subject to further split as shown in block 140. The collection of quadtree partitions of a picture to form variable-size coding units constitutes a partition map for the encoder to process the input image area accordingly. The partition map has to be conveyed to the decoder so that the decoding process can be performed accordingly.

[0019] Besides the concept of coding unit, the concept of prediction unit (PU) is also introduced in HEVC. Once the splitting of CU hierarchical tree is done, each leaf CU is subject to further split into prediction units (PUs) according to prediction type and PU partition. For temporal prediction, the PU types consist of SKIP, MERGE and INTER modes. For spatial prediction modes, the PU type consists of INTRA mode. For each 2N×2N leaf CU, one partition size is selected. When the PredMode (Prediction Mode) is SKIP or MERGE, the only allowed PartSize (Partition Size) is {2N×2N}. When the PredMode is INTER, the allowed PartSize is selected from the set {2N×2N, 2N×N, N×2N, N×N} as shown in FIG. 2. When the PredMode is INTRA, the allowed PartSize is selected from the set {2N×2N, N×N}. The PU design in the current HEVC development results in some redundancy. For example, redundancy may exist between the configuration of “the PU of the CU with depth=k, Mode=INTER, PartSize=N×N” and the configuration of “the PU of the CU with depth=k+1, Mode=INTER, PartSize=2N×2N” as shown in FIG. 3. The PU 310 at depth k will be processed again at depth (k+1) as the PU 320. The PU 310 is selected under the INTER mode with partition size N×N. On the other hand, the PU 320 is selected at the INTER mode with partition size 2N′×2N′, where 2N′=N. Consequently, the same block will be processed twice at depths k and depth (k+1). The redundancy will cause unnecessary processing and waste valuable system resources.

[0020] In order to eliminate the above redundancy, the allowable partition sizes are constrained according to U.S. Non-Provisional patent application Ser. No. 13/012,811, as shown in FIG. 4. Consequently, for each leaf CU larger than SCU (smallest CU), the partition sizes allowed are 2N×2N, 2N×N and N×2N. In other words, the N×N partition is not allowed for INTER mode if the leaf CU is larger than SCU. If the leaf CU size is the same as SCU size, all partition sizes, 2N×2N, 2N×N, N×2N, and N×N, are allowed. When a CU size is the same as SCU size, the CU is not subject to further split and the inclusion of N×N partition size will not cause redundancy. The partition types according to current HEVC HM3.0 (HEVC Test Model version 3.0) described above are summarized in Table 1. The codeword table associated with various partition types for HEVC HM3.0 is shown in Table 2.

[0021]

TABLE 1
	INTER	INTER	INTRA	INTRA
Partition Types	CU > SCU	CU = SCU	CU > SCU	CU = SCU
2Nx2N	Yes	Yes	Yes	Yes
Nx2N	Yes	Yes	No	No
2NxN	Yes	Yes	No	No
NxN	No	Yes	No	Yes

[0022]

	TABLE 2
	Partition type	CU > SCU	CU == SCU
	INTER 2Nx2N	1	1
	INTER Nx2N	01	01
	INTER 2NxN	001	001
	INTER NxN		0001
	INTRA 2Nx2N	000	00001
	INTRA NxN		00000

[0023] While the method disclosed in U.S. Non-Provisional patent application Ser. No. 13/012,811, uses constrained PU partition to reduce the coding redundancy, the process can be further improved. According to one embodiment of the present invention, the N×N coding mode is removed for INTER coding at all depths. FIG. 5A illustrates allowed INTER and INTRA partitions in various depths according to an embodiment of the present invention. The example shown in FIG. 5A still allows INTRA N×N partition when the CU size equals to the smallest size. Since the codeword table does not need to accommodate an entry for INTER N×N regardless whether CU is larger than SCU or CU has the same size as SCU, the codeword table can be simplified. An exemplary codeword table incorporating an embodiment according to the present invention is shown in Table 3. The codewords for INTRA 2N×2N and INTRA N×N in Table 3 are shorter than the respective codewords in Table 2.

[0024]

	TABLE 3
	Partition type	CU > SCU	CU == SCU
	INTER 2Nx2N	1	1
	INTER Nx2N	01	01
	INTER 2NxN	001	001
	INTRA 2Nx2N	000	0001
	INTRA NxN		0000

[0025] In another embodiment according to the present invention, the system can adaptively eliminate the INTER N×N partition and the selection can be indicated by syntax. For example, the sequence parameter set (SPS) and picture parameter set (PPS) syntax can be modified to allow more coding flexibility. FIG. 5B illustrates allowed INTER and INTRA partitions in various depths where INTER N×N partition is allowed when the CU size equals to the smallest size. Exemplary SPS and PPS syntaxes incorporating an embodiment according to the present invention are shown in FIG. 6 and FIG. 7 respectively. In order to provide more coding flexibility, a flag “disable_inter_4×4_pu_flag” is added in SPS as highlighted in FIG. 6. In addition, a flag “disable_inter_4×4_pu_pic” may be added in PPS as highlighted in FIG. 7 to allow the encoder to selectively enable the INTER N×N when INTER N×N is allowed as indicated by “disable_inter_4×4_pu_flag” in SPS. If “disable_inter_4×4_pu_flag” is 1 in SPS, the INTER N×N (N=4) is disabled for the whole sequence. The “disable_inter_4×4_pu_pic” in PPS will not be sent in this case. Otherwise, the “disable_inter_4×4_pu_pic” in PPS will be sent to determine whether to allow INTER N×N for CU=SCU is disabled for each picture. Therefore, if “disable_inter_4×4_pu_flag” is true, then Table 3 will be used for all Inter frames in the sequence; otherwise, if “disable_inter_4×4_pu_pic” is true, then Table 3 will be used for the current Inter frame, if “disable_inter_4×4_pu_pic” is false, Table 2 will be used. The exemplary syntax design in FIG. 6 and FIG. 7 are for the purpose to illustrate one means to practice the present invention. A skilled person in the field may use other syntax design to practice the present invention without departing from the spirit of the present invention. For example, instead of “disable_inter_4×4_pu_flag”, a flag “enable_inter_4×4_pu_flag”, “inter_4×4_enabled_flag” or any other equivalence in SPS may also be used. Similarly, instead of “disable_inter_4×4_pu_pic”, a flag “enable_inter_4×4_pu_pic”, “inter_4×4_enable_pic”, or any equivalence in PPS may also be used.

[0026] The coding tree semantics associated with the syntax described above are illustrated in FIG. 8 through FIG. 10. FIG. 8 illustrates specification of cu_split_pred_part_mode when CU is greater than SCU, where cu_split_pred_part_mode specifies split_coding_unit_flag and, when the coding unit is not split, the skip_flag, the merge_flag, PredMode and PartMode of a coding unit. FIG. 9 illustrates specification of cu_split_pred_part_mode when CU is equal to SCU. In FIG. 9, INTER N×N is allowed. FIG. 10 illustrates specification of cu_split_pred_part_mode when CU is equal to SCU and INTER N×N is not allowed, i.e., disable_inter_4×4_pu_flag=1 or disable_inter_4×4_pu_pic=1 according to exemplary syntax disclosed above.

[0027] When Asymmetric Motion Partitioning (AMP) is enabled, additional partitions including INTER 2N×nU, INTER 2N×nD, INTER nL×2N and INTER nR×2N, will be used. The codeword tables in Table 2 and Table 3 can be modified to accommodate the additional partitions as shown in Table 4, where the differences from Table 2 and Table 3 are shown in Italic.

[0028]

TABLE 4
		CU == SCU	CU == SCU
Partition type	CU > SCU	inter_4x4 disabled	inter_4x4 enabled
INTER 2Nx2N	1	1	1
INTER 2NxN	011	011	011
INTER 2NxnU	0101	0101	0101
INTER 2NxnD	0100	0100	0100
INTER Nx2N	0011	0011	0011
INTER nLx2N	00101	00101	00101
INTER nRx2N	00100	00100	00100
INTER NxN			0001
INTRA 2Nx2N	000	0001	00001
INTRA NxN		0000	00000

[0029] In U.S. Non-Provisional patent application Ser. No. 13/012,811, filed Jan. 25, 2011, entitled “Apparatus and Method of Constrained Partition Size for High Efficiency Video Coding”, it has been demonstrated that the method based on constrained partition size can noticeably reduce the required computations at the expense of very modest increase in RD-rates. The method incorporating an embodiment according to the present invention further selectively removes INTER N×N partition for all CU sizes to reduce computational complexity. Again, the increase in RD-rates is very modest. In another embodiment according to the present invention, a flag in SPS and/or PPS is used to select whether INTER 4×4 is allowed. If INTER 4×4 is allowed, the coding method for CU/PU partition similar to that of U.S. Non-Provisional patent application Ser. No. 13/012,811 is selected. If INTER 4×4 is not allowed, the method with further reduced computational complexity as disclose herein is used.

[0030] Embodiment of compressing CU partition with INTER 4×4 removed according to the present invention as described above may be implemented in various hardware, software codes, or a combination of both. For example, an embodiment of the present invention can be a circuit integrated into a video compression chip or program codes integrated into video compression software to perform the processing described herein. An embodiment of the present invention may also be program codes to be executed on a Digital Signal Processor (DSP) to perform the processing described herein. The invention may also involve a number of functions to be performed by a computer processor, a digital signal processor, a microprocessor, or field programmable gate array (FPGA). These processors can be configured to perform particular tasks according to the invention, by executing machine-readable software code or firmware code that defines the particular methods embodied by the invention. The software code or firmware codes may be developed in different programming languages and different format or style. The software code may also be compiled for different target platform. However, different code formats, styles and languages of software codes and other means of configuring code to perform the tasks in accordance with the invention will not depart from the spirit and scope of the invention.

[0031] The invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described examples are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope