Multiple layer quantum well FET with a side-gate

[0001] This invention relates to field effect transistors (FETs) that use quantum wells and more specifically to FETs having high linearity when used as a radio frequency (RF) amplifier, especially at microwave and millimeter-wave frequencies.

[0002] Electronic applications operating at microwave and millimeter-wave frequencies and requiring linearity in RF amplification place increasing demands on transistors to provide such amplification. It is a challenge to make transistors with characteristics that will provide RF amplification at ultra high frequencies, e.g. up to 300 GHz, with high linearity. Although high electron mobility transistors (HEMTs) have been utilized, there exists a need for transistors that can provide improved RF linearity performance with reduced DC power consumption while operating at ultra high frequencies.

[0003] It is an object of the present invention to provide an improved FET that satisfies this need.

[0004] An exemplary FET includes a substrate and multiple vertically stacked layer groups with each layer group having a quantum well semiconductive layer and a nonconductive layer adjacent the first quantum well semiconductive layer. Conductive source and drain electrodes in conductive contact with the semiconductive layers. A 3-dimensional ridge of the stacked layer groups is defined between spaced apart first and second trenches which are between the source and drain electrodes. A continuous conductive side gate is disposed on the sides and top of the ridge for inducing a field into the semiconductive layers. A gate electrode is disposed in conductive contact with the conductive side gate. The dimensional relationships, as will be described in more detail, enables the FET to provide improved linearity in the amplification of small RF signals, improved cutoff frequency response, and reduced DC power consumption.

[0015] FIG. 1 shows a representative FET transistor 100 in accordance with an embodiment of the present invention. The transistor 100 employs a heterodimensional field effect in a 3-dimensional side-gate with multiple stacked 2-dimensional charge carrier populations in semiconductor quantum well channels. The RF characteristics of the exemplary transistor can be scaled as a function of channel width, length, number of channels, and number of stacked quantum wells. The transistor provides high RF linearity, i.e. low harmonic distortion. Contributing to the high RF linearity is a linear drain current to gate control voltage relationship provided by the heterodimensional field effect. This translates into a flat transconductance characteristic that produces low RF distortion transistor amplifiers.

[0016] An idealized cross-sectional representation of a ridge 105 shows multiple, vertically stacked, planar layers of semiconducting quantum well layers 110 each separated by corresponding nonconductive (semiconductor barrier) layers 115. A conductive side-gate 120, e.g. made of a metal, engages the sides 125 and 130 and top 135 of the 3-dimensional ridge 105. The width of layers 115 defines the spacing between quantum well channel layers 110. The channel width 107 extends as shown. In a preferred embodiment the ratio of the channel width to the spacing between quantum well layers (channel width/spacing) is less than or equal to 8. In more preferred embodiments, the ratio is less than 4 and greater than 0.3. The quantum well channel layers and nonconductive barrier layers are composed of compound semiconductor materials or alloys of compound semiconductors such that the energy bandgaps of the quantum well channel layers are lower than the bandgaps of the adjoining barrier layers, with the energy band alignment between each quantum well and barrier interface being type 1 or 2. In a preferred embodiment the quantum well channel layer is composed of InGaAs with barrier layers composed of InAlAs, with a type 1 “straddling gap” energy band alignment at each InAlAs and InGaAs interface. The quantum well channels may be modulation-doped by a doping plane or layer within each adjoining barrier layer, or may be piezoelectrically doped in the case of GaN/AlN/InN compound semiconductors in a Wurtzite crystal structure. A preferred embodiment utilizes delta doping planes in InAlAs in order to modulation dope InGaAs quantum well channel layers.

[0017] Each of the semiconductive layers 110 are in low resistance contact, i.e. low resistance contact, at the respective ends of the planar layers to a source electrode or contact 140 and a spaced apart drain electrode or contact 145 of the FET 100. A gate electrode or contact 150 can be disposed at any convenient location in a low resistance connection with the side-gate 120. The layers 110 and 115 are disposed on a nonconductive substrate or base 155. The semiconductive layers 110, i.e. channel layers, are separated by the nonconductive layers 115 to form continuous and parallel quantum well channels connecting the source and drain electrodes.

[0018] FIG. 2 shows an exploded embodiment 101 similar to the corresponding structure shown in FIG. 1 but with an insulating (non-conductive) layer 122 disposed between the side-gate 120 and the ridge 105. Depending on the design objectives and desired characteristics, using an insulated side-gate may be desirable.

[0019] FIG. 3 shows a cross-sectional view of one ridge 205 of exemplary FET 200 in a practical implementation in which semiconductor manufacturing methods, e.g. epitaxial fabrication, deposition, etching, etc., have been used to fabricate the ridge. In this embodiment will be noticed that the sides 225, 230 of the ridge 205 are generally vertical relative to the planar substrate/base 255 but are sloped to form a pyramid shape with the layers of the ridge becoming narrower as the distance to the substrate 255 increases.

[0020] In the exemplary FET 200 three semiconducting quantum well channels 210, 211 and 212 have corresponding channel widths (cw) 1, 2 and 3. Channels 210, 211 and 212 have corresponding insulating layers 215, 216 and 217 having corresponding thicknesses of A1, A2 and A3, respectively. A top insulating layer 214 is disposed between insulating layer 215 and the top portion of the side gate 220. A bottom nonconductive semiconductor buffer layer 218 is disposed between semiconductor layer 212 and the substrate 255. For the exemplary pyramid shaped ridge where the charge density in each of the semiconducting channels is substantially the same, the following relationships are preferred in order to keep turn-ON side gate voltage for each channel layer substantially equal:
cw1/A1<=cw2/A2<=cw3/A3<=8
and for the general case where N number of semiconducting channels are used:
cw1/A1<=cw2/A2<=cw(N−1)/A(N−1)<=cw(N)/A(N)<=8.
The turn-ON side gate voltage for each quantum well semiconductive layer being substantially the same/equal meaning each side gate turn-ON voltage being within 20% of the same voltage. The charge density in each of the quantum well semiconductive layers being substantially the same means the charge density in each being within 20% of a given charge density.

[0021] This slope may be achieved by an etching away fabrication process since the upper layers will have been exposed for etching for a longer time than the lower layers near the substrate 255, assuming the etching starts from the top. It is anticipated that the side-gate 220 will be deposited following the etching process to extend across the ridge and adjacent trenches/valleys. Multiple ridges can be thus form on substrate 255.

[0022] The ridge 205 may be formed by etching away spaced apart portions of the parallel layers resulting in one or more generally parallel ridges or “saddles” remain between the etched away areas (trenches); see FIG. 1. Although FIG. 1 shows only left and right portions of the side gate 120/220, it will be understood that this is only to facilitate a better view of the ridge structure and that the actual structure of the side gate 120/220 extends continuously over and engaging the entirety of the ridge including its top as shown in FIGS. 2 and 3.

[0023] The operation of the FETs 100, 101 and 200 is based on capacitive and lateral coupling to carriers in each channel layer by fields from the side gate. The gate to source voltage applied to the side gate modulates carrier concentration at lateral edges in each channel layer as a function of the magnitude of the gate to source voltage. Since the change in carrier concentration for each channel is substantially the same for a given applied gate voltage, this produces a corresponding linear response of drain to source current for the FET. Each channel may be doped with carriers by any conventional means, e.g. modulation, piezoelectric, electrostatic, etc., and may be doped to different effective concentrations, but all channels should be doped with the same carrier type, i.e. electron or hole.

[0024] FIG. 4 shows a representative cross-sectional view of an exemplary FET transistor 300 which has a plurality of parallel ridges 305 on a substrate 310. Each ridge 305 has a plurality of layers as explained above. A single continuous conductive side gate 315 abuts and traverses across the sides and top of the ridges and adjacent trenches/valleys 317. The ridge has a width 345 and a height 350. The ridge pitch, i.e. dimension of the repetitive spacing of the ridges, is represented by 365.

[0025] FIG. 5 shows an illustrative top view of an exemplary FET transistor 300 having multiple parallel ridges 305. Source contact 320, gate contact 325 and drain contact 330 provide conductive pads for connecting the transistor 300 to other circuitry. A nonconductive top layer 335, and corresponding interleaved semiconductive and nonconductive layers below, extended with uniform width from the source 320 to the drain 330 prior to the etching of the ridges 305. The regions 340 adjacent the conductive side gate 315 as shown in FIG. 5 represent areas (trenches) in which the interleaved layers have been etched away. The width 345 of the ridge and the ridge height 350 define an aspect ratio of the ridges. The width of the side gate is represented by 355 and the source to drain spacing is represented by 360.

[0026] FIG. 6 is a table 600 illustrating representative characteristic parameters for exemplary FET embodiments in accordance with the present invention using different semiconductor materials. Each of columns 602-609 correspond to a different parameter or characteristic identified in row 620 for the respective columns. Rows 621, 622, 623 and 624 in column 601 identify an exemplary FET in accordance with the present invention made with the indicated semiconducting materials. Each of rows 621, 622, 623 and 624 show characteristics/parameters associated with the exemplary FET identified in column 601 of the same row. The listed characteristics/parameters are: 602—bandgap energy; 603—relative dielectric constant; 604—electron saturation velocity; 605—calculated transconductance per quantum well per ridge; 606—Ecrit, defined as the critical electric field for avalanche breakdown; 607—breakdown voltage; 608—calculated power handling; 609—calculated intrinsic high—frequency performance. The four listed semiconductor materials are: 621—Indium Arsenide; 622—Indium Phosphide; 623—Gallium Arsenide; 624—Gallium Nitride. Electron saturated velocity (VSAT) in the semiconductor has an inverse relationship to the bandgap. Generally, higher VSAT enables higher transconductance (GM) per quantum well layer, per ridge. Also, higher channel bandgap enables higher breakdown voltage; increases RF input power handling and survivability; high Imax increases RF linearity. Higher VSAT enables high frequency performance. For these characteristics, the length of the side-gate, LG, (dimension of side-gate from drain to source) is assumed to be 0.2×10⁻⁶ meters. FT, defined as the unity current gain cutoff frequency, has an inverse relationship to carrier transit time across the side-gate dimension LG, and therefore FT has a 1/LG relationship.

[0027] FIG. 7 shows a graph 700 of transconductance per quantum well, per ridge versus gate voltage curves 705, 710 and 715 for three FET embodiments using InP, GaAs and GaN semiconductor materials, respectively. Transconductance (G_M) is determined by:
G_M≈4∈_SV_S

[0028] Where ∈_S is the relative dielectric constant of non-conductive barrier layers around the quantum well channel layers, and Vs is the electron or hole carrier saturation velocity (VSAT). Looking at FIG. 7 it will be seen that parts of each curve show a flat portion (horizontal portion) indicating a corresponding flat Gm region.

[0029] FIG. 8 shows a graph 800 of curves 805, 810 and 815 of frequency response (cutoff frequency in GHz) versus number of channel layers for three FET embodiments using InP, GaAs and GaN semiconductor materials, respectively. All three curves show various degrees of improvement in frequency response as compared to a transistor utilizing only a single channel layer as could be comparable to currently available transistors. For example, considering a comparison of cutoff frequency for an FET using 10 channel layers versus 1 channel using the same semiconductive material: curve 805 shows an improvement of 125 GHz from 65 GHz; curve 810 shows an improvement of 90 GHz from 38 GHz; curve 815 chosen improvement of 35 GHz versus 10 GHz. Even a much lower number of channel layers, e.g. 3, shows a significant improvement in comparison to a single semiconducting channel.

[0030] FIG. 9 shows a graph 900 showing linearity as determined by output third order inter-modulation intercept power versus DC power for FET embodiments in accordance with the present invention and other existing transistors. The dashed straight lines 905, 910 and 915 represent linearity figures of merit of 1, 10 and 100, respectively. Regions 920 represent conventional single conductive channel FET transistors made of the respective materials. Region 925 represents current HEMT Gallium Nitride transistor technology using a single conductive channel with regard to DC power usage and linearity. Region 936 represents an embodiment of an FET in accordance with the present invention using Gallium Nitride showing a capability of a linearity figure of merit of 100 or better and a DC power usage about 10 W/mm. This represents an improvement of approximately 10 times in increased linearity for the same DC power as compared with the HEMT Gallium Nitride transistor, e.g. region 925. Region 930 represents an embodiment of a FET in accordance with the present invention using Gallium Arsenide showing a capability of a linearity figure of merit of 100 or better and a DC power usage somewhat above 1 W/mm. This represents an improvement of approximately 10 times in linearity for the same DC power as compared with the HEMT Gallium Arsenide transistor, e.g. region 926. Region 937 represents an embodiment of a FET in accordance with the present invention using Indium Phosphide showing a capability of a linearity figure of merit of 100 or better and a DC power usage less than 1 W/mm. This represents an improvement of approximately 10 times in linearity for the same DC power compared with the HEMT Indium Phosphide transistor, e.g. region 927.

[0031] One exemplary method of making an FET in accordance with the present invention is to grow sequential adjacent layers on a substrate in a known epitaxial technique. The trench/valley regions can then be etched away and the side gate then deposited over the exposed ridge structure. Metallic contact pads for the source, drain and side gate can be deposited to enable connections to be made with the FET. Of course, other techniques could be used as long as the objective final structure results.

[0032] Although exemplary implementations of the invention have been depicted and described in detail herein, it will be apparent to those skilled in the art that various modifications, additions, substitutions, and the like can be made without departing from the spirit of the invention.

[0033] The scope of the invention is defined in the following claims.