Nonvolatile memory device, storage device including the nonvolatile memory device, and operating method of the storage device

[0001] This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2014-0057311, filed on May 13, 2014 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

[0002] The present inventive concept relates to a nonvolatile memory device, a storage devices including the same and, an operating method of the storage device.

[0003] Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted. Volatile memory devices include a dynamic random access memory (DRAM) and a static RAM (SRAM). Nonvolatile memory devices retain their stored data after their power supplies are interrupted. Nonvolatile memory devices include a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), a phase change RAM (PRAM), a restive RAM (REAM), and a flash memory.

[0004] Nonvolatile memory devices have been developed to have three-dimensional structures for increased integration density. Three-dimensional nonvolatile memory devices exhibit faster write speed, extended cell lifetime, and increased power efficiency. A three-dimensional nonvolatile memory device and a conventional two-dimensional nonvolatile memory device are structurally different from each other. Due to the structural difference between the three-dimensional and two-dimensional nonvolatile memory devices, various methods for driving three-dimensional nonvolatile memory devices have been studied.

[0005] According to an exemplary embodiment of the present inventive concept, a storage device includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes a plurality of blocks. The memory controller is configured to detect, upon receiving a power-on signal, a partial block among the plurality of blocks. The partial block includes a first page incompletely programmed due to sudden power-off occurred to the storage device. The memory controller determines whether or not to perform a dummy program operation on the partial block, and programs a second page of the partial bock with dummy data. The first page is different from the second page.

[0006] According to an exemplary embodiment of the present inventive concept, an operating method of a storage device is provided. The storage device includes a nonvolatile memory device including a plurality of blocks and a memory controller configured to control the nonvolatile memory device. A partial block is detected. The partial block includes a first page incompletely programmed due to sudden power-off occurred to the storage device. A dummy program operation is performed on a second page of the partial block by using dummy data. The first page is different from the second page.

[0007] According to an exemplary embodiment of the present inventive concept, an operating method of a storage device is provided. Whether a nonvolatile memory includes a partial block is detected. The partial block includes a first page incompletely programmed due to sudden power-off occurred to the storage device. A dummy program operation is performed on a second page of the partial block using dummy data. The second page is disposed between the first page and a string selection transistor of the nonvolatile memory. A copyback operation is performed to move valid data of the partial block to another block different from the partial block.

[0031] Exemplary embodiments of the inventive concept will be described below in detail with reference to the accompanying drawings. However, the inventive concept may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the thickness of layers and regions may be exaggerated for clarity. It will also be understood that when an element is referred to as being “on” another element or substrate, it may be directly on the other element or substrate, or intervening layers may also be present. It will also be understood that when an element is referred to as being “coupled to” or “connected to” another element, it may be directly coupled to or connected to the other element, or intervening elements may also be present. Like reference numerals may refer to the like elements throughout the specification and drawings.

[0032] FIG. 1 is a block diagram of a storage device 100 according to an exemplary embodiment of the inventive concept. The storage device 100 includes a nonvolatile memory device 110 and a memory controller 120.

[0033] The nonvolatile memory device 110 includes a meta area 111 to store management information for managing the nonvolatile memory device 110 and a user data area 112 to store user data. The user data area 112 includes a plurality of memory blocks BLK1 to BLKz. The number of z is an integer equal to or greater than 2. Each of the memory blocks BLK1 to BLKz includes a plurality of pages Page 1 to Page n. The number of a is an integer equal to or greater than 2.

[0034] The meta area 111 may include at least one memory block having the same structure as each of the memory blocks BLK1 to BLKz in the user data area 112. The meta area 111 may store information on whether pages included in at least one memory block are completely programmed. The meta area 111 may also include power supply information. For example, the power supply information may include information of normal power-off, hereinafter referred to as “NPO” and sudden power off, hereinafter referred to as “SPO”.

[0035] If the nonvolatile memory device 110 is powered off after a page completely is programmed, the power supply information may indicate to NPO. Otherwise, the power supply information may indicate to SPO.

[0036] In the nonvolatile memory device 100, if a program operation of a block is stopped due to power-off before completed, the block is called a partial block. The partial block may refer to a block in which at least one page is not completely programmed due to SPO.

[0037] The memory controller 120 may determine based on the power supply information whether a block is a partial block, and may perform a dummy program operation on at least one page of the partial block. The memory controller 120 may include a partial block program determinator 121 and a dummy data generator 122.

[0038] The partial block program determinator 121 may receive the power supply information from the meta area 111 of the nonvolatile memory device 110. If the partial block program determinator 121 detects SPO based on the power supply information, the dummy data generator 122 generates dummy data in response to a determination result of the partial block program determinator 121. The memory controller 120 may perform a dummy program operation on the partial block of the nonvolatile memory device 110 using the dummy data.

[0039] The dummy data may be random data, and may be programmed in at least one upper page which may be disposed above a page which is incompletely programmed.

[0040] The at least one page may be a clean page or a dummy page. The clean page may refer to a page in an erased state. In an exemplary embodiment, a dummy program operation of a partial block may be performed if a partial block occurs as shown in FIG. 17. In an exemplary embodiment, a dummy program operation of a partial block may be performed depending on whether a copyback operation for a partial block is completed as shown in FIG. 19. The descriptions of FIGS. 17 and 19 will be made later.

[0041] FIG. 2 is a block diagram of a storage device 200 according to an exemplary embodiment of the inventive concept. Referring to FIG. 2, the storage device 200 includes a nonvolatile memory device 210 and a memory controller 220.

[0042] The memory controller 220 may include a partial block program determinator 221 and a dummy data generator 222. The memory controller 200 may program at least one upper page of the partial block with dummy data to increase power efficiency during a command of a host or a program operation.

[0043] FIG. 3 is a block diagram of a nonvolatile memory device 300 according to an exemplary embodiment of the inventive concept. The nonvolatile memory device 300 includes a memory cell array 310, an address decoder 320, a read and write circuit 330, and a control logic and voltage generator 340. The nonvolatile memory device 300 corresponds to the nonvolatile memory devices 110 and 210 in FIGS. 1 and 2.

[0044] The memory cell array 310 is connected to the address decoder 320 through a plurality of string select lines SSL, wordlines WL, and ground select lines GSL. The memory cell array 310 is connected to the read and write circuit 330 through a plurality of bitlines BL. The memory cell array 310 includes a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz may include a plurality of memory cells and a plurality of select transistors. The memory cells may be stacked on a substrate to constitute a three-dimensional structure. Each of the memory cells may store a single bit or multiple bits.

[0045] The address decoder 320 is connected to the memory cell array 310 through a plurality of string select lines SSL, wordlines WL, and ground select lines GSL. The address decoder 320 operates in response to a control signal of the control logic and voltage generator 340. The address decoder 320 externally receives an address ADDR.

[0046] The address decoder 320 may decode the received address ADDR. The address decoder 320 may control a voltage applied to wordlines WL according to the decoded address. For example, during a program operation, the address decoder 320 may apply a pass voltage to the wordlines WL according to the control of the control logic and voltage generator 340. During the program operation, the address decoder 320 may further apply a voltage to at least one wordline selected by a decoded address among the wordlines WL according to the control of the control logic and voltage generator 340.

[0047] The read and write circuit 330 is connected to the memory cell array 310 through a plurality of bitlines BL. The read and write circuit 330 may exchange data DATA with an external entity. The read and write circuit 330 operates in response to the control of the control logic and voltage generator 340. The read and write circuit 330 receives a decoded column address DCA from the address decoder 320.

[0048] The read and write circuit 330 may select bitlines BL using the decoded column address DCA. During a program operation, the read and write circuit 330 externally receives data DATA. The read and write circuit 330 applies the received data DATA to the memory cell array 310 through the plurality of bitlines BL. During a read operation, the read and write circuit 320 reads data DATA from the memory cell array 310. The read and write circuit 330 transmits the read data DATA to an external entity.

[0049] In an exemplary embodiment, the read and write circuit 330 may include a page buffer, a column select circuit, and the like. In an exemplary embodiment, the read and write circuit 330 may include a Sense amplifier, a write driver, a column select circuit, and the like.

[0050] The control logic and voltage generator 340 is connected to the address decoder 320 and the read and write circuit 330. The control logic and voltage generator 340 operates in response to a control signal CTRL and a command CMD that are externally applied. The control logic and voltage generator 340 may decode the received command CMD and control the overall operation of the nonvolatile memory device 300 according to the decoded command CMD. The control logic and voltage generator 340 may generate various control signals and voltages according to the received control signal CTRL.

[0051] FIG. 4 is a circuit diagram of the memory cell array 310 in FIG. 3. Referring to FIG. 4, the memory cell array 310 includes a plurality of memory blocks BLK1 to BLKz. For brevity of description, the first memory block BLK1 will be described. Each of the second to z memory blocks BLK2 to BLKz may have the same configuration as the first memory block BLK1.

[0052] The first memory block BLK1 is connected to a plurality of bitlines BL1 to BLp (p being an integer equal to or greater than 2). The first memory block BLK1 is connected to a plurality of string lines SSL1 to SSLq (q being an integer equal to or greater than 2), first to sixth wordlines WL1 to WL6, a dummy wordline DWL, a ground select line GSL, and a common source line CSL.

[0053] A single string line SSL1 is connected to a gate of the string select transistor SST. A string transistor SST is coupled between a single bitline and a sixth memory cell MC6.

[0054] First to sixth memory cells MC1 to MC6 are connected in series and coupled between the string select transistor SST and a dummy memory cell DMC. Gate terminals of the first to sixth memory cells MC1 to MC6 are connected to first to sixth wordlines WL1 to WL6, respectively. The present inventive concept is not limited to the first to sixth memory cells MC1 to MC6, and the number of memory cells may be less than six or greater than six.

[0055] The dummy memory cell DMC is coupled between the first memory cell MC1 and the ground select transistor GST. A gate terminal of the dummy memory cell is connected to a dummy wordline DWL. The ground select transistor GST is coupled between the dummy memory cell DMC and the common source line CSL. A gate of the ground select transistor GST is connected to the ground select line GSL.

[0056] The ground select transistor GST, the dummy memory cell DMC, the first to sixth memory cells MC1 to MC6, and the string select transistor SST coupled between the single bitline BL1 and the common source line CSL constitute a first string 311. A plurality of strings are connected to each of the bitlines BL1 to BLp. Each of the strings has the same configuration as the first string 311.

[0057] For brevity of description, a single dummy memory cell was described. The inventive concept is not limited thereto, and one or more dummy memory cells may be connected to the first memory cell MC1.

[0058] FIG. 5 is a perspective view showing a portion BLK1a of the first memory block BLK1 in FIG. 4, and FIG. 6 is a cross-sectional view taken along line V-V′ in FIG. 5. Referring to FIGS. 5 and 6, the portion BLK1a of the first memory block BLK1 includes structures extending in first to third directions.

[0059] A substrate 411 is provided. The substrate 411 may be a well having a first type. For example, the substrate 411 may include a silicon material doped with p-type impurities. For example, the substrate 411 may be a p-type well (e.g., p-type pocket well). Hereinafter, the substrate 411 is assumed to be a p-type well (or p-type pocket well). However, the substrate 411 is not limited to the p-type silicon substrate.

[0060] A plurality of doped regions 611-614 extending in the first direction are provided on the substrate 411. For example, the doped regions 611-614 may have a second type different from that of the substrate 411. For example, the doped regions 611-614 may have an n-type. Hereinafter, let it be assumed that the doped regions 611-614 may have n-type impurities. However, the conductivity type of the doped regions 611-614 is not limited to the n-type.

[0061] On a region of the substrate 411 between the first and second doped regions 611 and 612, a plurality of insulating materials 412 extending in the first direction is sequentially provided in the second direction. For example, the insulating materials 412 are provided in the second direction to be spaced apart from each other at specific intervals. The insulating materials 412 may include an insulating material such as silicon oxide.

[0062] On the region of the substrate 411 between the first and second doped regions 611 and 612, a plurality of pillars 413 is provided which are sequentially disposed in the first direction and penetrate the insulating materials 412. In an exemplary embodiment, the pillars 413 may be in contact with the substrate 411 through the insulating materials 412.

[0063] In an exemplary embodiment, each of the pillars 413 may include a plurality of layers 414 and 415. For example, the surface layer 414 of each of the pillars 413 may include a silicon material having a first impurity type. For example, the surface layer 414 of each of the pillars 413 may include a silicon material having the same type as the substrate 411. Hereinafter, it is assumed that the surface layer 411 of each of the pillars 413 includes p-type silicon. However, the surface 414 of each of the pillars 413 is not limited to the p-type.

[0064] The inner layer 415 of each of the pillars 413 may include an insulating material. For example, the inner layer 415 of each of the pillars 413 may include an insulating material such as silicon oxide. For example, the inner layer 115 of each of the pillars 113 may include an air gap.

[0065] In the region between the first and second doped regions 611 and 612, an insulating layer 416 is provided along exposed surfaces of the insulating materials 412, the pillars 413, and the substrate 411. The insulating layer 416 is not disposed on an upper surface of the uppermost insulating material 412 in the second direction.

[0066] In the region between the first and second doped regions 611 and 612, first conductive materials 511-591 are provided on an exposed surface of the insulating layer 416. For example, a first conductive material 511 extending in the first direction is provided between the substrate 411 and the insulating material 412 adjacent to the substrate 411. For example, the first conductive material 511 extending in the first direction is provided between the first conductive material 511 and the insulating layer 416 on a bottom surface of the insulating material 412 adjacent to the substrate 411.

[0067] Each of the first conductive materials extending in the first direction is provided between a top surface of the insulating layer 416 and a bottom surface of the insulating layer 416. The insulating layer 416 is extended in a sinuous way along the second directions, having multiple top surfaces and bottom surfaces. In an exemplary embodiment, a plurality of first conductive materials 521-581 extending in the first direction is provided between the insulating materials 412. In an exemplary embodiment, the first conductive materials 511-591 may include metal materials. In an exemplary embodiment, the first conductive materials 511-591 may include a conductive material such as polysilicon.

[0068] The same structure as that on the first and second doped regions 611 and 612 may be provided in a region between the second and third doped regions 612 and 613. In an exemplary embodiment, a plurality of insulating materials 412 extending in the first direction, a plurality of pillars 413 sequentially disposed in the first direction and penetrating the insulating materials 412 in the third direction, an insulating layer 416 provided on exposed surfaces of the insulating materials 412 and the pillars 413, and a plurality of first conductive materials 512-592 extending in the first direction are provided in the region between the second and third doped regions 612 and 613.

[0069] The same structure as that on the first and second doped regions 611 and 612 may be provided in a region between the third and fourth doped regions 613 and 614. In an exemplary embodiment, a plurality of insulating materials 412 extending in the first direction, a plurality of pillars 413 sequentially disposed in the first direction and penetrating the insulating materials 412 in the second direction, an insulating layer 416 provided on exposed surfaces of the insulating materials 412 and the pillars 413, and a plurality of first conductive materials 513-593 extending in the first direction are provided in the region between the third and fourth doped regions 613 and 614.

[0070] Drains 620 are provided on the pillars 413, respectively. In an exemplary embodiment, the drains 620 may include silicon materials doped with second-type impurities. For example, the drains 620 may include silicon materials doped with n-type impurities. However, the drains 620 are not limited to the n-type.

[0071] In an exemplary embodiment, width of each of the drains 620 may be greater than that of a corresponding pillar 413. For example, each of the drains 620 may be provided on a top surface of a corresponding pillar 412 in the form of a pad. In an exemplary embodiment, each of the drains 620 may extend to a portion of a corresponding surface layer 414.

[0072] Conductive materials 631-633 extending in a third direction are provided on the drains 620. The conductive materials 631-633 are arranged in the first direction to be spaced apart from each other at specific intervals. The conductive materials 631 to 633 are connected to the drains 620 in a corresponding region, respectively, in an exemplary embodiment, the drains 620 and the conductive material 633 extending in the third direction are connected through contact plugs, respectively. In an exemplary embodiment, the conductive materials 631-633 may include metal materials. The conductive materials 631-633 may include a conductive material such as polysilicon.

[0073] FIG. 7 is a circuit diagram illustrating a program operation of a storage device according to an exemplary embodiment of the inventive concept. Referring to FIG. 7, a memory block BLK includes a plurality of strings connected to a plurality of bitlines BL1 to BLr (r being an integer equal to or greater than 2). Each of the strings may include at least one string select transistor SST, a plurality of dummy memory cells DMC1 to DMC4, a plurality of memory cells MC1 to MCm (m being an integer equal to or greater than 2), and at least one ground select transistor GST. Each of the memory cells MC1 to MCm may store one or more bits of data.

[0074] For brevity of description, it is assumed that a single string includes four dummy memory cells DMC1 to DMC4.

[0075] A plurality of memory cells may be connected to each of a plurality of wordlines WL1 to WLm. The memory cells connected to each of the wordlines WL1 to WLm may be referred to as a page. Each of the wordlines WL1 to WLm may be applied with wordline voltages required for various operations. The wordline voltages include a program voltage, a pass voltage, a read voltage, and a read pass voltage.

[0076] At least one string select transistor SST may be connected to a string select line SSL. The string select line SSL may be applied with a string select voltage for controlling the at least one string select transistor SST. At least one ground select transistor GST may be connected to a ground select line GSL. The ground select line GSL may be applied with a ground select voltage for controlling the at least one ground select transistor GST.

[0077] It is assumed that SPO occurs in the memory block BLK while a page connected to a third wordline WL3 is programmed. When the SPO occurs, a dummy data program operation may be performed on a page connected to an uppermost wordline WLm. For example, dummy data may be programmed into the page connected to the uppermost wordline WLm. Leakage current of the memory block BLK may be prevented through the dummy data program operation of the page connected to the uppermost wordline WLm.

[0078] When SPO occurs, a memory block that is being programmed is not used any longer. The program operation stopped due to SPO is performed on a new memory block. After the new memory block is programmed, a bitline voltage is applied to a plurality of bitlines to verify the program operation. The bitline voltage applied to the partial block may be blocked by a plurality of string select transistors connected to a string select line. However, coupling may occur between a common source line and the string select line of the partial block.

[0079] Such coupling may cause the string select transistors connected to the string select line to form a leakage current path through a partial block. For example, the string select transistors do not fully block the bitline voltage from flowing through a plurality of bitlines through a partial block. Thus, a large amount of leakage current may flow through each string in the partial block.

[0080] The large amount of leakage current of the partial block may cause an inaccurate program verify operation of the new memory block. In an exemplary embodiment, at least one upper page of a partial block is programmed to prevent leakage current flowing abnormally flowing through the partial block.

[0081] For example, dummy data may be programmed into a page connected to at least one wordline disposed above a page which is incompletely programmed. In addition, the dummy data may be programmed into a page connected to at least one dummy wordline disposed above an uppermost wordline.

[0082] The page programmed with dummy data is not limited to the page connected to the uppermost wordline WLm. A page connected to at least one wordline disposed at a lower position than the uppermost wordline WLm may be programmed. The page programmed with the dummy data is not limited to a page connected to a wordline. For example, a dummy page connected a dummy wordline may be programmed with dummy data.

[0083] FIG. 8 is a circuit diagram illustrating a program operation of a storage device according to an exemplary embodiment of the inventive concept. Referring to FIG. 8, a memory block BLK includes a plurality of strings. Each of the strings may include at least one string select transistor SST, a plurality of dummy memory cells DMC1 to DMC4, a plurality of memory cells MC1 to MCm, and at least one ground select transistors GST. Each of the memory cells MC1 to MCm may store one or more bits of data. For brevity of description, it is assumed that a single string includes four dummy memory cells DMC1 to DMC4.

[0084] The page connected to a third dummy wordlines DWL3 may be programmed with dummy data when SPO occurs when a page connected to a third wordline WL3 is being programmed.

[0085] After a dummy program operation is performed on the page of DWL3, the program operation interrupted due to SPO is performed on a new block. A bitline voltage is applied to a plurality of bitlines to perform a program verify operation of the new block. At this point, leakage current that may be applied through the bitlines may be prevented by performing the dummy program operation of the page connected to third dummy wordline DWL3.

[0086] For brevity of description, it is assumed that a page of the third wordline WL3 is incompletely programmed due to SPO. A page programmed to prevent leakage current is not limited to the page of the third dummy wordline DWL3. When the SPO occurs, dummy pages connected to dummy wordlines between at least one string select line SSL and an uppermost wordline WLm may be subjected to a dummy program operation.

[0087] FIG. 9 is a block diagram illustrating a program operation of a storage device according to an exemplary embodiment of the inventive concept. A memory block includes a plurality of dummy wordlines DWL1 to DWL4 and a plurality of wordlines WL1 to WL23.

[0088] For brevity of description, it is assumed that a data program method of a nonvolatile memory device according to the inventive concept is a multi-level cell (MLC) technique. The MLC technique may store two-bit information in a single cell of a memory block. Thus, each memory cell may be programmed with data indicating a plurality of program states E to P3.

[0089] For brevity of description, it is assumed that a plurality of cells included in each page is programmed with data of the same program state.

[0090] For example, pages connected to first and second wordlines WL1 and WL2 are programmed with data indicating first and second program states P1 and P2, respectively. SPO occurs in a page connected to a third wordline WL3 while the page is programmed with data indicating a third program state P3. Pages connected to fourth to twenty third wordlines WL4 to WL23 are in an erase state. Thus, the block shown in FIG. 9 is a partial block.

[0091] SPO may occur in the page connected to the third wordline WL3 during a shadow program operation. SPO may occur in the page connected to the third wordline WL3 during a reprogram operation.

[0092] After the SPO occurs, a dummy program operation is performed on a page of the uppermost wordline WL23 with dummy data indicating the uppermost program state P3. Pages connected to fourth to twenty second wordlines WL4 to WL22 remain in the erase state E.

[0093] After the page of the uppermost wordline WL23 is programmed, the program operation interrupted due to SPO is performed on a new block. When a bitline voltage is applied through a plurality of bitlines to perform a program verify operation on the new block, leakage current through the partial block may be prevented by the dummy program operation. The inventive concept is not limited thereto, and a dummy program operation may be performed on a page disposed above a page which is subject to SPO.

[0094] Before a new program operation is performed on the partial block, data included in all pages are erased.

[0095] FIG. 10 is a block diagram illustrating a program operation of a storage device according to an exemplary embodiment of the inventive concept. In this case, SPO occurs when a page of the third wordline WL3 is being programmed with data indicating the third program state P3.

[0096] A page of the third dummy wordline DWL3 is programmed with dummy data indicating the third program state P3. Pages of fourth to twenty third wordlines WL4 to WL23 remain in an erase state E. The program of the third dummy wordline DWL3 is performed to prevent leakage current that may occur in the partial block during a program verify operation of a new block.

[0097] A page programmed to prevent leakage current is not limited to the page of the third dummy wordline DWL3.

[0098] Before a new program operation is performed on the partial block, data included in all pages are erased.

[0099] Referring to FIGS. 9 and 10, SPO may occur when a program operation is being performed on a wordline different from the third wordline WL3. A program operation performed on each of the pages connected to the wordlines WL1 to WL3 is not limited to data indicating first to third program states P1 to P3. A page connected to each wordline may be programmed with data indicating various program states.

[0100] Referring to FIGS. 9 and 10, the dummy program operation is performed using the third programmed state P3 having the highest threshold voltage range among threshold voltage ranges representing the three programmed states P1 to P3. Since at least on dummy wordline or wordline disposed above a page which is incompletely programmed due to SPO is programmed using the program state P3 having the highest threshold voltage, a leakage path is prevented if a string selection transistor SST of a partial block is coupled. The erased state corresponds to the lowest threshold voltage. The greater threshold voltage is, the less the leakage current is.

[0101] The page on which the dummy program operation is performed is disposed between a string selection transistor SST and a page where a program operation is interrupted due to SPO.

[0102] For brevity of description, four dummy wordlines DWL1 to DWL4 and twenty three wordlines WL1 to WL23 are shown in FIGS. 9 and 10.

[0103] Dummy data used to prevent leakage current is not limited to the data indicating the third program state P3. The dummy data is random data. The dummy data may be randomly selected from data indicating the program states P1 to P3.

[0104] FIG. 11 is a block diagram illustrating a data recovery operation according to an exemplary embodiment of the inventive concept. Referring to FIG. 11, it is assumed that an incomplete program page is formed in a partial block BLKa by SPO. The incomplete program page means a page including incompletely programmed data due to SPO.

[0105] There are at least one complete program page and at least one dummy page below an incomplete program page. The complete program page may refer to a page which is completely programmed. There are a plurality of clean page and at least one dummy page above the incomplete program page. The clean page may refer to a page having an erase state. The memory cells in the clean page have the lowest threshold voltage range. In an exemplary embodiment, SPO may occur in the incomplete program page during a shadow program operation, an exemplary embodiment, SPO may occur in the incomplete program page during a reprogram operation of data.

[0106] First data Data1 and second data Data2 are normally programmed into complete program pages, while an incomplete program page includes third data Data3 that is incompletely programmed data.

[0107] Following occurrence of SPO, a program operation is not performed in the partial block BLKa any longer. The data Data1 to Data3 programmed into the partial block BLKa are copied back to a new memory block BLKb to recover data of the partial block BLKa.

[0108] The copyback operation is performed only when the data stored in the partial block BLKa is valid data. If another SPO does not occur in the new memory block BLKb, a program operation of new data is performed on the clean page of the new memory block BLKb.

[0109] Following the copyback operation, an operation is performed to erase all the data included in the partial block BLKa.

[0110] The uppermost clean page of the partial block BLKa is dummy-programmed to prevent leakage current through the partial block BLKa. After the partial block BLKa is additionally programmed with dummy data, the new block BLKb copies back the valid data of the partial block BLKa. A page programmed with the dummy data is not limited to the uppermost clean page.

[0111] FIG. 12 is a block diagram illustrating a program operation of a storage device according to an exemplary embodiment of the inventive concept. When SPO occurs, a dummy data program operation may be performed on the uppermost clean page and a clean page below the uppermost clean page. The inventive concept is not limited thereto. The dummy data program operation may also be performed on a plurality of clean pages below the uppermost clean page.

[0112] FIG. 13 is a block diagram illustrating a program operation of a storage device according to an exemplary embodiment of the inventive concept. Referring to FIG. 13, a dummy data program operation may be performed on a dummy page disposed above the uppermost clean page of a partial hock BLKa.

[0113] FIG. 14 is a block diagram illustrating a program operation of a storage device according to an exemplary embodiment of the inventive concept. Referring to FIG. 14, a dummy data program operation may be performed on a plurality of dummy pages disposed above the uppermost clean page of a partial block BLKa.

[0114] FIG. 15 is a block diagram illustrating a program operation of a storage device according to an exemplary embodiment of the inventive concept. Referring to FIG. 15, a dummy program operation may be performed on the uppermost clean page of a partial block BLKa and a dummy page disposed above the uppermost page of the partial block BLKa. The inventive concept is not limited thereto. The dummy data program operation may be performed on a plurality of clean pages and a plurality of dummy pages of the partial block BLKa.

[0115] Referring to FIGS. 12 to 15, a dummy data program operation may be performed on at least one clean page disposed above an incomplete program page or at least one dummy page. In addition, the dummy data program operation may be performed on at least one clean page and at least one dummy page disposed above an incomplete program page. For example, the at least one clean page and/or at least one dummy page on which a dummy program operation using dummy data having the highest threshold range is disposed between a string selection transistor and a page where SPO occurs.

[0116] During a shadow program operation of data, SPO may occur in the incomplete program pages in FIGS. 12 to 15. During a reprogram operation of data, SPO may occur in an incomplete program page according to the inventive concept.

[0117] Similar to FIG. 11, referring to FIGS. 12 to 15, a recovery operation is performed on anew block to recover valid data of a partial block BLKa. An additional dummy data program operation of the new block may be performed to prevent leakage current generated by a bitline voltage from flowing through the partial block BLKa during a program verify operation of the new block.

[0118] Referring to FIGS. 11 to 15, a page including incompletely programmed data is not limited to a page including third data Data3. SPO may occur during a program operation of more pages. SPO may occur during a program operation of less pages.

[0119] FIG. 16 is a block diagram illustrating a data recovery operation according to an exemplary embodiment of the inventive concept. Referring to FIG. 16, complete program pages include first data Data1 to sixth data Data6 that are completely programmed. An incomplete program page includes k^th data Data k that is incompletely programmed.

[0120] In FIG. 16, it is assumed that a program operation is not performed on an upper page of a partial block BLKa. The partial block program determinators 121 and 221 in the memory controllers 120 and 220 in FIGS. 1 and 2 may determine whether the program operation is performed on the upper page of the partial block BLKa.

[0121] In an exemplary embodiment, the partial block program determinators 121 and 221 may determine whether or not need to program an upper page of the partial block BLKa. For example, the partial block program determinators 121 and 221 may determine whether or not need to program an upper page in a partial block BLKa, depending on whether a program verify operation of a new block BLKb is normally completed. If the program verify operation of the new block BLKb is normally completed, the programming of the upper page in the partial block BLKa is not necessary. Otherwise, the programming of the upper page in the partial block BLKa is necessary. After the program operation of the partial block BLKa is stopped, a plurality of data Data1 to Data k (k being an integer equal to or greater than 2) of the partial block BLKa are copied back to the new block BLKb. It is assumed that the data Data1 to Data k are valid data.

[0122] After each valid data is programmed into the new block BLKb, program verify operation is performed. If the program verify operation is normally completed, the upper page of the partial block BLKa need not be programmed.

[0123] In an exemplary embodiment, the partial block program determinators 121 and 221 may determine whether or not need to program an upper page according to the number of programmed pages of the partial block BLKa.

[0124] An upper page means at least one clean page or a dummy page disposed above an incomplete program page. If SPO does not occur during a program operation of the new block BLKb, the new block BLKb may be programmed ahead of clean pages disposed above the complete program page.

[0125] FIG. 16 illustrates a copyback operation to copy back valid data of a partial block BLKa into anew block BLKb. The partial block program determinators 121 and 221 of FIGS. 1 and 2 determine whether or not need to program the partial block BLKa. In some embodiments, an upper page need not be programmed even when SPO occurs during a program operation of less data than first to k^th data Data 1 to Data k.

[0126] FIG. 17 is a flowchart illustrating a programming method of a storage device according to an exemplary embodiment of the inventive concept. The programming method will now be described below with reference to FIGS. 9 to 15 and FIG. 17.

[0127] After power is on, whether SPO occurred in a program operation before the power is on is determined (S110). If SPO is detected, a partial block including an incomplete program page (S110) is located. The incomplete program page means a page including incompletely programmed data.

[0128] After the incomplete program page is detected, a dummy data program operation is performed on at least one upper clean page of the partial block or at least one dummy page disposed above the uppermost clean page of the partial block (S120). The partial block is a block including a page where a program operation is not completed. The at least one upper clean page is disposed above an incomplete program page. A dummy data program operation may be performed on the at least one upper clean page and the dummy page at the same time. In this case, the dummy data is random data.

[0129] Valid data programmed into the partial block is copied back to a new block (S130). The copyback operation is an operation to move the valid data of the partial block to the new block. If another SPO does not occur in the new block, a program operation continues to perform on the new block.

[0130] If another SPO occurs in the new block, the programming method in FIG. 17 restarts in a new block.

[0131] The inventive concept is not limited thereto. For example, the step S130 for a copyback operation is performed before the step S120 for a dummy program operation.

[0132] FIG. 18 is a flowchart for performing a programming method of a storage device according to an exemplary embodiment of the inventive concept. The programming method will now be described with reference to FIGS. 16 and 18.

[0133] Power is on (S210). Whether SPO occurred in a program operation is determined (S210). If no SPO detected, the operation proceeds to step S220. Otherwise, the operation proceeds to a normal program operation.

[0134] After the incomplete program page is detected, whether or not need to program an upper page of the partial block is determined (S220). The partial block means a block including a page which is incompletely programmed due to the SPO. The upper page program determinators 121 and 221 in FIGS. 1 and 2 determine whether or not need to program the upper page of the partial block.

[0135] When the upper page needs to be programmed, a dummy data program operation is performed on at least one upper clean page or a dummy page (S230). The at least one upper page is at least one clean page disposed above the incomplete program page. The dummy page may be disposed above the uppermost clean page.

[0136] After the dummy program operation is performed on the at least one clean page or the dummy page, valid data programmed into the partial block is copied back to a new block (S240). When a dummy program operation need not to be performed on an upper page of the incomplete program page, the operation proceeds to step S240 where the programmed valid data is copied back to a new block. When another SPO occurs in the new block, a program procedure described in FIG. 18 restarts in the new block.

[0137] The inventive concept is not limited thereto. For example, step S240 for a copyback operation is performed before step S230 for a dummy program operation if it is determined that a dummy operation is necessary in step S220.

[0138] FIG. 19 is a flowchart for performing a programming method of a storage device according to an exemplary embodiment of the inventive concept. The programming method will now be described with reference to FIG. 19.

[0139] Data is copied back to a new block (S310). The data is valid data programmed into a partial block. The partial block is a memory block that is incompletely programmed due to SPO. After the SPO occurs, the partial block is not used any longer and the programmed valid data is copied to a new block.

[0140] After the data is copied back to the new block, a program verify operation is performed and whether the program verify operation is normally completed is determined (S320). A bitline voltage is applied to a plurality of bitlines to verify the program. Leakage current may be generated through the partial block. Excessive leakage current may flow through the partial block due to coupling between a common source line and a string select line of the partial block.

[0141] When the program verify operation of the new block is not normally completed due to the excessive leakage current, a dummy program operation is performed on the partial block (S330). A dummy data program operation is performed on at least one clean page disposed above an incomplete program page or at least one dummy page. The incomplete program page is a page in which data is not completely programmed in the partial block due to the SPO.

[0142] After the dummy program operation is performed on the partial block, the program verify operation is re-performed on the new block (S340). When the program verify operation of the new block is normally completed, the program operation interrupted due to the SPO is completed. Another program operation is performed (S350).

[0143] FIG. 20 illustrates a solid state drive (SSD) 1000 according to an exemplary embodiment of the inventive concept. As illustrated, the SSD 1000 includes a nonvolatile memory device 1100 including a plurality of nonvolatile memories and a controller 1200. The nonvolatile memory device 1100 may receive a high voltage Vpp.

[0144] The controller 1200 is connected to the nonvolatile memory device 1100 through a plurality of channels CH1 to CHi (i being an integer equal to or greater than 2). The controller 1200 includes at least one processor 1210, a buffer memory 1220, an error correction code (ECC) circuit 1230, a dummy data generator 1240, a host interface 1250, and a nonvolatile memory interface 1260. The controller 1200 determines whether upper page program is necessary to be performed on at least one memory block.

[0145] The buffer memory 1220 may temporarily store data required to drive the memory controller 1200. The buffer memory 1220 may store an error rate table (ERT) depending on operation conditions. In an exemplary embodiment, the buffer memory 1220 may include a plurality of memory lines to store data or a command.

[0146] The buffer memory 1220 may buffer data to be used in a fine program operation during a write request. In FIG. 19, the buffer memory 1220 is disposed inside the controller 1200. However, the inventive concept is not limited thereto. The buffer memory 1220 may be disposed outside the controller 1200.

[0147] The ECC circuit 1230 may calculate an ECC value of data to be programmed during a write operation, correct an error of data read during a read operation based on the ECC value, and correct an error of recovered data from the nonvolatile memory device 1100 during a data recovery operation.

[0148] The dummy data generator 1240 generates dummy data. The dummy data generator may generate dummy data using a seed value. The dummy data may be random data.

[0149] The host interface 1250 may provide interface with an external device. The nonvolatile memory interface 1260 may provide interface with the nonvolatile memory device 1100.

[0150] FIG. 21 illustrates an embedded multimedia card (eMMC) 2000 according to an exemplary embodiment of the inventive concept. The inventive concept may be applied to an eMMC. As illustrated, the eMMC 2000 may include at least one NAND flash memory device 2100 and a controller 2200.

[0151] The controller 2200 is connected to the NAND flash memory device 2100 through a plurality of channels. The controller 2200 may include at least one controller core 2210, a host interface 2250, and a NAND interface 2260. The at least one control core 2210 controls the overall operation of the eMMC 2000. The host interface 2250 may provide host interface with the controller 2200. The NAND interface 2260 may provide interface between the NAND flash memory device 2100 and the controller 2200.

[0152] In an exemplary embodiment, the host interface 2250 may be a parallel interface (e.g., MMC interface). Alternatively, the host interface 2250 of the eMMC 2000 may be a serial interface (e.g., UHS-II or UFS interface).

[0153] The eMMC 2000 receives first and second power supply voltages Vcc and Vccq from a host. The first power supply voltage Vcc is supplied to the NAND flash memory device 2100 and the NAND interface 2260, and the second power supply voltage Vccq is supplied to the controller 2200.

[0154] FIG. 22 is a block diagram of a computing device 3000 according to an exemplary embodiment of the inventive concept. As illustrated, the computing device 3000 includes a processor 3100, a memory 3200, a storage 3300, a modem 3400, and a user interface 3500. The processor 3100 may control the overall operation of the computing device 3000 and perform a logic operation. For example, the processor 3100 may be a universal processor or an application processor.

[0155] The memory 3200 may communicate with the processor 3100. The memory 3200 may be a working memory of the processor 3100 or the computing device 3000. The memory 3200 may include a volatile memory such as static random access memory (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM) or a nonvolatile memory such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM) and ferroelectric RAM (FRAM).

[0156] The storage 3300 may store data that the computing device 3000 desires to stores for a long period. The storage 3300 may include a hard disk drive (HDD) or a nonvolatile memory device such as flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0157] The storage 3300 may be the nonvolatile memory device described with reference to FIGS. 1 to 17. As described with reference to FIGS. 1 to 17, the storage 3300 may program an upper page of a partial block where SPO occurs to prevent leakage current from flowing through the partial block from bitlines.

[0158] The memory 3200 and the storage 3300 may include the same type of nonvolatile memory devices. In this case, the memory 3200 and the storage 3300 may include a single semiconductor integrated circuit.

[0159] The modern 3400 may be configured to communicate with an external device according to the control of the processor 3100. For example, the modern 3400 may perform wired or wireless communications with an external device. The modem 3400 may perform communications based on at least one of wireless communication techniques or protocols such as LTE (Long Term Evolution), WiMax, GSM (Global System for Mobile communication), CDMA (Code Division Multiple Access), Bluetooth, NFC (Near Field Communication), WiFi, and RFID (Radio Frequency Identification) or wired communication techniques or protocols such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SCSI (Small Computer Small Interface), Firewire, and PCI (Peripheral Component interconnection).

[0160] The user interface 3500 may communicate with a user according to the control of the processor 3100. For example, the user interface 3500 may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch ball, a touch pad, a camera, a gyroscope sensor, and a vibration sensor. The user interface 3500 may include user output interfaces such as an liquid crystal display (LCD), an organic light emitting diode (OLED) display, an active matrix OLED (AMOLED) display, an LED, a speaker, and a motor.

[0161] While the present inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims.