Buck converter with a variable-gain feedback circuit for transient responses optimization

[0001] 1. Technical Field

[0002] The present disclosure relates generally to a buck converter, and more particularly to a buck converter with a variable-gain feedback circuit for transient responses optimization.

[0003] 2. Description of Related Art

[0004] Switching buck converters are widely used as voltage regulators in battery-powered portable devices to achieve high power-conversion efficiency. FIG. 10 shows a block diagram of a conventional buck converter which includes a power stage and a controller. Also, FIG. 11A and FIG. 11B are schematic circuit diagrams respectively showing operations of a high-side ON state and a low-side ON state in FIG. 10. The synchronous topology of the buck converter has two switches, one is referred to as the high-side switch S_H and the other is referred to as the low-side switch S_L.

[0005] The controller mainly has an error amplifier with compensation components 21, a pulse width modulation (PWM) generator 22, and a driver 23. The error amplifier with compensation components 21 receives a reference voltage V_REF and a feedback voltage V_FB to generate an error voltage. The feedback voltage V_FB is obtained by dividing the output voltage V_O by resistors R_O1,R_O2. The PWM generator 22 receives the error voltage and a voltage, which may be a sawtooth signal, a sensed inductor current I_L or the output voltage V_O, to generate a PWM signal to control the high-side switch S_H and the low-side switch S_L. Accordingly, in steady state conditions, this cycle of turning the high-side and low-side switches S_H,S_L ON and OFF complimentary to each other regulates the output voltage V_O to its targeted value.

[0006] As shown in FIGS. 12A-12B, the inductor current I_L is increased when the high-side switch S_H is turned on; on the contrary, the inductor current I_L is decreased when the low-side switch S_L is turned on.

[0007] To integrate more multi-functional system-on-chip (SOC) applications into battery-powered portable devices, buck converters should provide a regulated voltage despite large and frequently varying load current. In addition, to reduce the power consumption of digital systems, buck converters should also offer an adjustable output voltage for realizing dynamic voltage scaling (DVS). However, if the transient responses of the buck converters are slow, a large output voltage undershoot/overshoot or a long settling time will occur, resulting in reduced reliability of the systems or degraded signal-to-noise ratio (SNR) performance of noise-sensitive circuits. These problems can be alleviated by a buck converter that simultaneously achieves both fast load transient response and fast DVS transient response.

[0008] To improve the power stage for achieving fast transient responses, asynchronous low dropout regulator (LDO) or a power switch can be connected in parallel with the buck converter to bypass the output inductor L_O and prevent the transient response from being limited by the charging slope of the output inductor current I_L. However, the chip area and power consumption will increase.

[0009] To improve the controller for achieving fast load transient response, a feed-forward path in V²-based controls can deliver the output voltage directly to the PWM generator 22 and bypass the error amplifier with compensation components 21, which limits transient responses. The adaptive pole-zero position technique can reconfigure the error amplifier with compensation components 21 to extend the loop bandwidth during load transient. In addition, for achieving fast DVS transient response, the end-point prediction (EPP) technique can predict the output voltage of the error amplifier with compensation components 21 to accelerate the transient response. However, the aforementioned techniques for improving the controller can only achieve either fast load transient or fast DVS transient response.

[0010] Accordingly, a buck converter with a variable-gain feedback circuit for transient responses optimization is provided to attempt to resolve the above-mentioned disadvantages. The buck converter with a variable-gain feedback circuit for transient responses optimization includes a power stage circuit and a control circuit. The power stage circuit with an input side and an output side has a pair of switches and an output capacitor. The switches are electrically connected at the input side. The output capacitor is electrically connected at the output side.

[0011] The control circuit has a current-sensing unit, an error-amplifying and transient-holding unit, a transient-optimized feedback unit, and a PWM generation unit. The current-sensing unit senses an output capacitor current flowing through the output capacitor and converts the output capacitor current into a converting signal. The error-amplifying and transient-holding unit receives a feedback voltage at the output side and a reference voltage to generate an error signal. The transient-optimized feedback unit receives the feedback voltage and the reference voltage to convert the voltage difference into a proportional voltage signal by a variable gain value.

[0012] The PWM generation unit receives the proportional voltage signal and a sensing voltage signal obtained by adding the converting signal and the error signal to generate a PWM signal to control the switches. When the proportional voltage signal is equal to the sensing voltage signal, the switches are controlled by the PWM signal to start charging and discharging the output capacitor.

[0013] The buck converter is substantially a capacitor-current-controlled hysteretic buck converter, which is implemented to simultaneously optimize both a load transient response and a DVS transient response with insignificant increase of chip area and power consumption. Also, the optimized load transient response and DVS transient response are implemented for minimizing both output voltage undershoot/overshoot and settling time in the buck converter.

[0014] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the present disclosure as claimed. Other advantages and features of the present disclosure will be apparent from the following description, drawings and claims.

[0028] Reference will now be made to the drawing figures to describe the present disclosure in detail.

[0029] FIG. 1 shows a buck converter with a variable-gain feedback circuit for transient responses optimization. The buck converter includes a power stage circuit and a control circuit. The power stage circuit with an input side and an output side includes a pair of switches S_H,S_L, an output capacitor C_O, and an output inductor L_O. The switches S_H,S_L include a high-side switch S_H and a low-side switch S_L, both are electrically connected to an input voltage V_I, which is a direct current (DC) voltage at the input side. In this example, the high-side switch S_H is, but not limited to, a P-type MOSFET switch and the low-side switch S_L is, but not limited to, an N-type MOSFET switch.

[0030] The output capacitor C_O is electrically connected between the output side and a ground. In particular, the output capacitor C_O is modeled with its parasitic inductance L_ESL and parasitic resistance R_ESR. The output inductor L_O is electrically connected between the switches S_H,S_L and the output capacitor C_O at the output side.

[0031] In the present disclosure, the buck converter is substantially a capacitor-current-controlled hysteretic buck converter, which is implemented to optimize both a load transient response and a DVS transient response with insignificant increase of chip area and power consumption.

[0032] The control circuit includes a current-sensing unit 11, an error-amplifying and transient-holding unit 12, a transient-optimized feedback unit 13, a calculation unit 14, a PWM generation unit 15, a driving unit 16, and a zero current detecting unit (ZCD) 17.

[0033] The current-sensing unit 11 senses an output capacitor current I_Co flowing through the output capacitor C_O and converts the output capacitor current I_Co into a converting voltage signal V_CCS. The error-amplifying and transient-holding unit 12 receives a feedback voltage V_FB at the output side and a reference voltage V_REF to output an error voltage signal V_C. The transient-optimized feedback unit 13 receives the feedback voltage V_FB and the reference voltage V_REF to output a proportional voltage signal V_W. The calculation unit 14 receives the converting voltage signal V_CCS and the error voltage signal V_C to generate a sensing voltage signal V_S. The PWM generation unit 15 receives the proportional voltage signal V_W and the sensing voltage signal V_S to generate a PWM signal V_PWM to control the switches S_H,S_L.

[0034] The zero current detecting unit 17 receives a ZCD-disabling signal V_DZ generated from the transient-optimized feedback unit 13 and an inductor input voltage V_LX at the input side to generate a zero current output signal V_ZC. The driving unit 16 may drive the switches S_H,S_L based on the PWM signal V_PWM. Alternatively, the driving unit 16 may further drive the switches S_H,S_L based on both the zero current output signal V_ZC and the PWM signal V_PWM.

[0035] The detailed operation of the buck converter with a variable-gain feedback circuit for transient responses optimization will be described hereinafter as follows.

[0036] FIGS. 2A-2F show corresponding current and voltage waveforms in load transient response of the buck converter, where I_LOAD is the load current, I_L is the output inductor current, I_Co is the output capacitor current, V_O is the output voltage, V_REF is the reference voltage, V_FB is the feedback voltage, V_W is the proportional voltage signal, V_S is the sensing voltage signal, and V_PWM is the PWM signal. As shown in FIG. 2A, the output inductor current I_L should start charging instantly when the load transient starts at a first time point t₁, and continue charging until the output inductor current I_L exceeds the load current I_LOAD to minimize a first electric charge Q₁, which is defined as the decreased electric charge stored in the output capacitor C_O before the output inductor current I_L equals the load current I_LOAD at a zero-crossing time point t_C, resulting in a minimized output voltage undershoot ΔV_OU shown in FIG. 2C. Moreover, if the output inductor current I_L starts discharging at an optimal time point t_SW to ensure that a second electric charge Q₂ equals the minimized first electric charge Q₁, resulting in a minimized settling time ΔT_S shown in FIG. 2C. The second electric charge Q₂ is defined as the excess electric charge stored in the output capacitor C_O before the next switching activity of the power stage. On the contrary, if the output inductor current I_L starts discharging too late or too early, the settling time ΔT_S will be longer.

[0037] FIGS. 3A-3F show corresponding current and voltage waveforms in DVS transient response of the buck converter. Similarly, the optimized up-tracking DVS transient response shown in FIG. 3A ensures that the output inductor current I_L starts charging instantly at the first time point t₁, and starts discharging at the optimal time point t_SW. Therefore, a minimized settling time ΔT_S and negligible overshoot are achieved as shown in FIG. 3C. On the contrary, if the output inductor current I_L starts discharging too late or too early, the settling time ΔT_S will be longer and the overshoot is larger.

[0038] FIG. 4 shows a detailed block circuit diagram of FIG. 1. The buck converter is substantially a hysteretic buck converter. The output capacitor C_O is modeled with its parasitic inductance L_ESL and parasitic resistance R_ESR. The current-sensing unit 11 includes a current sensor 111 and a resistor 112 with a resistance value R_I. The current sensor 111 senses the output capacitor current I_Co and then the resistor 112 converts the output capacitor current I_Co into the converting voltage signal V_CCS. More specifically, the converting voltage signal V_CCS is converted by multiplying the output capacitor current I_Co by the resistance value R_I of the resistor 112. Thus, the converting voltage signal V_CCS can be expressed as:
V_CCS(t)=R_I×I_Co(t)  (1)

[0039] The transient-optimized feedback unit 13 includes a voltage difference sensing unit 131 and a variable gain amplifier 132. The voltage difference sensing unit 131 receives the feedback voltage V_FB and the reference voltage V_REF and generates a voltage difference between the feedback voltage V_FB and the reference voltage V_REF, and then the voltage difference is multiplied by a variable gain value K_TOF of the variable gain amplifier 132 to generate the proportional voltage signal V_W. In addition, the transient-optimized feedback unit 13 further generates a transient detection signal V_TH and a ZCD-disabling signal V_DZ, described in detail later.

[0040] The error-amplifying and transient-holding unit 12 includes an error amplifier 121, a switch 122, and a compensation capacitor 123. The error amplifier 121 receives the feedback voltage V_FB and the reference voltage V_REF and integrates an error of the output voltage V_O to adjust the error voltage signal V_C outputted from the error amplifier 121. In particular, the switch 122 provided between the error amplifier 121 and the compensation capacitor 123 is dynamically activated by the transient detection signal V_TH generated from a transient detection unit of the transient-optimized feedback unit 13.

[0041] Accordingly, by respectively using the current-sensing unit 11 and transient-optimized feedback unit 13, the load transient and DVS transient information bypasses the error-amplifying and transient-holding unit 12 and affects the PWM signal V_PWM through the PWM generation unit 15, which is substantially a hysteretic comparator, resulting in an instant response of the output inductor current I_L. Especially, both load transient response and DVS transient response are not limited by the error-amplifying and transient-holding unit 12 since the error voltage signal V_C does not need to change when the load current I_LOAD or the reference voltage V_REF changes.

[0042] The similarities between the detailed waveforms of both optimized responses are examined to simultaneously optimize load transient response and DVS transient response. As mentioned above, the converting voltage signal V_CCS is subtracted by the error voltage signal V_C to obtain the sensing voltage signal V_S, namely V_S(t)=V_CCS(t)−V_C(t) since the error voltage signal V_C is obtained from a negative feedback path through the error-amplifying and transient-holding unit 12. However, the error voltage signal V_C outputted from the error amplifier 121 will remain unchanged during transients by the switch 122 and the compensation capacitor 123.

[0043] More specifically, the purpose of the error amplifier 121 is to integrate the error of the output voltage V_O in the steady-state period to adjust the error voltage signal V_C outputted from the error amplifier 121 for a more accurate output voltage V_O. However, the error amplifier 121 also integrates the error of the output voltage V_O in the transient period, resulting in an unnecessary change of the error voltage signal V_C. The change of the error voltage signal V_C affects the transient response optimization of the transient-optimized feedback unit 13 since the sensing voltage signal V_S does not proportionally change with the output capacitor current I_Co. This effect of change of the error voltage signal V_C is large for a large DVS transient, resulting in a large output voltage overshoot and a longer settling time.

[0044] Although increasing the compensation capacitor 123 can reduce the change of the error voltage signal V_C during transients, the chip area and costs increase. As mentioned above, the transient detection signal V_TH, which is generated by the transient-optimized feedback unit 13, pulls high when a large transient is detected. Accordingly, the transient detection signal V_TH opens the switch 122 during a large transient to disconnect the error amplifier 121 from the compensation capacitor 123 so that the change of the error voltage signal V_C is greatly reduced without increasing the compensation capacitor 123. Therefore, the sensing voltage signal V_S will proportionally change with the output capacitor current I_Co during transients according to equation (1).

[0045] When load transient or DVS transient starts at the first time point t₁, the output inductor current I_L starts charging the output capacitor C_O, resulting in an increasing sensing voltage signal V_S. Also, the sensing voltage signal V_S continues increasing until it equals the V_W generated by the transient-optimized feedback unit 13. The PWM generation unit 15, namely the hysteretic comparator will control the PWM signal V_PWM to ensure that the output inductor current I_L starts discharging at the optimal time point t_SW to settle the output voltage V_O to its targeted value at the second time point t₂. The relationship between all waveforms in load transient response shown in FIGS. 2A-2F is identical to that in DVS transient response shown in FIGS. 3A-3F from the optimal time point t_SW to the second time point t₂. Accordingly, the excess electric charge Q_Co of the output capacitor C_O from the optimal time point t_SW to the second time point t₂ is derived as:

[0046] $\begin{array}{cc}{Q}_{\mathrm{Co}}=\frac{I_{\mathrm{Co}}\left(t_{\mathrm{SW}}\right)}{2}\times \left(t_2-t_{\mathrm{SW}}\right)=\frac{I_{\mathrm{Co}}\left(t_{\mathrm{SW}}\right)}{2}\times \frac{I_{\mathrm{Co}}\left(t_{\mathrm{SW}}\right)}{m_f}& \left(2\right)\end{array}$

[0047] Since the change in the output inductor current I_L and the output capacitor current I_Co are identical from the optimal time point t_SW to the second time point t₂, m_f is the falling slope of the output inductor current I_L, resulting in

[0048] $\mathrm{mf}=\frac{\stackrel{\_}{V_O}}{L_O},$
where V_O is the average of the output voltage V_O from the optimal time point t_SW to the second time point t₂. Thus,

[0049] $\begin{array}{cc}{Q}_{\mathrm{Co}}=\frac{L_O}{2\stackrel{\_}{V_O}}\times I_{\mathrm{Co}}^2\left(t_{\mathrm{SW}}\right)& \left(3\right)\end{array}$

[0050] Since the optimized response ensures that the output voltage V_O settles to its targeted value at the second time point t₂, the increased voltage of the output voltage V_O from the optimal time point t_SW to the second time point t₂ can be expressed as:

[0051] $\begin{array}{cc}{V}_O\left(t_2\right)-V_O\left(t_{\mathrm{SW}}\right)=\frac{Q_{\mathrm{Co}}}{C_O}-R_{\mathrm{ESR}}\times I_{\mathrm{Co}}\left(t_{\mathrm{SW}}\right)& \left(4\right)\end{array}$

[0052] where the first term on the right side of equation (4) is the voltage change due to the excess electric charge Q_Co stored in the output capacitor C_O, while the second term on the right side of equation (4) is the voltage across the parasitic resistance R_ESR due to the output capacitor current I_Co at the optimal time point t_SW. By combining equations (1), (3), and (4), the optimized response should ensure

[0053] $\begin{array}{cc}{V}_S\left(t_{\mathrm{SW}}\right)=R_I\times \frac{R_{\mathrm{ESR}}+\sqrt{R_{\mathrm{ESR}}^2+\frac{2L_O}{\beta \stackrel{\_}{V_O}{C}_O}\left[V_{\mathrm{FB}}\left(t_2\right)-V_{\mathrm{FB}}\left(t_{\mathrm{SW}}\right)\right]}}{\frac{L_O}{\stackrel{\_}{V_O}{C}_O}}& \left(5\right)\end{array}$

[0054] where β is the ratio of the feedback voltage V_FB(t) to the output voltage V_O(t). As depicted in FIGS. 2A-2F and FIGS. 3A-3F, a condition of V_FB(t₂)=V_REF(t_SW) will be satisfied in both load transient response and DVS transient response so that V_REF(t_SW) can replace V_FB(t₂) in equation (5).

[0055] Therefore, if the transient-optimized feedback unit 13 can be designed to generate the proportional voltage signal V_W as

[0056] $\begin{array}{cc}{V}_W\left(t\right)=R_I\times \frac{R_{\mathrm{ESR}}+\sqrt{R_{\mathrm{ESR}}^2+\frac{2L_O}{\beta \stackrel{\_}{V_O}{C}_O}\left[V_{\mathrm{REF}}\left(t\right)-V_{\mathrm{FB}}\left(t\right)\right]}}{\frac{L_O}{\stackrel{\_}{V_O}{C}_O}},& \left(6\right)\end{array}$
and then when the PWM generation unit 15 detects that the proportional voltage signal V_W equals the sensing voltage signal V_S at the optimal time point t_SW, equation (5) will be guaranteed. In other words, if the transient-optimized feedback unit 13 can convert V_REF(t)−V_FB(t) into V_W(t) according to equation (6), the optimized load transient response and DVS transient response can be simultaneously achieved. The analysis for heavy-to-light load transient response and down-tracking DVS transient response can be similarly derived by replacing m_f in equation (2) with the rising slope of the current ripple m_r which is

[0057] $\frac{V_I-\stackrel{\_}{V_O}}{L_O}.$

[0058] By individually examining both load transient response and DVS transient response above, it is found that the key to transient optimization is the relationship between the output capacitor C_O and the required excess electric charge Q_Co. Therefore, regardless of whether the load transient or/and DVS transient occur(s) alone or simultaneously, the transient response can be optimized by the control circuit of the present disclosure.

[0059] FIG. 5 shows the circuit implementation of the current-sensing unit 11. The current-sensing unit 11 connected in parallel with the output capacitor C_O is implemented by a poly-insulator-poly (PIP) capacitor whose bottom plate is connected to the output voltage V_O since the equivalent impedance is less sensitive to the parasitic capacitance at the output voltage V_O than at the voltage V_CL. An inductor L_S is an active inductor and designed as L_S=C_LS/G²_M, while R_S is implemented as the diode-connected transistor M_Rs, where R_S=1/G_MR_S. M_Rs is biased by the current source I_S,bias to allow negative output capacitor current I_Co sensing. The sensed capacitor current flows into a resistor R_I by current mirrors M₁ to M₃. C_S, L_S, and R_S are series-connected to implement Z_S, which is a scaled replica impedance of the output capacitor Z_Co.

[0060] FIG. 6 shows the theoretical transfer curve C_T of V_W(t) versus V_REF(t)−V_FB(t) as expressed in equation (6). If V_W(t) is generated according to its theoretical transfer function as expressed in equation (6), the output voltage V_O settling exactly to the targeted value at the second time point t₂ is guaranteed, as shown in FIGS. 2A-2F and FIGS. 3A-3F. However, according to a commonly-used definition, if the error of the output voltage V_O is within ±1% of the targeted value, it is regarded as being settled. Therefore, by replacing V_O(t₂) with V_O(t₂)×(1±1%) in equation (4), the boundaries between an acceptable and unacceptable V_W(t) transfer function in terms of V_REF(t)−V_FB(t) can be derived. After plotting the boundaries with the boundary curves C_B, including an upper boundary curve and a lower boundary curve, an optimal region and a non-optimal region of V_W(t) versus V_REF(t)−V_FB(t) can be obtained. In particular, a region between the boundary curves shown in the first quadrant and the third quadrant is the optimal region; and a region out of the boundary curves is the non-optimal region. A non-linear input-to-output transfer function of the transient-optimized feedback unit 13 is required to ensure that proportional voltage signal V_W falls in the optimal region over a wide range of the voltage differences between the reference voltage V_REF and the feedback voltage V_FB, namely V_REF−V_FB. To avoid a complicated circuit for implementing a square root function, the transient-optimized feedback unit 13 realizes a piecewise linear transfer function, depicted as the piecewise lines L_P.

[0061] FIG. 7 shows the circuit implementation of the transient-optimized feedback unit 13, which operates in three different states according to three different ranges of |V_REF−V_FB|. In state 1, V_REF−V_FB| is small, and M₉ to M₁₀ are designed to turn off. As such, the transient-optimized feedback unit 13 operates as a folded-cascode operational amplifier, and the cascade branches, comprising M₃ to M₈, are biased at (I_B2−I_B1). OP₁ and OP₂ fix the voltage across to R1 to (V_REF−V_FB), which is then converted to current I_R1, where I_R1=(V_REF−V_FB)/R₁. The output current I_R2=2×I_R1 so that the input-to-output voltage gain of the transient-optimized feedback unit 13 is 2×(R₂/R₁).

[0062] By designing I_B1<I_B2<2×I_B1, the transient-optimized feedback unit 13 operates in state 2 when |V_REF−V_FB| exceeds the boundary voltage V_BD1 shown in FIG. 6, where V_BD1=(I_B2−I_B1)×R₁. Since I_R1 is larger than (I_B2−I_B1) in state 2, no bias current flows through the left-half cascode branch, comprised of M₃ to M₅. As a result, I_R1 only flows through M₂ and M₈ to output; therefore, I_R2=I_R1, and the input-to-output voltage gain of the transient-optimized feedback unit 13 is only (R₂/R₁). In addition, since I_R1 is larger than (I_B2−I_B1) in state 2, both M₉ and M₁₁ are forced to turn on, pulling the transient detection signal V_TH high. The transient detection signal V_TH enables the transient hold technique to decide if the error amplifier 121 should be disconnected from the compensation capacitor 123. For design simplicity, the threshold voltage of the transient hold technique is the same as V_BD1.

[0063] If |V_REF−V_FB|>V_BD2, where V_BD2=I_B1×R₁, I_R1 is larger than I_B1, the excess current will increase the source voltage of M₂ so that the gate-source voltage of M₂ decreases, and finally M₂ turns off. Accordingly, the transient-optimized feedback unit 13 is now operating in state 3. As a result, both branches of the folded-cascode operational amplifier are disabled, so I_R2 is independent of (V_REF−V_FB), resulting in a flat curve shown in FIG. 6.

[0064] To disable the zero current detecting unit 17 during the heavy-to-light load-transient or down-tracking DVS transient period, the transient-optimized feedback unit 13 also generates a ZCD-disabling signal V_DZ by a method similar to generating the transient detection signal V_TH, except that the ZCD-disabling signal V_DZ pulls high only when (V_FB−V_REF)>V_BD1 instead of (V_REF−V_FB)>V_BD1.

[0065] In practical implementation, the equivalent C_O, R_ESR, and L_ESL shown in FIG. 4 vary with time, different operating output voltages V_O and PCB layout. According to the theoretical transfer function of equation (6), the variations of the equivalent C_O and R_ESR affect the optimal region depicted in FIG. 6.

[0066] FIG. 8 shows the circuit implementation of the error-amplifying and transient-holding unit 12, namely the error amplifier 121 with the transient hold technique. The error amplifier 121 is composed of M₁ to M₈, and I_B, and since the error voltage signal V_C does not need to change when I_LOAD or V_REF changes, the requirement of the bandwidth of the error amplifier 121 is relaxed. Therefore, the power consumption of the error amplifier 121 is much smaller than that of a conventional one. When the transient detection signal V_TH is high, the switch 122, implemented by the transmission gates M_SN and M_SP, disconnects the error amplifier 121 to hold the error voltage signal V_C. In addition, the compensation capacitor 123 is implemented as a MOS capacitor M_C.

[0067] For different patterns of V_REF(t)−V_FB(t), the exact error voltage signal V_C changes after the switch S_TH opens are different due to the sampling error of the aperture jitter effect. However, for fast DVS transients with slopes larger than 0.2 V/μs, the maximum value of the change of the error voltage signal V_C is less than 5 mV, which is insignificant compared with V_W shown in FIG. 6. For load transients or slower DVS transients, V_REF(t)−V_FB(t) are small, resulting in a negligible change of the error voltage signal V_C.

[0068] FIG. 9 shows the circuit implementation of the zero current detecting unit 17. In order to reduce the power loss caused by current ripple in light-load conditions, the zero current detecting unit 17 is used to prevent reversed output inductor current I_L and allow the buck converter to operate in discontinuous conduction mode (DCM). However, when load current I_LOAD is small, the heavy-to-light load transient and down-tracking DVS transient response will be limited since the output voltage V_O can only be discharged by a small I_LOAD. The effect is more significant in the down-tracking DVS transient response. In the present disclosure, the zero current detecting unit 17 is temporarily disabled to allow a reversed output inductor current I_L when a large voltage difference between the feedback voltage V_FB and the reference voltage V_REF, namely V_FB−V_REF, is detected so that output voltage V_O can be discharged through the reversed output inductor current I_L.

[0069] The zero current detecting unit 17 uses a comparator and a D-type flip-flop to compare V_LX with the ground and detect the gate terminal of the high-side power MOSFET to determine if the zero current detecting unit 17 is activated. In the present disclosure, an inverter and an AND gate are used to temporarily disable the zero current detecting unit 17 when the ZCD-disabling signal V_DZ is pulled-high by the transient-optimized feedback unit 13 in FIG. 7, thereby realizing transient response optimization.

[0070] In conclusion, the present disclosure has the following advantages:

[0071] 1. The buck converter is substantially a capacitor-current-controlled hysteretic buck converter, which is implemented to simultaneously optimize both a load transient response and a DVS transient response with insignificant increase of chip area and power consumption;

[0072] 2. The optimized load transient response and DVS transient response are implemented for minimizing both output voltage undershoot/overshoot and settling time in the buck converter; and

[0073] 3. The buck converter with a variable-gain feedback circuit for transient responses optimization has been implemented in a single chip, which is suitable for compact-sized portable devices.

[0074] Although the present disclosure has been described with reference to the preferred embodiment thereof, it will be understood that the present disclosure is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the present disclosure as defined in the appended claims.