US 9,530,892 B2Grant

Semiconductor device and method for manufacturing the same

Issue Date:2016-12-27

•16 Claims

•41 Drawing Sheets

Abstract

A semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, and an oxide insulating film covering the transistor. The multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide insulating film contains more oxygen than that in the stoichiometric composition, and in the transistor, by a bias-temperature stress test, threshold voltage does not change or the amount of the change in a positive direction or a negative direction is less than or equal to 1.0 V, preferably less than or equal to 0.5 V.

Metadata

Assignee

Semiconductor Energy Laboratory Co., Ltd.

Inventors

Junichi Koezuka
Yukinori Shima
Hajime Tokunaga
Toshinari Sasaki
Keisuke Murayama
Daisuke Matsubayashi

Application Information

Application Number:US 14/062,481

Filing Date:2013-10-24

Priority Date:2012-10-24

Art Unit:2899

Classifications

IPC:

H01L21/00H01L27/146H01L29/786H01L21/02H01L29/51H01L29/66

Field of Search:

H01L 29/51H01L 29/66969H01L 29/7869H01L 29/78606H01L 29/78696H01L 21/02109H01L 21/02631H01L 21/02263H01L 21/02565

Patent Drawings (41 sheets)

Description

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device including a transistor and a method for manufacturing the semiconductor device.

[0003] 2. Description of the Related Art

[0004] Transistors used for most flat panel displays typified by a liquid crystal display device and a light-emitting display device are formed using silicon semiconductors such as amorphous silicon, single crystal silicon, and polycrystalline silicon provided over glass substrates. Further, transistors formed using the silicon semiconductors are used in integrated circuits (ICs) and the like.

[0005] In recent years, attention has been drawn to a technique in which, instead of a silicon semiconductor, a metal oxide exhibiting semiconductor characteristics is used for transistors. Note that in this specification, a metal oxide exhibiting semiconductor characteristics is referred to as an oxide semiconductor.

[0006] For example, a technique is disclosed in which a transistor is manufactured using zinc oxide or an In—Ga—Zn-based oxide as an oxide semiconductor and the transistor is used as a switching element or the like of a pixel of a display device (see Patent Documents 1 and 2).

REFERENCE

Patent Document

[0007] [Patent Document 1] Japanese Published Patent Application No. 2007-123861
[0008] [Patent Document 2] Japanese Published Patent Application No. 2007-096055

SUMMARY OF THE INVENTION

[0009] In a transistor using an oxide semiconductor film, there are a large number of oxygen vacancies in the oxide semiconductor film, which causes poor electrical characteristics of the transistor and causes an increase in the amount of change in electrical characteristics of the transistor, typically the threshold voltage due to a change over time or a stress test (e.g., a bias-temperature (BT) stress test).

[0010] Thus, an object of one embodiment of the present invention is to reduce defects in an oxide semiconductor film of a semiconductor device including the oxide semiconductor film. Another object of one embodiment of the present invention is to improve electrical characteristics of a semiconductor device including an oxide semiconductor film. Another object of one embodiment of the present invention is to improve reliability of a semiconductor device including an oxide semiconductor film.

[0011] One embodiment of the present invention is a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, and an oxide insulating film covering the transistor. In the semiconductor device, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition, and the transistor has characteristics in which, by a bias-temperature stress test, threshold voltage does not change or changes in a positive direction or a negative direction and the amount of the change in a negative direction or a positive direction is less than or equal to 1.0 V, preferably less than or equal to 0.5 V.

[0012] Note that the oxide semiconductor film preferably contains In or Ga.

[0013] Further, the energy of the conduction band bottom of the oxide film containing In or Ga is closer to the vacuum level than the energy of the conduction band bottom of the oxide semiconductor film. Furthermore, the difference between the energy of the conduction band bottom of the oxide film containing In or Ga and the energy of the conduction band bottom of the oxide semiconductor film is preferably greater than or equal to 0.05 eV and less than or equal to 2 eV. Note that an energy difference between the vacuum level and the conduction band bottom is also referred to as an electron affinity. Thus, it is preferable that the electron affinity of the oxide film containing In or Ga be less than the electron affinity of the oxide semiconductor film and the difference be greater than or equal to 0.05 eV and less than or equal to 2 eV.

[0014] Further, it is preferable that each of the oxide semiconductor film and the oxide film containing In or Ga be an In-M-Zn oxide (M represents Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) film and the atomic ratio of M in the oxide film containing In or Ga be higher than that in the oxide semiconductor film.

[0015] Further, it is preferable that, in the multilayer film, an absorption coefficient derived from a constant photocurrent method (CPM) be lower than 1×10⁻³/cm in an energy range of 1.5 eV to 2.3 eV.

[0016] Further, it is preferable that the silicon concentration in between the oxide semiconductor film and the oxide film containing In or Ga be lower than 2×10¹⁸atoms/cm³.

[0017] Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of forming a gate electrode and a gate insulating film, forming, over the gate insulating film, a multilayer film including an oxide semiconductor film and an oxide film containing In or Ga, forming a pair of electrodes in contact with the multilayer film, and forming an oxide insulating film over the multilayer film and the pair of electrodes. The oxide insulating film is formed under the following conditions: the substrate placed in a treatment chamber which is vacuum-evacuated is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; pressure in the treatment chamber is set to be greater than or equal to 100 Pa and less than or equal to 250 Pa with introduction of a source gas into the treatment chamber; and a high-frequency power higher than or equal to 0.17 W/cm²and lower than or equal to 0.5 W/cm²is supplied to the electrode provided in the treatment chamber.

[0018] In accordance with one embodiment of the present invention, defects in an oxide semiconductor film of a semiconductor device including the oxide semiconductor film can be reduced. Further, in accordance with one embodiment of the present invention, the electrical characteristics of a semiconductor device including an oxide semiconductor film can be improved. Further, in accordance with one embodiment of the present invention, reliability of a semiconductor device or the like including an oxide semiconductor film can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In the accompanying drawings:

[0020] FIGS. 1A to 1D are a top view and cross-sectional views illustrating one embodiment of a transistor, and a graph showing Vg-Id characteristics of the transistor;

[0021] FIGS. 2A to 2C are diagrams illustrating the band structure of a transistor;

[0022] FIGS. 3A to 3D are cross-sectional views illustrating one embodiment of a method for manufacturing a transistor;

[0023] FIGS. 4A to 4C are cross-sectional views each illustrating one embodiment of a transistor;

[0024] FIGS. 5A to 5C are a top view and cross-sectional views illustrating one embodiment of a transistor, and FIGS. 5D and 5E are cross-sectional views illustrating another embodiment of a transistor;

[0025] FIGS. 6A and 6B are diagrams illustrating the band structure of a transistor;

[0026] FIGS. 7A to 7C are a top view and cross-sectional views illustrating one embodiment of a transistor;

[0027] FIGS. 8A to 8D are cross-sectional views illustrating one embodiment of a method for manufacturing a transistor;

[0028] FIGS. 9A to 9C are a top view and cross-sectional views illustrating one embodiment of a transistor;

[0029] FIGS. 10A to 10D are cross-sectionals views illustrating one embodiment of a method for manufacturing a transistor;

[0030] FIGS. 11A to 11C are a top view and cross-sectional views illustrating one embodiment of a transistor;

[0031] FIG. 12 is a cross-sectional view illustrating one embodiment of a transistor;

[0032] FIGS. 13A to 13C are top views each illustrating one embodiment of a semiconductor device;

[0033] FIGS. 14A and 14B are cross-sectional views each illustrating one embodiment of a semiconductor device;

[0034] FIGS. 15A to 15C illustrate electronic appliances each including a semiconductor device of one embodiment of the present invention;

[0035] FIGS. 16A to 16C illustrate an electronic appliance including a semiconductor device of one embodiment of the present invention;

[0036] FIGS. 17A and 17B are graphs each showing Vg-Id characteristics of a transistor;

[0037] FIG. 18 is a graph showing the amount of change in threshold voltage of transistors after a BT photostress test;

[0038] FIG. 19 is a graph showing spin density at a g-factor originating from oxygen vacancies in an oxide semiconductor film;

[0039] FIGS. 20A and 20B are graphs showing the result of CPM measurement of a multilayer film included in a transistor;

[0040] FIGS. 21A and 21B are graphs each showing the result of ToF-SIMS of a multilayer film included in a transistor;

[0041] FIGS. 22A and 22B are graphs each showing the result of TDS measurement of an oxide insulating film included in a transistor;

[0042] FIG. 23 is a graph showing spin density at a g-factor originating from dangling bonds in an oxide insulating film;

[0043] FIG. 24 is a top view showing a structural example of a pixel portion of a display device;

[0044] FIG. 25 is a cross-sectional view showing a structural example of a pixel portion of a display device;

[0045] FIGS. 26A and 26B show one example of a connection structure of a common electrode of a display device and one example of a connection structure of a wiring of a display device;

[0046] FIG. 27 is a cross-sectional view showing a structural example of a pixel portion of a display device;

[0047] FIG. 28 is a top view illustrating one embodiment of a semiconductor device;

[0048] FIGS. 29A and 29B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device;

[0049] FIGS. 30A to 30C are an exploded perspective view and top views showing a structural example of a touch sensor;

[0050] FIGS. 31A and 31B are a cross-sectional view and a circuit diagram showing a structural example of a touch sensor;

[0051] FIG. 32 is a cross-sectional view illustrating one embodiment of a transistor;

[0052] FIG. 33 is a block diagram showing a structural example of a liquid crystal display device;

[0053] FIG. 34 is a timing chart showing one example of a method for driving a liquid crystal display device;

[0054] FIG. 35 is a graph showing valence band spectra obtained by HAXPES measurement;

[0055] FIGS. 36A and 36B are diagrams each illustrating a structure used in calculation of a band structure;

[0056] FIG. 37 is a diagram showing the results of calculation of band structures;

[0057] FIGS. 38A to 38C are schematic views of oxide semiconductor films and diagrams each illustrating the band structure in the oxide semiconductor film;

[0058] FIG. 39 is a diagram showing the results of calculation of band structures; and

[0059] FIG. 40 is a graph showing change of height of an energy barrier with respect to a channel length.

DETAILED DESCRIPTION OF THE INVENTION

[0060] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description and it is easily understood by those skilled in the art that the mode and details can be variously changed without departing from the scope and spirit of the present invention. Therefore, the present invention should not be construed as being limited to the description in the following embodiments and examples. In addition, in the following embodiments and examples, the same portions or portions having similar functions are denoted by the same reference numerals or the same hatching patterns in different drawings, and description thereof will not be repeated.

[0061] Note that in each drawing described in this specification, the size, the film thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, embodiments of the present invention are not necessarily limited to such scales.

[0062] Note that terms such as “first”, “second”, and “third” in this specification are used in order to avoid confusion among components, and the terms do not limit the components numerically. Therefore, for example, description can be made even when “first” is replaced with “second” or “third”, as appropriate.

[0063] Functions of a “source” and a “drain” are sometimes replaced with each other when the direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be used to denote the drain and the source, respectively, in this specification.

[0064] Note that a voltage refers to a difference between electric potentials of two points, and an electric potential refers to electrostatic energy (electric potential energy) of a unit charge at a given point in an electrostatic field. Note that in general, a difference between an electric potential of one point and a reference electric potential is merely called an electric potential or a voltage, and an electric potential and a voltage are used as synonymous words in many cases. Thus, in this specification, an electric potential may be rephrased as a voltage and a voltage may be rephrased as an electric potential unless otherwise specified.

[0065] In this specification, in the case where an etching step is performed after a photolithography step, a mask formed in the photolithography step is removed after the etching step.

(Embodiment 1)

[0066] In this embodiment, a semiconductor device which is one embodiment of the present invention and a manufacturing method thereof are described with reference to drawings.

[0067] In a transistor including an oxide semiconductor film, oxygen vacancies are given as an example of a defect which leads to poor electrical characteristics of the transistor. For example, the threshold voltage of a transistor including an oxide semiconductor film which contains oxygen vacancies in the film easily shifts in the negative direction, and such a transistor tends to have normally-on characteristics. This is because electric charges are generated owing to oxygen vacancies in the oxide semiconductor film and the resistance is thus reduced. The transistor having normally-on characteristics causes various problems in that malfunction is likely to be caused when in operation and that power consumption is increased when not in operation, for example. Further, there is a problem in that the amount of change in electrical characteristics, typically in threshold voltage, of the transistor is increased by change over time or a stress test.

[0068] One of the factors in generating oxygen vacancies is damage caused in a manufacturing process of a transistor. For example, when an insulating film or the like is formed over an oxide semiconductor film by a plasma CVD method, the oxide semiconductor film might be damaged depending on formation conditions thereof.

[0069] Further, not only oxygen vacancies but also impurities such as silicon or carbon which is a constituent element of the insulating film cause poor electrical characteristics of a transistor. Therefore, there is a problem in that mixing of the impurities into an oxide semiconductor film reduces the resistance of the oxide semiconductor film and the amount of change in electrical characteristics, typically in threshold voltage, of the transistor is increased by change over time or a stress test.

[0070] Thus, an object of this embodiment is to reduce oxygen vacancies in an oxide semiconductor film having a channel region and the concentration of impurities in the oxide semiconductor film, in a semiconductor device including a transistor having the oxide semiconductor film.

[0071] A top view and cross-sectional views of a transistor 50 included in a semiconductor device are shown in FIGS. 1A to 1C. FIG. 1A is a top view of the transistor 50, FIG. 1B is a cross-sectional view taken along dashed-dotted line A-B in FIG. 1A, and FIG. 1C is a cross-sectional view taken along dashed-dotted line C-D in FIG. 1A. Note that in FIG. 1A, a substrate 11, a gate insulating film 17, an oxide insulating film 24, a nitride insulating film 25, and the like are omitted for simplicity.

[0072] The transistor 50 shown in FIGS. 1B and 1C includes a gate electrode 15 provided over the substrate 11. Further, the gate insulating film 17 is formed over the substrate 11 and the gate electrode 15, and a multilayer film 20 overlapping with the gate electrode 15 with the gate insulating film 17 provided therebetween, and a pair of electrodes 21 and 22 in contact with the multilayer film 20 are included. Furthermore, a protective film 26 including the oxide insulating film 24 and the nitride insulating film 25 is formed over the gate insulating film 17, the multilayer film 20, and the pair of electrodes 21 and 22.

[0073] In the transistor 50 described in this embodiment, the multilayer film 20 includes an oxide semiconductor film 18 and an oxide film 19 containing In or Ga. Further, part of the oxide semiconductor film 18 serves as a channel region. Furthermore, the oxide insulating film 24 is formed in contact with the multilayer film 20. That is, the oxide film 19 containing In or Ga is provided between the oxide semiconductor film 18 and the oxide insulating film 24.

[0074] The oxide semiconductor film 18 is typically In—Ga oxide, In—Zn oxide, or In-M-Zn oxide (M represents Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf).

[0075] Note that when the oxide semiconductor film 18 is In-M-Zn oxide, the proportions of In and M are preferably as follows: the proportion of In atoms be higher than or equal to 25 atomic % and the proportion of M atoms be lower than 75 atomic %, and it is further preferably as follows: the proportion of In atoms be higher than or equal to 34 atomic % and the proportion of M atoms be lower than 66 atomic %.

[0076] The energy gap of the oxide semiconductor film 18 is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. With the use of an oxide semiconductor having such a wide energy gap, the off-state current of the transistor 50 can be reduced.

[0077] The thickness of the oxide semiconductor film 18 is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, more preferably greater than or equal to 3 nm and less than or equal to 50 nm.

[0078] The oxide film 19 containing In or Ga is typically In—Ga oxide, In—Zn oxide, or In-M-Zn oxide (M represents Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf). The energy at the conduction band bottom thereof is closer to a vacuum level than that of the oxide semiconductor film 18, and typically, the difference between the energy at the conduction band bottom of the oxide film 19 containing In or Ga and the energy at the conduction band bottom of the oxide semiconductor film 18 is greater than or equal to 0.05 eV, greater than or equal to 0.07 eV, greater than or equal to 0.1 eV, or greater than or equal to 0.15 eV and also less than or equal to 2 eV, less than or equal to 1 eV, less than or equal to 0.5 eV, or less than or equal to 0.4 eV. That is, the difference between the electron affinity of the oxide film 19 containing In or Ga and the electron affinity of the oxide semiconductor film 18 is greater than or equal to 0.05 eV, greater than or equal to 0.07 eV, greater than or equal to 0.1 eV, or greater than or equal to 0.15 eV and also less than or equal to 2 eV, less than or equal to 1 eV, less than or equal to 0.5 eV, or less than or equal to 0.4 eV.

[0079] When the oxide film 19 containing In or Ga is In-M-Zn oxide, the proportions of In and M are preferably as follows: the proportion of In atoms be lower than 50 atomic % and the proportion of M atoms be higher than or equal to 50 atomic %, and it is further preferably as follows: the proportion of In atoms be lower than 25 atomic % and the proportion of M atoms be higher than or equal to 75 atomic %.

[0080] Further, in the case where each of the oxide semiconductor film 18 and the oxide film 19 containing In or Ga is In-M-Zn oxide (M represents Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf), the proportion of M atoms (M represents Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) in the oxide film 19 containing In or Ga is higher than that in the oxide semiconductor film 18. Typically, the proportion of M in each of the films is 1.5 or more times, preferably twice or more, more preferably three or more times as high as that in the oxide semiconductor film 18.

[0081] Furthermore, in the case where each of the oxide semiconductor film 18 and the oxide film 19 containing In or Ga is In-M-Zn-based oxide (M represents Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf), when In:M:Zn=x₁:y₁:z₁[atomic ratio] is satisfied in the oxide semiconductor film 18 and In:M:Zn=x₂:y₂:z₂[atomic ratio] is satisfied in the oxide film 19 containing In or Ga, y₁/x₁is higher than y₂/x₂. It is preferable that y₁/x₁be 1.5 or more times as high as y₂/x₂. It is further preferable that y₁/x₁be twice or more as high as y₂/x₂. It is still further preferable that y₁/x₁be three or more times as high as y₂/x₂. In this case, it is preferable that in the oxide semiconductor film, y₂be higher than or equal to x₂because a transistor including the oxide semiconductor film can have stable electric characteristics. However, when y₂is larger than or equal to three or more times x₂, the field-effect mobility of the transistor including the oxide semiconductor film is reduced. Thus, it is preferable that y₂be higher than or equal to x₂or lower than three times x₂.

[0082] For example, as the oxide semiconductor film 18, an In—Ga—Zn oxide with an atomic ratio of In:Ga:Zn=1:1:1 or 3:1:2 can be used. Further, as the oxide film 19 containing In or Ga, an In—Ga—Zn oxide with an atomic ratio of In:Ga:Zn=1:3:2, 1:6:4, or 1:9:6 can be used. Note that a proportion of each atom in the atomic ratio of the oxide semiconductor film 18 and the oxide film 19 containing In or Ga varies within a range of ±20% as an error.

[0083] Note that, without limitation to those described above, a material with an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (e.g., field-effect mobility and threshold voltage) of a transistor. Further, in order to obtain required semiconductor characteristics of a transistor, it is preferable that the carrier density, the impurity concentration, the defect density, the atomic ratio of a metal element to oxygen, the interatomic distance, the density, and the like of the oxide semiconductor film 18 be set to be appropriate.

[0084] The oxide film 19 containing In or Ga also serves as a film which relieves damage to the oxide semiconductor film 18 at the time of forming the oxide insulating film 24 later.

[0085] The thickness of the oxide film 19 containing In or Ga is greater than or equal to 3 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm.

[0086] When silicon or carbon, which is one of elements belonging to Group 14, is contained in the oxide semiconductor film 18, the number of oxygen vacancies is increased, and the oxide semiconductor film 18 becomes an n-type film. Thus, the concentration of silicon or carbon in the oxide semiconductor film 18 or the concentration of silicon or carbon in the vicinity of an interface between the oxide film 19 containing In or Ga and the oxide semiconductor film 18 is adjusted to be lower than or equal to 2×10¹⁸atoms/cm³, preferably lower than or equal to 2×10¹⁷atoms/cm³.

[0087] Further, the crystal structure of each of the oxide semiconductor film 18 and the oxide film 19 containing In or Ga may be an amorphous structure, a single-crystal structure, a polycrystalline structure, a microcrystalline structure, a mixed structure in which crystal grains are dispersed in an amorphous region, or a c-axis aligned crystalline oxide semiconductor (CAAC-OS) which is described later. In the microcrystalline structure, the plane orientations of crystal grains are random. The grain size of a crystal grain contained in the microcrystalline structure or the mixed structure is greater than or equal to 0.1 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 10 nm, and more preferably greater than or equal to 2 nm and less than or equal to 4 nm. Note that when the crystal structure of at least the oxide semiconductor film 18 is CAAC-OS, the amount of change in electrical characteristics due to irradiation with visible light or ultraviolet light can be further reduced.

[0088] Furthermore, in the transistor 50 described in this embodiment, the oxide insulating film 24 is formed in contact with the multilayer film 20.

[0089] The oxide insulating film 24 is formed in contact with the multilayer film 20. The oxide insulating film 24 is an oxide insulating film containing more oxygen than that in the stoichiometric composition. Part of oxygen is released by heating from the oxide insulating film containing more oxygen than that in the stoichiometric composition. The oxide insulating film containing more oxygen than that in the stoichiometric composition is an oxide insulating film of which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×10¹⁸atoms/cm³, preferably greater than or equal to 3.0×10²⁰atoms/cm³in TDS analysis.

[0090] A silicon oxide film, a silicon oxynitride film, or the like with a thickness greater than or equal to 30 nm and less than or equal to 500 nm, preferably greater than or equal to 50 nm and less than or equal to 400 nm can be used as the oxide insulating film 24.

[0091] Further, it is preferable that the number of defects in the oxide insulating film 24 be small, typically the spin density of a signal which appears at g=2.001 originating from a dangling bond of silicon, be lower than 1.5×10¹⁸spins/cm³, more preferably lower than or equal to 1×10¹⁸spins/cm³by ESR measurement.

[0092] Here, the band structure along dashed-dotted line E-F in the vicinity of the multilayer film 20 of FIG. 1B is described with reference to FIG. 2A, and the flow of carrier in the transistor 50 is described with reference to FIGS. 2B and 2C.

[0093] In the band structure shown in FIG. 2A, for example, In—Ga—Zn oxide (the atomic ratio of a sputtering target used for film formation is In:Ga:Zn=1:1:1) with an energy gap of 3.15 eV is used for the oxide semiconductor film 18. In—Ga—Zn oxide (the atomic ratio of a sputtering target used for film formation is In:Ga:Zn=1:3:2) with an energy gap of 3.5 eV is used for the oxide film 19 containing In or Ga. Note that the energy gap can be measured using a spectroscopic ellipsometer.

[0094] The energy difference between the vacuum level and the valence band top (also referred to as ionization potential) of the oxide semiconductor film 18 and the energy difference therebetween of the oxide film 19 containing In or Ga are 7.9 eV and 8.0 eV, respectively. Note that the energy difference between the vacuum level and the valence band top can be measured using an ultraviolet photoelectron spectroscopy (UPS) device (VersaProbe manufactured by ULVAC-PHI, Inc.).

[0095] The energy difference between the vacuum level and the conduction band bottom (also referred to as electron affinity) of the oxide semiconductor film 18 and the energy difference therebetween of the oxide film 19 containing In or Ga are 4.7 eV and 4.5 eV, respectively.

[0096] Further, the conduction band bottom of the oxide semiconductor film 18 is denoted by Ec_18, and the conduction band bottom of the oxide film 19 containing In or Ga is denoted by Ec_19. Further, the conduction band bottom of the gate insulating film 17 is denoted by Ec_17, and the conduction band bottom of the oxide insulating film 24 is denoted by Ec_24.

[0097] As shown in FIG. 2A, in the multilayer film 20, the conduction band bottom in the vicinity of the interface between the oxide semiconductor film 18 and the oxide film 19 containing In or Ga varies continuously. That is, there is no barrier in the vicinity of the interface between the oxide semiconductor film 18 and the oxide film 19 containing In or Ga, and the conduction band bottom smoothly varies. Such a shape is caused by mutual transfer of oxygen between the oxide semiconductor film 18 and the oxide film 19 containing In or Ga. Further, in the multilayer film 20, the energy of the conduction band bottom of the oxide semiconductor film 18 is the lowest, and this region serves as a channel region.

[0098] Now, a state where electrons serving as carrier flow in the transistor is described with reference to FIGS. 2B and 2C. Note that in FIGS. 2B and 2C, the amount of electrons flowing in the oxide semiconductor film 18 is represented by a size of a dotted arrow.

[0099] In the vicinity of the interface between the oxide film 19 containing In or Ga and the oxide insulating film 24, trap levels 27 are formed by an impurity and defects. Thus, for example, in the case where a channel region of the transistor is formed with a single layer of the oxide semiconductor film 18 as illustrated in FIG. 2B, in the oxide semiconductor film 18, electrons serving as carrier flows mainly in the gate insulating film 17 side, but a small amount of electrons also flow on the oxide insulating film 24 side. As a result, part of electrons flowing on the oxide semiconductor film 18 is captured by the trap levels 27.

[0100] On the other hand, in the transistor 50 described in this embodiment, the oxide film 19 containing In or Ga is provided between the oxide semiconductor film 18 and the oxide insulating film 24 as illustrated in FIG. 2C; thus, there is a distance between the oxide semiconductor film 18 and the trap levels 27. As a result, electrons flowing in the oxide semiconductor film 18 are less likely to be captured by the trap levels 27. When the electrons are captured by the trap levels, the electrons become negative fixed charges. As a result, a threshold voltage of the transistor varies. However, by the distance between the oxide semiconductor film 18 and the trap levels 27, capture of the electrons by the trap levels 27 can be reduced, and accordingly a variation of the threshold voltage can be reduced.

[0101] Note that when the energy difference ΔE1 of the conduction band bottom in the vicinity of the interface between the oxide semiconductor film 18 and the oxide film 19 containing In or Ga is small, carrier flowing in the oxide semiconductor film 18 transcends the conduction band bottom of the oxide film 19 containing In or Ga and is captured by the trap levels 27. Thus, the energy difference ΔE1 between the conduction band bottom Ec_18 of the oxide semiconductor film 18 and the conduction band bottom Ec_19 of the oxide film 19 containing In or Ga is greater than or equal to 0.1 eV, preferably greater than or equal to 0.15 eV.

[0102] Further, the oxide insulating film 24 (see FIG. 1B) containing more oxygen than that in the stoichiometric composition is provided on the back channel side of the multilayer film 20 (a surface of the multilayer film 20, which is opposite to a surface facing the gate electrode 15). Therefore, oxygen contained in the oxide insulating film 24 containing more oxygen than that in the stoichiometric composition can be moved to the oxide semiconductor film 18 included in the multilayer film 20, whereby oxygen vacancies in the oxide semiconductor film 18 can be reduced.

[0103] From the above, oxygen vacancies in the multilayer film 20 can be reduced by providing the multilayer film 20 including the oxide semiconductor film 18 and the oxide film 19 containing In or Ga, and the oxide insulating film 24 containing more oxygen than that in the stoichiometric composition over the multilayer film 20. Further, by providing the oxide film 19 containing In or Ga between the oxide semiconductor film 18 and the oxide insulating film 24, the concentration of silicon or carbon in the oxide semiconductor film 18 or in the vicinity of the interface between the oxide film 19 containing In or Ga and the oxide semiconductor film 18 can be reduced.

[0104] Consequently, in the multilayer film 20, the absorption coefficient derived from a constant photocurrent method is lower than 1×10⁻³/cm, preferably lower than 1×10⁻⁴/cm. The absorption coefficient has a positive correlation with an energy corresponding to the localized levels originating from oxygen vacancies and entry of impurities (calculated from a wavelength); thus, the density of localized levels in the multilayer film 20 is extremely low.

[0105] Note that the absorption coefficient which is called an Urbach tail due to the band tail is removed from a curve of the absorption coefficient obtained by the CPM measurement, whereby the absorption coefficient due to the localized levels can be calculated from the following formula. Note that the Urbach tail indicates a constant gradient region on a curve of the absorption coefficient obtained by the CPM measurement, and the gradient is called Urbach energy.

[0106]

\begin{matrix} \int \frac{α (E) - α_{u}}{E} ⅆ E & [FORMULA 1] \end{matrix}

[0107] Here, α(E) indicates the absorption coefficient at each energy level and α_uindicates the absorption coefficient due to the Urbach tail.

[0108] Since the transistor 50 having such a structure includes very few defects in the multilayer film 20 including the oxide semiconductor film 18, the electrical characteristics of the transistor can be improved. Further, in a BT stress test and a BT photostress test which are examples of a stress test, the threshold voltage does not change or changes in the positive direction or the negative direction and the amount of the change is less than or equal to 1.0 V, preferably less than or equal to 0.5 V, and thus, reliability is high.

[0109] Here, electrical characteristics of a transistor having a small amount of change in threshold voltage in a BT stress test and a BT photostress test are described with reference to FIG. 1D.

[0110] The BT stress test is one kind of accelerated test and can evaluate, in a short time, change in characteristics (i.e., change over time) of transistors, which is caused by long-term use. In particular, the amount of change in threshold voltage of the transistor between before and after the BT stress test is an important indicator when examining the reliability of the transistor. If the amount of change in the threshold voltage between before and after the BT stress test is small, the transistor has higher reliability.

[0111] Next, a specific method of the BT stress test is described. First, initial characteristics of the transistor are measured. Next, the temperature of the substrate over which the transistor is formed (substrate temperature) is set at fixed temperature, the pair of electrodes serving as a source and a drain of the transistor are set at a same electric potential, and the gate electrode is supplied for a certain period with an electric potential different from that of the pair of electrodes serving as a source and a drain. The substrate temperature may be determined as appropriate in accordance with the test purpose. Then, the substrate temperature is set at a temperature similar to that of a temperature when the initial characteristics are measured, and electrical characteristics of the transistor are measured again. As a result, a difference between the threshold voltage in the initial characteristics and the threshold voltage after the BT stress test can be obtained as the amount of change in the threshold voltage.

[0112] Note that the test in the case where the electric potential applied to the gate electrode is higher than the electric potential of the source and the drain is referred to as a positive BT stress test, and the test in the case where the electric potential applied to the gate electrode is lower than the electric potential of the source and the drain is referred to as a negative BT stress test. A BT stress test with light irradiation is referred to as a BT photostress test. The test in the case where light irradiation is performed and the electric potential applied to the gate electrode is higher than the electric potential of the source and the drain is referred to as a positive BT photostress test, and the test in the case where light irradiation is performed and the electric potential applied to the gate electrode is lower than the electric potential of the source and the drain is referred to as a negative BT photostress test.

[0113] The stress conditions for the BT stress test can be determined by setting the substrate temperature, the electric field intensity applied to the gate insulating film, and the time period of application of an electric field. The intensity of the electric field applied to the gate insulating film is determined in accordance with a value obtained by dividing an electric potential difference between the gate, and the source and the drain by the thickness of the gate insulating film. For example, in the case where the intensity of the electric field applied to a 100-nm-thick gate insulating film is to be 3 MV/cm, the electric potential difference between the gate electrode, and the source and the drain can be set to 30 V.

[0114] FIG. 1D shows electrical characteristics of the transistor, and the horizontal axis indicates the gate voltage (Vg) and the vertical axis indicates the drain current (Id). A dashed line 41 denotes the initial characteristics of the transistor, and a solid line 43 denotes the electrical characteristics of the transistor after the BT stress test. In the transistor described in this embodiment, the amount of change in threshold voltage in the dashed line 41 and the solid line 43 is 0 V or the amount of change in the positive direction or the negative direction is less than or equal to 1.0 V, preferably less than or equal to 0.5 V. Therefore, in the transistor described in this embodiment, the amount of change in the threshold voltage after the BT stress test is small. As a result, it is apparent that the transistor 50 described in this embodiment has high reliability.

[0115] Note that a transistor including an oxide semiconductor film is an n-channel transistor; therefore, in this specification, a transistor which can be regarded as having no drain current flowing therein when a gate voltage is 0 V is defined as a transistor having normally-off characteristics. In contrast, a transistor which can be regarded as having a drain current flowing therein when a gate voltage is 0 V is defined as a transistor having normally-on characteristics.

[0116] Further, in this specification, in a curve (not shown) where the horizontal axis indicates the gate voltage (Vg [V]) and the vertical axis indicates the square root of drain current (Id^1/2[A]), the threshold voltage (Vth) is defined as a gate voltage at a point of intersection of an extrapolated tangent line of Id^1/2having the highest inclination with the Vg axis.

[0117] Other details of the transistor 50 are described below.

[0118] There is no particular limitation on a material and the like of the substrate 11 as long as the material has heat resistance high enough to withstand at least heat treatment performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate may be used as the substrate 11. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium or the like, an SOI substrate, or the like may be used. Still alternatively, any of these substrates provided with a semiconductor element may be used as the substrate 11.

[0119] Alternatively, a flexible substrate may be used as the substrate 11, and the transistor 50 may be provided directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 11 and the transistor 50. The separation layer can be used when part or the whole of a semiconductor device formed over the separation layer is completed and separated from the substrate 11 and transferred to another substrate. In such a case, the transistor 50 can be transferred to a substrate having low heat resistance or a flexible substrate as well.

[0120] The gate electrode 15 can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of these metal elements as a component; an alloy containing any of these metal elements in combination; or the like. Further, one or more metal elements selected from manganese or zirconium may be used. The gate electrode 15 may have a single-layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, and the like can be given. Alternatively, an alloy film or a nitride film which contains aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

[0121] Further, the gate electrode 15 can be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added. It is also possible to have a stacked-layer structure formed using the above light-transmitting conductive material and the above metal element.

[0122] Further, an In—Ga—Zn-based oxynitride semiconductor film, an In—Sn-based oxynitride semiconductor film, an In—Ga-based oxynitride semiconductor film, an In—Zn-based oxynitride semiconductor film, a Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a film of a metal nitride (such as InN or ZnN), or the like may be provided between the gate electrode 15 and the gate insulating film 17. These films each have a work function higher than or equal to 5 eV, preferably higher than or equal to 5.5 eV, which is higher than the electron affinity of an oxide semiconductor; thus, the threshold voltage of a transistor including the oxide semiconductor can be shifted in the positive direction, and accordingly, a switching element having what is called normally-off characteristics can be obtained. For example, in the case of using an In—Ga—Zn-based oxynitride semiconductor film, an In—Ga—Zn-based oxynitride semiconductor film having a higher nitrogen concentration than at least the oxide semiconductor film 18, specifically, an In—Ga—Zn-based oxynitride semiconductor film having a nitrogen concentration of higher than or equal to 7 atomic % is used.

[0123] The gate insulating film 17 can be formed to have a single-layer structure or a stacked-layer structure using, for example, any of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn-based metal oxide, and silicon nitride. Further, as shown in FIG. 32, the gate insulating film 17 can be formed to have a stacked-layer structure of a gate insulating film 17a and a gate insulating film 17b, and an oxide insulating film from which oxygen is released by heating may be used for the gate insulating film 17b in contact with the multilayer film 20. With the use of a film from which oxygen is released by heating as the gate insulating film 17b, density of interface states at the interface between the oxide semiconductor film 18 and the gate insulating film 17 can be reduced; accordingly, a transistor with less deterioration in electrical characteristics can be obtained. Further, it is possible to prevent outward diffusion of oxygen from the oxide semiconductor film 18 and entry of hydrogen, water, or the like into the oxide semiconductor film 18 from the outside by providing an insulating film having a blocking effect against oxygen, hydrogen, water, and the like as the gate insulating film 17a. The insulating film having a blocking effect against oxygen, hydrogen, water, and the like is formed using aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like.

[0124] The gate insulating film 17 may be formed using a high-k material such as hafnium silicate (HfSiO_x), hafnium silicate to which nitrogen is added (HfSi_xO_yN_z), hafnium aluminate to which nitrogen is added (HfAl_xO_yN_z), hafnium oxide, or yttrium oxide, so that gate leakage current of the transistor can be reduced.

[0125] The thickness of the gate insulating film 17 may be greater than or equal to 5 nm and less than or equal to 400 nm, preferably greater than or equal to 10 nm and less than or equal to 300 nm, more preferably greater than or equal to 50 nm and less than or equal to 250 nm.

[0126] The pair of electrodes 21 and 22 is formed to have a single-layer structure or a stacked-layer structure including, as a conductive material, any of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten or an alloy containing any of these metals as its main component. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a tungsten film, a two-layer structure in which a copper film is formed over a copper-magnesium-aluminum alloy film, a three-layer structure in which a titanium film or a titanium nitride film, an aluminum film or a copper film, and a titanium film or a titanium nitride film are stacked in this order, a three-layer structure in which a molybdenum film or a molybdenum nitride film, an aluminum film or a copper film, and a molybdenum film or a molybdenum nitride film are stacked in this order, and the like can be given. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0127] Further, it is possible to prevent outward diffusion of oxygen from the multilayer film 20 and entry of hydrogen, water, or the like into the multilayer film 20 from the outside by providing the nitride insulating film 25 having a blocking effect against oxygen, hydrogen, water, and the like over the oxide insulating film 24. The nitride insulating film is formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like. Note that instead of the nitride insulating film having a blocking effect against oxygen, hydrogen, water, and the like, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like, may be provided. As the oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, an yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, and a hafnium oxynitride film can be given.

[0128] Next, a method for manufacturing the transistor 50 shown in FIGS. 1A to 1D is described with reference to FIGS. 3A to 3D.

[0129] As shown in FIG. 3A, the gate electrode 15 is formed over the substrate 11, and the gate insulating film 17 is formed over the gate electrode 15.

[0130] Here, a glass substrate can be used as the substrate 11.

[0131] A method for forming the gate electrode 15 is described below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, or the like, and a mask is formed over the conductive film by a photolithography process. Next, part of the conductive film is etched with the use of the mask to form the gate electrode 15. After that, the mask is removed.

[0132] Note that the gate electrode 15 may be formed by an electrolytic plating method, a printing method, an inkjet method, or the like instead of the above formation method.

[0133] Here, a 100-nm-thick tungsten film is formed by a sputtering method. Next, a mask is formed by a photolithography process, and the tungsten film is subjected to dry etching with the use of the mask to form the gate electrode 15.

[0134] The gate insulating film 17 is formed by a sputtering method, a CVD method, an evaporation method, or the like.

[0135] In the case where a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film is formed as the gate insulating film 17, a deposition gas containing silicon and an oxidizing gas are preferred to be used as source gases. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. As the oxidizing gas, oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, and the like can be given as examples.

[0136] In the case where a silicon nitride film is formed as the gate insulating film 17, it is preferable to use a two-step formation method. First, a first silicon nitride film with few defects is formed by a plasma CVD method in which a mixed gas of silane, nitrogen, and ammonia is used as a source gas. Then, a second silicon nitride film in which the hydrogen concentration is low and hydrogen can be blocked is formed by switching the source gas to a mixed gas of silane and nitrogen. With such a formation method, a silicon nitride film with few defects and a blocking property against hydrogen can be formed as the gate insulating film 17.

[0137] Moreover, in the case of forming a gallium oxide film as the gate insulating film 17, a metal organic chemical vapor deposition (MOCVD) method can be employed.

[0138] Next, as shown in FIG. 3B, the oxide semiconductor film 18 and the oxide film 19 containing In or Ga are formed over the gate insulating film 17.

[0139] Methods for forming the oxide semiconductor film 18 and the oxide film 19 containing In or Ga are described below. An oxide semiconductor film which is to be the oxide semiconductor film 18 and an oxide film containing In or Ga which is to be the oxide film 19 containing In or Ga are successively formed over the gate insulating film 17. Next, after a mask is formed over the oxide film containing In or Ga by a photolithography process, the oxide semiconductor film and the oxide film containing In or Ga are partly etched with the use of the mask; thus, as shown in FIG. 3B, the multilayer film 20 which is subjected to element isolation and includes the oxide semiconductor film 18 and the oxide film 19 containing In or Ga is formed over the gate insulating film 17 so as to overlap with part of the gate electrode 15. After that, the mask is removed.

[0140] The oxide semiconductor film which is to be the oxide semiconductor film 18 and the oxide film containing In or Ga which is to be the oxide film 19 containing In or Ga can be formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, or the like.

[0141] In the case where the oxide semiconductor film and the oxide film containing In or Ga are formed by a sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be used as appropriate as a power supply device for generating plasma.

[0142] As a sputtering gas, a rare gas (typically argon), an oxygen gas, or a mixed gas of a rare gas and oxygen is used as appropriate. In the case of using the mixed gas of a rare gas and oxygen, the proportion of oxygen is preferably higher than that of a rare gas.

[0143] Further, a target may be selected as appropriate in accordance with the composition of the oxide semiconductor film and the oxide film containing In or Ga to be formed.

[0144] Note that, for example, when a sputtering method is used to form the oxide semiconductor film and the oxide film containing In or Ga, the oxide semiconductor film and the oxide film containing In or Ga are formed while heating at a substrate temperature higher than or equal to 150° C. and lower than or equal to 500° C., preferably higher than or equal to 150° C. and lower than or equal to 450° C., more preferably higher than or equal to 200° C. and lower than or equal to 350° C., whereby a CAAC-OS film which is described later can be formed.

[0145] The oxide semiconductor film and the oxide film containing In or Ga are not simply stacked but formed to have a continuous energy band (to have a structure in which the energy at the conduction band bottom varies continuously across the films). In other words, a stacked structure in which a defect level such as a trap center or a recombination center or an impurity which forms a barrier blocking the flow of carrier does not exist at the interface between the films is formed. If an impurity exists between the oxide semiconductor film and the oxide film containing In or Ga which are stacked, a continuity of the energy band is damaged, and the carrier is captured or recombined at the interface and then disappears.

[0146] In order to form such a continuous energy band, it is necessary to form films continuously without being exposed to air, with use of a multi-chamber deposition apparatus (sputtering apparatus) including a load lock chamber. Each chamber in the sputtering apparatus is preferably evacuated to be a high vacuum state (to the degree of about 1×10⁻⁴Pa to 5×10⁻⁷Pa) with an adsorption vacuum evacuation pump such as a cryopump in order to remove water or the like, which serves as an impurity against the oxide semiconductor film, as much as possible. Alternatively, a turbo molecular pump and a cold trap are preferably combined so as to prevent a backflow of a gas from an exhaust system to the inside of the chamber.

[0147] In order to obtain a highly purified intrinsic oxide semiconductor film, besides the high vacuum evacuation of the chamber, a highly purification of a sputtering gas is also needed. As an oxygen gas or an argon gas used for a sputtering gas, a gas which is highly purified to have a dew point of −40° C. or lower, preferably −80° C. or lower, further preferably −100° C. or lower is used, whereby entry of moisture or the like into the oxide semiconductor film can be prevented as much as possible.

[0148] Here, a 35-nm-thick In—Ga—Zn oxide film (the atomic ratio of a sputtering target used for film formation is In:Ga:Zn=1:1:1) is formed as the oxide semiconductor film by a sputtering method, and then, a 20-nm-thick In—Ga—Zn oxide film (the atomic ratio of a sputtering target used for film formation is In:Ga:Zn=1:3:2) is formed as the oxide film containing In or Ga by a sputtering method. Next, a mask is formed over the oxide film containing In or Ga, and the oxide semiconductor film and the oxide film containing In or Ga are partly and selectively etched to form the multilayer film 20 including the oxide semiconductor film 18 and the oxide film 19 containing In or Ga.

[0149] After that, heat treatment may be performed.

[0150] Next, as shown in FIG. 3C, the pair of electrodes 21 and 22 is formed.

[0151] A method for forming the pair of electrodes 21 and 22 is described below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, or the like. Then, a mask is formed over the conductive film by a photolithography process. Next, the conductive film is etched with the use of the mask to form the pair of electrodes 21 and 22. After that, the mask is removed.

[0152] Here, a 50-nm-thick tungsten film, a 400-nm-thick aluminum film, and a 100-nm-thick titanium film are sequentially stacked by a sputtering method. Next, a mask is formed over the titanium film by a photolithography process and the tungsten film, the aluminum film, and the titanium film are dry-etched with use of the mask to form the pair of electrodes 21 and 22.

[0153] Next, as shown in FIG. 3D, the oxide insulating film 24 is formed over the multilayer film 20 and the pair of electrodes 21 and 22.

[0154] Note that after the pair of electrodes 21 and 22 is formed, the oxide insulating film 24 is preferably formed in succession without exposure to the air. After the pair of electrodes 21 and 22 is formed, the oxide insulating film 24 is formed in succession by adjusting at least one of the flow rate of the source gas, the pressure, the high-frequency power, and the substrate temperature without exposure to the atmosphere, whereby the concentration of impurities originating from the atmosphere at the interface between the oxide film 19 containing In or Ga and the oxide insulating film 24 can be reduced and further oxygen contained in the oxide insulating film 24 can be moved to the oxide semiconductor film 18; accordingly, the amount of oxygen vacancies in the oxide semiconductor film 18 can be reduced.

[0155] As the oxide insulating film 24, a silicon oxide film or a silicon oxynitride film is formed under the following conditions: the substrate placed in a treatment chamber of the plasma CVD apparatus, which is vacuum-evacuated, is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C., more preferably higher than or equal to 200° C. and lower than or equal to 240° C., the pressure is greater than or equal to 100 Pa and less than or equal to 250 Pa, preferably greater than or equal to 100 Pa and less than or equal to 200 Pa with introduction of a source gas into the treatment chamber, and high-frequency power higher than or equal to 0.17 W/cm²and lower than or equal to 0.5 W/cm², preferably higher than or equal to 0.25 W/cm²and lower than or equal to 0.35 W/cm²is supplied to an electrode provided in the treatment chamber.

[0156] A deposition gas containing silicon and an oxidizing gas can be used as the source gases of the oxide insulating film 24. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. As the oxidizing gas, oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, and the like can be given as examples.

[0157] As the film formation conditions of the oxide insulating film 24, the high-frequency power having the above power density is supplied to the treatment chamber having the above pressure, whereby the degradation efficiency of the source gas in plasma is increased, oxygen radicals are increased, and oxidation of the source gas is promoted; therefore, the oxygen content in the oxide insulating film 24 becomes higher than that in the stoichiometric composition. However, in the case where the substrate temperature is the above-described temperature, the bonding strength between silicon and oxygen is low, and accordingly, part of oxygen is released by heating. Thus, it is possible to form an oxide insulating film which contains more oxygen than that in the stoichiometric composition and from which part of oxygen is released by heating. Further, the oxide film 19 containing In or Ga serves as a protective film of the oxide semiconductor film 18. Consequently, the oxide insulating film 24 can be formed using the high-frequency power having a high power density while damage to the oxide semiconductor film 18 is reduced.

[0158] Note that in the film formation conditions of the oxide insulating film 24, the flow rate of the deposition gas containing silicon relative to the oxidizing gas can be increased, whereby the number of defects in the oxide insulating film 24 can be reduced. Typically, it is possible to form an oxide insulating film in which the number of defects is small, i.e. the spin density of a signal which appears at g=2.001 originating from a dangling bond of silicon, be lower than 6×10¹⁷spins/cm³, preferably lower than or equal to 3×10¹⁷spins/cm³, more preferably lower than or equal to 1.5×10¹⁷spins/cm³by ESR measurement. As a result, the reliability of the transistor can be improved.

[0159] Here, as the oxide insulating film 24, a 400-nm-thick silicon oxynitride film is formed by a plasma CVD method in which silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 4000 sccm are used as the source gases, the pressure in the treatment chamber is 200 Pa, the substrate temperature is 220° C., and the high-frequency power of 1500 W is supplied to the parallel plate electrodes with the use of a 27.12 MHz high-frequency power source. Note that the plasma CVD apparatus is a parallel plate plasma CVD apparatus in which the electrode area is 6000 cm², and the power per unit area (power density) into which the supplied power is converted is 0.25 W/cm².

[0160] Next, heat treatment is performed. The temperature of the heat treatment is typically higher than or equal to 150° C. and lower than the strain point of the substrate, preferably higher than or equal to 200° C. and lower than or equal to 450° C., more preferably higher than or equal to 300° C. and lower than or equal to 450° C.

[0161] An electric furnace, an RTA apparatus, or the like can be used for the heat treatment. With the use of an RTA apparatus, the heat treatment can be performed at a temperature of higher than or equal to the strain point of the substrate if the heating time is short. Therefore, the heat treatment time can be shortened.

[0162] The heat treatment may be performed under an atmosphere of nitrogen, oxygen, ultra-dry air (air in which a water content is 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a rare gas (argon, helium, or the like). Note that the nitrogen, the oxygen, the ultra-dry air, or the rare gas preferably does not contain hydrogen, water, and the like.

[0163] By the heat treatment, part of oxygen contained in the oxide insulating film 24 can be moved to the oxide semiconductor film 18, so that the number of oxygen vacancies contained in the oxide semiconductor film 18 can be reduced. Further, in the case where water, hydrogen, or the like is contained in the oxide insulating film 24, when the nitride insulating film 25 having a function of blocking water, hydrogen, and the like is formed later and heat treatment is performed, water, hydrogen, or the like contained in the oxide insulating film 24 are moved to the oxide semiconductor film 18, so that defects are generated in the oxide semiconductor film 18. However, by the heating, water, hydrogen, or the like contained in the oxide insulating film 24 can be released; thus, variation in electrical characteristics of the transistor 50 can be reduced, and change in threshold voltage can be inhibited. Note that the oxide insulating film 24 can be formed over the oxide film 19 containing In or Ga while heating, whereby oxygen can be moved to the oxide semiconductor film 18 and oxygen vacancies contained in the oxide semiconductor film 18 can be reduced accordingly. Therefore, the heat treatment is not necessarily performed.

[0164] Here, the heat treatment is performed at 350° C. in an atmosphere of nitrogen and oxygen for 1 hour.

[0165] Further, when the pair of electrodes 21 and 22 is formed, the multilayer film 20 is damaged by etching of the conductive film, so that oxygen vacancies are generated on the back-channel side of the multilayer film 20. However, with the use of the oxide insulating film containing more oxygen than that in the stoichiometric composition as the oxide insulating film 24, the oxygen vacancies generated on the back channel side can be repaired by heat treatment. By this, defects contained in the multilayer film 20 can be reduced, and thus, the reliability of the transistor 50 can be improved.

[0166] Next, the nitride insulating film 25 is formed by a sputtering method, a CVD method, or the like.

[0167] Note that in the case where the nitride insulating film 25 is formed by a plasma CVD method, the substrate placed in the treatment chamber of the plasma CVD apparatus, which is vacuum-evacuated, is preferably set to be higher than or equal to 300° C. and lower than or equal to 400° C., more preferably, higher than or equal to 320° C. and lower than or equal to 370° C., so that a dense nitride insulating film can be formed.

[0168] In the case where a silicon nitride film is formed by the plasma CVD method as the nitride insulating film 25, a deposition gas containing silicon, nitrogen, and ammonia is preferably used as a source gas. As the source gas, a small amount of ammonia compared to the amount of nitrogen is used, whereby ammonia is dissociated in the plasma and activated species are generated. The activated species cleave a bond between silicon and hydrogen which are contained in a deposition gas containing silicon and a triple bond of nitrogen molecules. As a result, a dense silicon nitride film having few defects, in which a bond between silicon and nitrogen is promoted and a bond between silicon and hydrogen is few can be formed. On the other hand, when the amount of ammonia with respect to nitrogen is large in the source gas, cleavage of a deposition gas containing silicon and cleavage of nitrogen are not promoted, so that a sparse silicon nitride film in which a bond between silicon and hydrogen remains and defects are increased is formed. Therefore, in the source gas, a flow rate ratio of the nitrogen to the ammonia is set to be greater than or equal to 5 and less than or equal to 50, preferably greater than or equal to 10 and less than or equal to 50.

[0169] Here, in the treatment chamber of a plasma CVD apparatus, a 50-nm-thick silicon nitride film is formed by a plasma CVD method in which silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and ammonia with a flow rate of 100 sccm are used as the source gas, the pressure in the treatment chamber is 100 Pa, the substrate temperature is 350° C., and high-frequency power of 1000 W is supplied to parallel-plate electrodes with a high-frequency power supply of 27.12 MHz. Note that the plasma CVD apparatus is a parallel-plate plasma CVD apparatus in which the electrode area is 6000 cm², and the power per unit area (power density) into which the supplied power is converted is 1.7×10⁻¹W/cm².

[0170] By the above-described steps, the protective film 26 including the oxide insulating film 24 and the nitride insulating film 25 can be formed.

[0171] Next, heat treatment may be performed. The temperature of the heat treatment is typically higher than or equal to 150° C. and lower than the strain point of the substrate, preferably higher than or equal to 200° C. and lower than or equal to 450° C., more preferably higher than or equal to 300° C. and lower than or equal to 450° C.

[0172] By the above-described process, the transistor 50 can be manufactured.

[0173] The oxide insulating film containing more oxygen than that in the stoichiometric composition is formed to overlap with the oxide semiconductor film which serves as a channel region, and thus, oxygen in the oxide insulating film can be moved to the oxide semiconductor film. Consequently, the number of oxygen vacancies in the oxide semiconductor film can be reduced.

[0174] Further, the oxide film containing In or Ga is formed over the oxide semiconductor film, whereby damage to the oxide semiconductor film at the time of forming the oxide insulating film containing more oxygen than that in the stoichiometric composition can be further reduced. In addition, the oxide film containing In or Ga is formed, whereby mixing of a constituent element of an insulating film, e.g., the oxide insulating film, formed over the oxide semiconductor film to the oxide semiconductor film can be inhibited.

[0175] From the above, in a semiconductor device including an oxide semiconductor film, a semiconductor device in which the number of defects is reduced can be obtained. Further, in a semiconductor device including an oxide semiconductor film, a semiconductor device with improved electrical characteristics can be obtained.

Modification Example 1

[0176] In the transistor 50 described in this embodiment, a base insulating film may be provided between the substrate 11 and the gate electrode 15 as necessary. As a material of the base insulating film, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, and the like can be given as examples. Note that when silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, or the like is used as a material of the base insulating film, it is possible to inhibit diffusion of impurities such as alkali metal, water, and hydrogen into the multilayer film 20 from the substrate 11.

[0177] The base insulating film can be formed by a sputtering method, a CVD method, or the like.

Modification Example 2

[0178] It is preferable to use, as the oxide semiconductor film 18 provided in the transistor 50 described in this embodiment, an oxide semiconductor film in which the impurity concentration is low and density of defect states is low, in which case a transistor with more excellent electrical characteristics can be manufactured. Here, the state in which impurity concentration is low and density of defect states is low (the number of oxygen vacancies is small) is referred to as “highly purified intrinsic” or “substantially highly purified intrinsic”. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, and thus has a low carrier density in some cases. Thus, a transistor using the oxide semiconductor as a channel region rarely has electrical characteristics in which a threshold voltage is negative (also referred to as normally-on). A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states and accordingly has a low density of trap levels. Thus, the transistor using the oxide semiconductor as the channel region has a small variation in electrical characteristics and high reliability. Charges trapped by the trap levels in the oxide semiconductor take a long time to be released and may behave like fixed charges. Thus, the transistor which uses the oxide semiconductor having a high density of trap levels as a channel region has unstable electrical characteristics in some cases. As examples of the impurities, hydrogen, nitrogen, alkali metal, alkaline earth metal, and the like are given.

[0179] Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and in addition, an oxygen vacancy is formed in a lattice from which oxygen is released (or a portion from which oxygen is released). Due to entry of hydrogen into the oxygen vacancy, an electron serving as a carrier is generated in some cases. Further, in some cases, bonding of part of hydrogen to oxygen bonded to a metal element causes generation of an electron serving as a carrier. Thus, a transistor including an oxide semiconductor which contains hydrogen is likely to be normally on.

[0180] Accordingly, it is preferable that hydrogen be reduced as much as possible in the oxide semiconductor film 18. Specifically, the hydrogen concentration of the oxide semiconductor film 18, which is measured by secondary ion mass spectrometry (SIMS), is lower than or equal to 5×10¹⁸atoms/cm³, preferably lower than or equal to 1×10¹⁸atoms/cm³, more preferably lower than or equal to 5×10¹⁷atoms/cm³, even more preferably lower than or equal to 1×10¹⁶atoms/cm³.

[0181] As a method for reducing the hydrogen concentration of the oxide semiconductor film 18, after the multilayer film 20 including the oxide semiconductor film 18 and the oxide film 19 containing In or Ga are formed in FIG. 3B, heat treatment is performed; thus, the hydrogen concentration of the oxide semiconductor film 18 can be reduced. The temperature of the heat treatment is typically higher than or equal to 150° C. and lower than the strain point of the substrate, preferably higher than or equal to 200° C. and lower than or equal to 450° C., more preferably higher than or equal to 300° C. and lower than or equal to 450° C.

[0182] Further, the concentration of alkali metal or alkaline earth metal of the oxide semiconductor film 18, which is measured by secondary ion mass spectrometry, is set to lower than or equal to 1×10¹⁸atoms/cm³, preferably lower than or equal to 2×10¹⁶atoms/cm³. Alkali metal and alkaline earth metal might generate carriers when bonded to an oxide semiconductor, in which case the off-state current of the transistor might be increased. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal of the oxide semiconductor film 18.

[0183] By providing a nitride insulating film in part of the gate insulating film 17, the concentration of alkali metal or alkaline earth metal of the oxide semiconductor film 18 can be reduced.

[0184] Further, when containing nitrogen, the oxide semiconductor film 18 easily has n-type conductivity by generation of electrons serving as carriers and an increase of carrier density. Thus, a transistor including an oxide semiconductor which contains nitrogen is likely to have normally-on characteristics. For this reason, nitrogen in the oxide semiconductor film is preferably reduced as much as possible; the concentration of nitrogen is preferably set to, for example, lower than or equal to 5×10¹⁸atoms/cm³.

[0185] In this manner, when the oxide semiconductor film 18 highly purified by reducing impurities (such as hydrogen, nitrogen, alkali metal, and alkaline earth metal) as much as possible is included, it is possible to inhibit making the transistor have normally-on characteristics, so that the off-state current of the transistor can be significantly reduced. Accordingly, a semiconductor device having favorable electrical characteristics can be manufactured. Further, a semiconductor device with improved reliability can be manufactured.

[0186] Various experiments can prove the low off-state current of a transistor including a highly purified oxide semiconductor film. For example, even when an element has a channel width of 1×10⁶μm and a channel length L of 10 μm, off-state current can be less than or equal to the measurement limit of a semiconductor parameter analyzer, i.e., less than or equal to 1×10⁻¹³A, at a voltage (drain voltage) between the source electrode and the drain electrode of from 1 V to 10 V. In that case, it can be found that a value obtained by dividing the off-state current by the channel width of the transistor is less than or equal to 100 zA/μm. In addition, a capacitor and a transistor are connected to each other and the off-state current is measured with a circuit in which charge flowing into or from the capacitor is controlled by the transistor. In the measurement, part of a highly purified oxide semiconductor film is used for a channel region of the transistor, and the off-state current of the transistor is measured from a change in the amount of charge of the capacitor per unit time. As a result, it is found that in the case where the voltage between the source electrode and the drain electrode of the transistor is 3 V, lower off-state current of several tens of yoctoamperes per micrometer (yA/μm) can be obtained. Thus, the transistor including the highly purified oxide semiconductor film has a significantly low off-state current.

Modification Example 3

[0187] As for the pair of electrodes 21 and 22 provided in the transistor 50 described in this embodiment, it is preferable to use a conductive material which is easily bonded to oxygen, such as tungsten, titanium, aluminum, copper, molybdenum, chromium, or tantalum, or an alloy thereof. Thus, oxygen contained in the multilayer film 20 and the conductive material contained in the pair of electrodes 21 and 22 are bonded to each other, so that an oxygen deficient region is formed in the multilayer film 20. Further, in some cases, part of constituent elements of the conductive material that forms the pair of electrodes 21 and 22 is mixed into the multilayer film 20. As a result of these, in the multilayer film 20, a low-resistance region is formed in the vicinity of a region in contact with the pair of electrodes 21 and 22. FIGS. 4A to 4C are each an enlarged cross-sectional view of the multilayer film 20 of the transistor 50 shown in FIG. 1B. There is a case where, as shown in FIG. 4A, large parts of low-resistance regions 28a and 29a are formed in the oxide film 19 containing In or Ga. There is another case where, as shown in FIG. 4B, low-resistance regions 28b and 29b are formed in the oxide semiconductor film 18 and the oxide film 19 containing In or Ga. There is still another case where, as shown in FIG. 4C, low-resistance regions 28c and 29c are formed in the oxide semiconductor film 18 and the oxide film 19 containing In or Ga so as to be in contact with the gate insulating film 17. Since the low-resistance regions 28a to 28c and 29a to 29c have high conductivity, contact resistance between the multilayer film 20 and the pair of electrodes 21 and 22 can be reduced, and thus, the on-state current of the transistor can be increased.

Modification Example 4

[0188] In the method for manufacturing the transistor 50 described in this embodiment, after the pair of electrodes 21 and 22 is formed, cleaning treatment may be performed to remove an etching residue. By performing the cleaning treatment, occurrence of leakage current flowing between the pair of electrodes 21 and 22 can be inhibited. The cleaning treatment can be performed using an alkaline solution such as a tetramethylammonium hydroxide (TMAH) solution, an acidic solution such as diluted hydrofluoric acid, an oxalic acid solution, or a phosphorus acid solution.

Modification Example 5

[0189] In the method for manufacturing the transistor 50 described in this embodiment, after the pair of electrodes 21 and 22 is formed, the multilayer film 20 may be exposed to plasma generated in an oxygen atmosphere, so that oxygen may be supplied to the oxide semiconductor film 18 and the oxide film 19 containing In or Ga. Atmospheres of oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, and the like can be given as examples of the oxygen atmosphere. Further, in the plasma treatment, the multilayer film 20 is preferred to be exposed to plasma generated with no bias applied to the substrate 11 side. Consequently, the multilayer film 20 can be supplied with oxygen without being damaged, and the number of oxygen vacancies in the multilayer film 20 can be reduced. Moreover, impurities remaining on the surface of the multilayer film 20 due to etching treatment, for example, a halogen such as fluorine or chlorine can be removed.

[0190] Note that the structures, methods, and the like described in this embodiment can be used as appropriate in combination with any of the structures, methods, and the like described in the other embodiments and examples.

(Embodiment 2)

[0191] In this embodiment, a semiconductor device having a transistor in which the number of defects in the oxide semiconductor film can be further reduced as compared to Embodiment 1 is described with reference to drawings. The transistor described in this embodiment is different from that in Embodiment 1 in having an oxide film containing In or Ga between the gate insulating film and the oxide semiconductor film.

[0192] FIGS. 5A to 5E are a top view and cross-sectional views of a transistor 60 included in the semiconductor device. FIG. 5A is a top view of the transistor 60, FIG. 5B is a cross-sectional view taken along dashed-dotted line A-B of FIG. 5A, and FIG. 5C is a cross-sectional view taken along dashed-dotted line C-D of FIG. 5A. Note that in FIG. 5A, the substrate 11, the gate insulating film 17, the oxide insulating film 23, the oxide insulating film 24, the nitride insulating film 25, and the like are omitted for simplicity.

[0193] The transistor 60 shown in FIGS. 5A to 5E includes the gate electrode 15 provided over the substrate 11. Further, the gate insulating film 17 is formed over the substrate 11 and the gate electrode 15, and a multilayer film 34 overlapping with the gate electrode 15 with the gate insulating film 17 provided therebetween, and the pair of electrodes 21 and 22 in contact with the multilayer film 34 are included. Furthermore, the protective film 26 including the oxide insulating film 24 and the nitride insulating film 25 is formed over the gate insulating film 17, the multilayer film 34, and the pair of electrodes 21 and 22.

[0194] In the transistor 60 described in this embodiment, the multilayer film 34 includes an oxide film 31 containing In or Ga, an oxide semiconductor film 32, and an oxide film 33 containing In or Ga. Further, part of the oxide semiconductor film 32 serves as a channel region.

[0195] Further, the gate insulating film 17 and the oxide film 31 containing In or Ga are in contact with each other. That is, the oxide film 31 containing In or Ga is provided between the gate insulating film 17 and the oxide semiconductor film 32.

[0196] Further, the oxide insulating film 24 and the oxide film 33 containing In or Ga are in contact with each other. That is, the oxide film 33 containing In or Ga is provided between the oxide semiconductor film 32 and the oxide insulating film 24.

[0197] A material and a formation method which are similar to those of the oxide film 19 containing In or Ga in Embodiment 1 can be used for the oxide film 31 containing In or Ga and the oxide film 33 containing In or Ga as appropriate.

[0198] The oxide semiconductor film 32 can be formed as appropriate using a material and a formation method that are similar to those of the oxide semiconductor film 18 described in Embodiment 1.

[0199] Note that when the oxide film 31 containing In or Ga is In-M-Zn oxide, the proportions of In and M are preferably as follows: the proportion of In atoms be lower than 50 atomic % and the proportion of M atoms be higher than or equal to 50 atomic %, and it is further preferably as follows: the proportion of In atoms be lower than 25 atomic % and the proportion of M atoms be higher than or equal to 75 atomic %. When the oxide semiconductor film 32 and the oxide film 33 containing In or Ga are In-M-Zn oxide, the proportions of In and M are preferably similar to that shown in Embodiment 1.

[0200] Here, as the oxide film 31 containing In or Ga, a 30-nm-thick In—Ga—Zn oxide film (the atomic ratio of a sputtering target used for film formation is In:Ga:Zn=1:6:4) is formed by a sputtering method. Further, as the oxide semiconductor film 32, a 10-nm-thick In—Ga—Zn oxide film (the atomic ratio of a sputtering target used for film formation is In:Ga:Zn=1:1:1) is formed. Furthermore, as the oxide film 33 containing In or Ga, a 10-nm-thick In—Ga—Zn oxide film (the atomic ratio of a sputtering target used for film formation is In:Ga:Zn=1:3:2) is formed.

[0201] Here, the band structure along dashed-dotted line G-H in the vicinity of the multilayer film 34 of the transistor 60 in FIGS. 5A to 5E is described with reference to FIG. 6A, and the flow of carrier in the transistor 60 is described with reference to FIG. 6B.

[0202] In the band structure shown in FIG. 6A, for example, In—Ga—Zn oxide (the atomic ratio of a sputtering target used for film formation is In:Ga:Zn=1:6:4) with an energy gap of 3.8 eV is used for the oxide film 31 containing In or Ga. In—Ga—Zn oxide (the atomic ratio of a sputtering target used for film formation is In:Ga:Zn=1:1:1) with an energy gap of 3.2 eV is used for the oxide semiconductor film 32. In—Ga—Zn oxide (the atomic ratio of a sputtering target used for film formation is In:Ga:Zn=1:3:2) with an energy gap of 3.5 eV is used for the oxide film 33 containing In or Ga.

[0203] The energy difference between the vacuum level and the valence band top (also referred to as ionization potential) of the oxide film 31 containing In or Ga, the energy difference therebetween of the oxide semiconductor film 32, and the energy difference therebetween of the oxide film 33 containing In or Ga are 7.8 eV, 7.9 eV, and 8.0 eV, respectively.

[0204] The energy difference between the vacuum level and the conduction band bottom (also referred to as electron affinity) of the oxide film 31 containing In or Ga, the energy difference therebetween of the oxide semiconductor film 32, and the energy difference therebetween of the oxide film 33 containing In or Ga are 4.0 eV, 4.7 eV, and 4.5 eV, respectively.

[0205] Further, the conduction band bottom of the oxide film 31 containing In or Ga is denoted by Ec_31, the conduction band bottom of the oxide semiconductor film 32 is denoted by Ec_32, and the conduction band bottom of the oxide film 33 containing In or Ga is denoted by Ec_33. Further, the conduction band bottom of the gate insulating film 17 is denoted by Ec_17, and the conduction band bottom of the oxide insulating film 24 is denoted by Ec_24.

[0206] As shown in FIG. 6A, in the multilayer film 34, the conduction band bottom in the vicinity of the interface between the oxide film 31 containing In or Ga and the oxide semiconductor film 32 and the conduction band bottom in the vicinity of the interface between the oxide semiconductor film 32 and the oxide film 33 containing In or Ga vary continuously. That is, there is no barrier in the vicinity of the interface between the oxide film 31 containing In or Ga and the oxide semiconductor film 32 and in the vicinity of the interface between the oxide semiconductor film 32 and the oxide film 33 containing In or Ga and the conduction band bottom smoothly varies. A structure having such a conduction band bottom can also be referred to as a U-shaped well (U shape well) structure. Such a shape is caused by mutual transfer of oxygen between the oxide film 31 containing In or Ga and the oxide semiconductor film 32 and between the oxide semiconductor film 32 and the oxide film 33 containing In or Ga. Further, in the multilayer film 34, the energy of the conduction band bottom Ec_32 of the oxide semiconductor film 32 is the lowest, and this region serves as a channel region.

[0207] Now, a state where electrons serving as carrier flow in the transistor 60 is described with reference to FIG. 6B. Note that in FIG. 6B, the flow of electrons flowing in the oxide semiconductor film 32 is represented by a dotted arrow.

[0208] Trap levels 36 due to impurities and defects are formed in the vicinity of the interface between the gate insulating film 17 and the oxide film 31 containing In or Ga. Further, trap levels 37 are formed in the vicinity of the interface between the oxide film 33 containing In or Ga and the oxide insulating film 24 in a similar manner. In the transistor 60 described in this embodiment, the oxide film 31 containing In or Ga is provided between the gate insulating film 17 and the oxide semiconductor film 32 as shown in FIG. 6B; thus, there is a distance between the oxide semiconductor film 32 and the trap levels 36. Further, the oxide film 33 containing In or Ga is provided between the oxide semiconductor film 32 and the oxide insulating film 24; thus, there is a distance between the oxide semiconductor film 32 and the trap levels 37.

[0209] As a result, electrons flowing in the oxide semiconductor film 32 are less likely to be captured by the trap levels 36 and 37, the on-state current of the transistor can be increased, and field effect mobility can be increased. Further, when the electrons are captured by the trap levels 36 and 37, the electrons become negative fixed charges. Consequently, a threshold voltage of the transistor varies. However, by the distance between the oxide semiconductor film 32 and the trap levels 36 and 37, capture of the electrons by the trap levels 36 and 37 can be reduced, and accordingly a variation of the threshold voltage can be reduced.

[0210] Note that when the energy difference ΔE2 of the conduction band bottom in the vicinity of the interface between the oxide film 31 containing In or Ga and the oxide semiconductor film 32 and the energy difference ΔE3 of the conduction band bottom in the vicinity of the interface between the oxide semiconductor film 32 and the oxide film 33 containing In or Ga are small, carrier flowing in the oxide semiconductor film 32 transcends the conduction band bottom of the oxide film 31 containing In or Ga and the conduction band bottom of the oxide film 33 containing In or Ga and is captured by the trap levels 36 and 37. Thus, the energy difference ΔE2 between the conduction band bottoms of the oxide film 31 containing In or Ga and the oxide semiconductor film 32 and the energy difference ΔE3 between the conduction band bottoms of the oxide semiconductor film 32 and the oxide film 33 containing In or Ga are greater than or equal to 0.1 eV, preferably greater than or equal to 0.15 eV.

[0211] Note that when the energy difference ΔE3 in the vicinity of the interface between the oxide semiconductor film 32 and the oxide film 33 containing In or Ga is small as compared with the energy difference ΔE2 in the vicinity of the interface between the oxide film 31 containing In or Ga and the oxide semiconductor film 32, resistance between the oxide semiconductor film 32 and the pair of electrodes 21 and 22 can be reduced and the amount of electrons captured by the trap levels 36 can be reduced. Thus, the amount of on-state current of the transistor can be further increased, and the field-effect mobility can be further increased.

[0212] Although the energy difference ΔE3 is smaller than the energy difference ΔE2, the energy difference ΔE2 and the energy difference ΔE3 can be same or the energy difference ΔE3 can be larger than the energy difference ΔE2 by selecting, as appropriate, constituent elements and compositions of the oxide film 31 containing In or Ga, the oxide semiconductor film 32, and the oxide film 33 containing In or Ga in accordance with the electrical characteristics of the transistor.

[0213] Further, the oxide insulating film 24 (see FIGS. 5A to 5E) containing more oxygen than that in the stoichiometric composition is provided on the back channel side of the multilayer film 34 (a surface of the multilayer film 34, which is opposite to a surface facing the gate electrode 15). Therefore, oxygen contained in the oxide insulating film 24 containing more oxygen than that in the stoichiometric composition is moved to the oxide semiconductor film 32 included in the multilayer film 34, whereby oxygen vacancies in the oxide semiconductor film 32 can be reduced.

[0214] Although the multilayer film 34 is damaged by etching for forming the pair of electrodes 21 and 22 and oxygen vacancies are generated on the back channel side of the multilayer film 34, the oxygen vacancies can be repaired by oxygen contained in the oxide insulating film 24 containing more oxygen than that in the stoichiometric composition. Accordingly, the reliability of the transistor 60 can be improved.

[0215] From the above, oxygen vacancies in the multilayer film 34 can be reduced by providing the multilayer film 34 including the oxide film 31 containing In or Ga, the oxide semiconductor film 32, and the oxide film 33 containing In or Ga, and the oxide insulating film 24 containing more oxygen than that in the stoichiometric composition provided over the multilayer film 34. Further, the oxide film 31 containing In or Ga is provided between the gate insulating film 17 and the oxide semiconductor film 32, and the oxide film 33 containing In or Ga is provided between the oxide semiconductor film 32 and the oxide insulating film 24. Thus, it is possible to reduce the concentration of silicon or carbon in the vicinity of the interface between the oxide film 31 containing In or Ga and the oxide semiconductor film 32, the concentration of silicon or carbon in the oxide semiconductor film 32, or the concentration of silicon or carbon in the vicinity of the interface between the oxide film 33 containing In or Ga and the oxide semiconductor film 32. Consequently, in the multilayer film 34, the absorption coefficient derived from a constant photocurrent method is lower than 1×10⁻³/cm, preferably lower than 1×10⁻⁴/cm, and thus density of localized levels is extremely low.

[0216] Since the transistor 60 having such a structure includes very few defects in the multilayer film 34 including the oxide semiconductor film 32, the electrical characteristics of the transistor can be improved, and typically, the on-state current can be increased and the field-effect mobility can be improved. Further, in a BT stress test and a BT photostress test which are examples of a stress test, the threshold voltage does not change or the amount of change in the positive direction or the negative direction is less than or equal to 1.0 V, preferably less than or equal to 0.5 V, and thus, reliability is high.

Modification Example 1

[0217] Instead of the multilayer film 34 which is described in this embodiment and shown in FIGS. 5A to 5C, a multilayer film 34a including the oxide film 31 containing In or Ga, the oxide semiconductor film 32, the oxide film 33 containing In or Ga, and an oxide film 35 containing In or Ga can be used as shown in FIGS. 5D and 5E. Note that FIG. 5D corresponds to an enlarged view of the vicinity of the multilayer film 34 shown in FIG. 5B, and FIG. 5E corresponds to an enlarged view of the vicinity of the multilayer film 34 shown in FIG. 5C.

[0218] The oxide film 35 containing In or Ga is provided on the side surfaces of the oxide film 31 containing In or Ga, the oxide semiconductor film 32, and the oxide film 33 containing In or Ga. That is, the oxide semiconductor film 32 is surrounded by the oxide films each containing In or Ga.

[0219] The oxide film 35 containing In or Ga is formed using metal oxide which is similar to that of the oxide films 31 and 33 each containing In or Ga. That is, the bandgap of the oxide film 35 containing In or Ga is larger than that of the oxide semiconductor film 32, and thus, it is possible to inhibit capturing of an electron in a trap level in the vicinity of the interface between the multilayer film 34a and the gate insulating film 17 or a trap level in the vicinity of the interface between the multilayer film 34a and the oxide insulating film 23. Consequently, the reliability of the transistor is improved.

[0220] Note that the oxide film 35 containing In or Ga is formed in such a manner that a reaction product generated in a step of dry etching for forming the oxide film 31 containing In or Ga, the oxide semiconductor film 32, and the oxide film 33 containing In or Ga is attached to the side surfaces of the oxide film 31 containing In or Ga, the oxide semiconductor film 32, and the oxide film 33 containing In or Ga. The dry etching may be performed under conditions in which, for example, a boron trichloride gas and a chlorine gas are used as etching gases and inductively coupled plasma (ICP) power and substrate bias power are applied.

[0221] In the transistor 60, in the case where an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition and from which part of oxygen is released by heating is used as the gate insulating film 17 and the oxide insulating film 24, a cross-sectional structure in a channel width direction (see FIG. 5E) is a structure in which the oxide semiconductor film 32 covered with the oxide films 31, 33, and 35 containing In or Ga is further covered with the oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition and from which part of oxygen is released by heating.

[0222] With the cross-sectional structure, leakage current flowing in the side surfaces of the oxide semiconductor film 32 can be reduced, an increase in off-state current can be suppressed, and an amount of change in the threshold voltage due to a stress test can be reduced, so that the reliability can be increased. Further, oxygen can be effectively transferred from the gate insulating film 17 and the oxide insulating film 24 to the oxide semiconductor film 32, so that the number of oxygen vacancies contained in the oxide semiconductor film 32 can be reduced.

Modification Example 2

[0223] In the transistor 60 described in this embodiment, the stacked-layer structure of the multilayer film 34 and the pair of electrodes 21 and 22 may be changed as appropriate. For example, a transistor 65 as shown in FIGS. 7A to 7C can be given as a modification example.

[0224] A top view of the transistor 65 is shown in FIG. 7A. A cross-sectional view taken along dashed-dotted line A-B in FIG. 7A is shown in FIG. 7B, and a cross-sectional view taken along dashed-dotted line C-D is shown in FIG. 7C. Note that in FIG. 7A, the substrate 11, the gate insulating film 17, the oxide film 31 containing In or Ga, the oxide semiconductor film 32, the protective film 26, and the like are omitted for simplicity.

[0225] The transistor 65 is different from the transistor 60 in that part of the pair of electrodes 21 and 22 is surrounded by the oxide semiconductor film 32 and the oxide film 33 containing In or Ga. Specifically, in the transistor 65, the oxide semiconductor film 32 is provided over the oxide film 31 containing In or Ga, the pair of electrodes 21 and 22 is provided over the oxide semiconductor film 32, and the oxide film 33 containing In or Ga is provided in contact with the oxide semiconductor film 32 and the pair of electrodes 21 and 22. Note that in the transistor 65, the stacked-layer structure of the other components is the same as the stacked-layer structure in the transistor 60.

[0226] The transistor 65 is a transistor in which the contact resistance between the multilayer film 34 and the pair of electrodes 21 and 22 is lower than that of the transistor 60 and the on-state current is improved as compared to the transistor 60 because the pair of electrodes 21 and 22 is in contact with the oxide semiconductor film 32.

[0227] Further, since the pair of electrode 21 and 22 is in contact with the oxide semiconductor film 32 in the transistor 65, the oxide film 33 containing In or Ga can be thickened without increase of the contact resistance between the multilayer film 34 and the pair of electrodes 21 and 22. Thus, it is possible to inhibit formation of a trap level, which occurs due to plasma damage at the time of forming the protective film 26, mixing of a constituent element of the protective film 26, or the like, in the vicinity of the interface between the oxide semiconductor film 32 and the oxide film 33 containing In or Ga. That is, the transistor 65 can achieve both improvement of on-state current and reduction of change in threshold voltage.

[0228] A method for manufacturing the transistor 65 is described with reference to FIGS. 8A to 8D. First, in a manner similar to that of FIG. 3A, the gate electrode and the gate insulating film 17 are formed over the substrate 11 (see FIG. 8A).

[0229] Next, an oxide film 44 containing In or Ga which is to be the oxide film 31 containing In or Ga and an oxide semiconductor film 45 which is to be the oxide semiconductor film 32 are successively formed, and then, the pair of electrodes 21 and 22 is formed (see FIG. 8B). A material and a formation method which are similar to those of the oxide film 19 containing In or Ga described in Embodiment 1 can be used for the oxide film 44 containing In or Ga as appropriate. A material and a formation method which are similar to those of the oxide semiconductor film 18 described in Embodiment 1 can be used for the oxide semiconductor film 45 as appropriate. Further, the pair of electrodes 21 and 22 can be formed in a manner similar to that of FIG. 3C. Note that the pair of electrodes 21 and 22 is formed over the oxide semiconductor film 45.

[0230] Next, an oxide film containing In or Ga which is to be the oxide film 33 containing In or Ga is formed to cover the oxide semiconductor film 45 which is to be the oxide semiconductor film 32 and the pair of electrodes 21 and 22. A material and a formation method which are similar to those of the oxide film 19 containing In or Ga described in Embodiment 1 can be used for the oxide film containing In or Ga as appropriate.

[0231] After that, the oxide film 44 containing In or Ga which is to be the oxide film 31 containing In or Ga, the oxide semiconductor film 45 which is to be the oxide semiconductor film 32, and the oxide film containing In or Ga which is to be the oxide film 33 containing In or Ga are each partly etched to form the multilayer film 34 including the oxide film 31 containing In or Ga, the oxide semiconductor film 32, and the oxide film 33 containing In or Ga (see FIG. 8C). Note that the etching can be implemented with the use of a mask after the mask is formed by a photolithography process over the oxide film containing In or Ga which is to be the oxide film 33 containing In or Ga.

[0232] Next, the protective film 26 is formed to cover the gate insulating film 17, the multilayer film 34, and the pair of electrodes 21 and 22. The protective film 26 can be formed in a manner similar to that in Embodiment 1 (see FIG. 8D). Further, in the method for manufacturing the transistor 65, heat treatment can be performed with reference to Embodiment 1 as appropriate.

[0233] Further, by the etching for forming the pair of electrodes 21 and 22, defects such as oxygen vacancies are generated in the oxide semiconductor film which is to be the oxide semiconductor film 32 and the carrier density is increased in some cases; therefore, before the oxide film containing In or Ga which is to be the oxide film 33 containing In or Ga is formed, the oxide semiconductor film is preferably exposed to plasma generated in an oxygen atmosphere so that oxygen is supplied to the oxide semiconductor film. Thus, in the transistor 65, formation of a trap level in the vicinity of the interface between the oxide semiconductor film 32 and the oxide film 33 containing In or Ga can be inhibited, and change in threshold voltage can be reduced. Further, in the transistor 65, leakage current that flows in the vicinity of the side surface of the oxide semiconductor film 32 in the multilayer film 34 can be reduced, and increase of off-state current can be inhibited.

[0234] Although the multilayer film 34 is damaged by etching for forming the pair of electrodes 21 and 22 and oxygen vacancies are generated on the back channel side of the multilayer film 34, the oxygen vacancies can be repaired by oxygen contained in the oxide insulating film 24 containing more oxygen than that in the stoichiometric composition. Accordingly, the reliability of the transistor 65 can be improved.

Modification Example 3

[0235] In the transistor 60 described in this embodiment, the stacked-layer structure of the multilayer film 34 and the pair of electrodes 21 and 22 may be changed as appropriate. For example, a transistor 66 as shown in FIGS. 9A to 9C can be given as a modification example.

[0236] A top view of the transistor 66 is shown in FIG. 9A. A cross-sectional view taken along dashed-dotted line A-B in FIG. 9A is shown in FIG. 9B, and a cross-sectional view taken along dashed-dotted line C-D is shown in FIG. 9C. Note that in FIG. 9A, the substrate 11, the gate insulating film 17, the protective film 26, and the like are omitted for simplicity.

[0237] The transistor 66 is different from the transistor 60 in that the oxide film 33 containing In or Ga is formed over the gate insulating film 17, the pair of electrodes 21 and 22, and the oxide semiconductor film 32. Specifically, in the transistor 66, the oxide semiconductor film 32 is provided over the oxide film 31 containing In or Ga, the pair of electrodes 21 and 22 is provided to cover the oxide film 31 containing In or Ga and the oxide semiconductor film 32, and the oxide film 33 containing In or Ga is provided to cover the oxide film 31 containing In or Ga, the oxide semiconductor film 32, and the pair of electrodes 21 and 22. Note that in the transistor 66, the stacked-layer structure of the other components is the same as the stacked-layer structure of the transistor 60.

[0238] The transistor 66 is a transistor in which the contact resistance between the multilayer film 34 and the pair of electrodes 21 and 22 is low and the on-state current is improved as compared to the transistor 60 because the area of contact of the pair of electrodes 21 and 22 with the oxide semiconductor film 32 is larger than that in the transistor 60.

[0239] Further, since the area of contact of the pair of electrodes 21 and 22 with the oxide semiconductor film 32 is large in the transistor 66, the oxide film 33 containing In or Ga can be thickened without increase of the contact resistance between the multilayer film 34 and the pair of electrodes 21 and 22. Thus, it is possible to inhibit formation of a trap level, which occurs due to plasma damage at the time of forming the protective film 26, mixing of a constituent element of the protective film 26, or the like, in the vicinity of the interface between the oxide semiconductor film 32 and the oxide film 33 containing In or Ga. That is, the transistor 66 can achieve both improvement of on-state current and reduction of change in threshold voltage.

[0240] A method for manufacturing the transistor 66 is described with reference to FIGS. 10A to 10D. First, in a manner similar to that in FIG. 3A, the gate electrode and the gate insulating film 17 are formed over the substrate 11 (see FIG. 10A).

[0241] Next, the oxide film containing In or Ga which is to be the oxide film 31 containing In or Ga and the oxide semiconductor film which is to be the oxide semiconductor film 32 are successively formed, and a mask is provided over the oxide semiconductor film by a photolithography process, and etching is performed with the use of the mask to form the oxide film 31 containing In or Ga and the oxide semiconductor film 32. After that, the pair of electrodes 21 and 22 is formed to cover the edge portions of the oxide film 31 containing In or Ga and the oxide semiconductor film 32 (see FIG. 10B). Note that a material and a film formation method which are similar to those of the oxide film 19 containing In or Ga in Embodiment 1 can be used for the oxide film containing In or Ga as appropriate. A material and a film formation method which are similar to those of the oxide semiconductor film 18 in Embodiment 1 can be used for the oxide semiconductor film as appropriate. Further, the pair of electrodes 21 and 22 can be formed in a manner similar to that shown in FIG. 3C.

[0242] Next, the oxide film 33 containing In or Ga is formed to cover the oxide semiconductor film 32 and the pair of electrodes 21 and 22; thus, the multilayer film 34 is formed (see FIG. 10C). A material and a film formation method which are similar to those of the oxide film 19 containing In or Ga in Embodiment 1 can be used for the oxide film containing In or Ga as appropriate. Note that the oxide film 33 containing In or Ga may be processed by etching or the like using a mask formed by a photolithography process or the like as shown in FIG. 7B, or may remain the state when the film was formed.

[0243] Next, the protective film 26 is formed over the gate insulating film 17 and the oxide film 33 containing In or Ga. The protective film 26 can be formed in a manner similar to that in Embodiment 1 (see FIG. 10D). Further, in the method for manufacturing the transistor 66, heat treatment can be performed referring to Embodiment 1 as appropriate.

[0244] Further, by etching for forming the oxide film 31 containing In or Ga and the oxide semiconductor film 32, defects such as oxygen vacancies are generated in the side surface of the oxide semiconductor film 32 and carrier density is increased accordingly in some cases. Furthermore, by etching for forming the pair of electrodes 21 and 22, defects such as oxygen vacancies are generated in the surface of the oxide semiconductor film 32 and carrier density is increased accordingly in some cases. Therefore, after the oxide film 31 containing In or Ga and the oxide semiconductor film 32 are formed or/and after the pair of electrodes 21 and 22 is formed, the oxide semiconductor film 32 is preferably exposed to plasma generated in an oxygen atmosphere so that oxygen is supplied to the oxide semiconductor film 32.

[0245] Although the multilayer film 34 is damaged by etching for forming the pair of electrodes 21 and 22 and oxygen vacancies are generated on the back channel side of the multilayer film 34, the oxygen vacancies can be repaired by oxygen contained in the oxide insulating film 24 containing more oxygen than that in the stoichiometric composition. Accordingly, the reliability of the transistor 66 can be improved.

[0246] Thus, in the transistor 66, formation of a trap level in the side surface of the oxide semiconductor film 32 and in the vicinity of the interface between the oxide semiconductor film 32 and the oxide film 33 containing In or Ga can be inhibited, and change in threshold voltage can be reduced.

[0247] Further, in the transistor 66, the oxide film 33 containing In or Ga is provided to cover the side surfaces (the side surfaces in the channel length direction) of the oxide film 31 containing In or Ga and the oxide semiconductor film 32 (see FIG. 9C). Thus, leakage current that flows in the side surface of the oxide semiconductor film 32 can be reduced, and increase of off-state current can be inhibited.

[0248] Further, when the oxide film 31 containing In or Ga and the oxide semiconductor film 32 are formed (see FIG. 9B), in an etching step for forming the oxide film 31 containing In or Ga after the oxide semiconductor film 32 is formed, there may be a case where a reaction product is attached on the side surfaces of the oxide film 31 containing In or Ga and the oxide semiconductor film 32 to form an oxide film containing In or Ga (corresponding to the oxide film 35 containing In or Ga shown in FIG. 5D). In this case, the oxide film 33 containing In or Ga is formed to cover the oxide film containing In or Ga that covers the side surface of the oxide semiconductor film 32.

Modification Example 4

[0249] In the transistor 60 described in this embodiment, the stacked-layer structure of the multilayer film 34 and the pair of electrodes 21 and 22 may be changed as appropriate. For example, a transistor 67 as shown in FIGS. 11A to 11C can be given as a modification example.

[0250] A top view of the transistor 67 is shown in FIG. 11A. A cross-sectional view taken along dashed-dotted line A-B in FIG. 11A is shown in FIG. 11B, and a cross-sectional view taken along dashed-dotted line C-D is shown in FIG. 11C. Note that in FIG. 11A, the substrate 11, the gate insulating film 17, the protective film 26, and the like are omitted for simplicity.

[0251] In the transistor 67, the oxide film 33 containing In or Ga is provided to cover the pair of electrodes 21 and 22 and the edge portions of the oxide film 33 containing In or Ga are located over the pair of electrodes 21 and 22 in the transistor 66 shown in FIG. 9B. Note that in the transistor 67, the stacked-layer structure of the other components is the same as the stacked-layer structure of the transistor 66.

[0252] In the transistor 67, as shown in FIG. 11C, the oxide film 33 containing In or Ga is provided to cover the side surfaces of the oxide film 31 containing In or Ga and the oxide semiconductor film 32 on the side surfaces intersecting with the channel width direction. Thus, leakage current that flows in the side surface of the oxide semiconductor film 32 can be reduced, and increase of off-state current can be inhibited.

(Embodiment 3)

[0253] In this embodiment, a transistor having a different structure from the transistors in Embodiment 1 and Embodiment 2 is described with reference to FIG. 12. A transistor 70 described in this embodiment includes a plurality of gate electrodes facing each other with an oxide semiconductor film provided therebetween.

[0254] The transistor 70 shown in FIG. 12 includes the gate electrode 15 provided over the substrate 11. Further, the gate insulating film 17 is formed over the substrate 11 and the gate electrode 15, and the multilayer film 20 overlapping with the gate electrode 15 with the gate insulating film 17 provided therebetween, and the pair of electrodes 21 and 22 in contact with the multilayer film 20 are included. Note that the multilayer film 20 includes the oxide semiconductor film 18 and the oxide film 19 containing In or Ga. Furthermore, the protective film 26 including the oxide insulating film 24 and the nitride insulating film 25 is formed over the gate insulating film 17, the multilayer film 20, and the pair of electrodes 21 and 22. Still furthermore, a gate electrode 61 overlapping with the multilayer film 20 with the protective film 26 provided therebetween is included.

[0255] The gate electrode 61 can be formed in a manner similar to that of the gate electrode 15 in Embodiment 1.

[0256] The transistor 70 described this embodiment has the gate electrode 15 and the gate electrode 61 facing each other with the multilayer film 20 provided therebetween. By applying different electric potentials to the gate electrode 15 and the gate electrode 61, the threshold voltage of the transistor 70 can be controlled.

[0257] Further, when the multilayer film 20 having the oxide semiconductor film 18 in which the number of oxygen vacancies is reduced is included, the electrical characteristics of the transistor can be improved. Further, the transistor in which the amount of change in threshold voltage is small and which is highly reliable is obtained.

[0258] Although the oxide semiconductor film which is described in the above embodiments can be formed by a sputtering method, such film may be formed by another method, e.g., a thermal CVD method. A metal organic chemical vapor deposition (MOCVD) method or an atomic layer deposition (ALD) method may be employed as an example of a thermal CVD method.

[0259] A thermal CVD method has an advantage that no defect due to plasma damage is generated since it does not utilize plasma for forming a film.

[0260] Deposition by a thermal CVD method may be performed in such a manner that the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, and a source gas and an oxidizer are supplied to the chamber at a time and react with each other in the vicinity of the substrate or over the substrate.

[0261] Deposition by an ALD method may be performed in such a manner that the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, source gases for reaction are sequentially introduced into the chamber, and then the sequence of the gas introduction is repeated. For example, two or more kinds of source gases are sequentially supplied to the chamber by switching respective switching valves (also referred to as high-speed valves). For example, a first source gas is introduced, an inert gas (e.g., argon or nitrogen) or the like is introduced at the same time as or after the introduction of the first gas so that the source gases are not mixed, and then a second source gas is introduced. Note that in the case where the first source gas and the inert gas are introduced at a time, the inert gas serves as a carrier gas, and the inert gas may also be introduced at the same time as the introduction of the second source gas. Alternatively, the first source gas may be exhausted by vacuum evacuation instead of the introduction of the inert gas, and then the second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first single-atomic layer; then the second source gas is introduced to react with the first single-atomic layer; as a result, a second single-atomic layer is stacked over the first single-atomic layer, so that a thin film is formed. The sequence of the gas introduction is repeated plural times until a desired thickness is obtained, whereby a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of repetitions times of the sequence of the gas introduction; therefore, an ALD method makes it possible to accurately adjust a thickness and thus is suitable for manufacturing a minute FET.

[0262] The oxide semiconductor film which is described in the above embodiments can be formed by a thermal CVD method such as a MOCVD method or an ALD method. For example, in the case where an InGaZnO_X(X>0) film is formed, trimethylindium, trimethylgallium, and diethylzinc are used. Note that the chemical formula of trimethylindium is (CH₃)₃In. The chemical formula of trimethylgallium is (CH₃)₃Ga. The chemical formula of diethylzinc is (CH₃)₂Zn. Without limitation to the above combination, triethylgallium (chemical formula: (C₂H₅)₃Ga) can be used instead of trimethylgallium and dimethylzinc (chemical formula: (C₂H₅)₂Zn) can be used instead of diethylzinc.

[0263] For example, in the case where an oxide semiconductor film, e.g., an InGaZnO_X(X>0) film is formed using a deposition apparatus employing ALD, an In(CH₃)₃gas and an O₃gas are sequentially introduced plural times to form an InO₂layer, a Ga(CH₃)₃gas and an O₃gas are introduced at a time to form a GaO layer, and then a Zn(CH₃)₂gas and an O₃gas are introduced at a time to form a ZnO layer. Note that the order of these layers is not limited to this example. A mixed compound layer such as an InGaO₂layer, an InZnO₂layer, a GaInO layer, a ZnInO layer or a GaZnO layer may be formed by mixing of these gases. Note that although an H₂O gas which is obtained by bubbling with an inert gas such as Ar may be used instead of an O₃gas, it is preferable to use an O₃gas, which does not contain H. Further, instead of an In(CH₃)₃gas, an In(C₂H₅)₃gas may be used. Instead of a Ga(CH₃)₃gas, a Ga(C₂H₅)₃gas may be used. Instead of an In(CH₃)₃gas, an In(C₂H₅)₃may be used. Furthermore, a Zn(CH₃)₂gas may be used.

[0264] Note that the structures, methods, and the like described in this embodiment can be used as appropriate in combination with any of the structures, methods, and the like described in the other embodiments and examples.

(Embodiment 4)

[0265] In this embodiment, one embodiment which can be applied to an oxide semiconductor film in the transistor included in the semiconductor device described in the above embodiment is described.

[0266] The oxide semiconductor film can be formed using any of an amorphous oxide semiconductor, a single crystal oxide semiconductor, and a polycrystalline oxide semiconductor. Alternatively, the oxide semiconductor film may be formed using an oxide semiconductor including a crystalline portion (CAAC-OS).

[0267] The CAAC-OS film is one of oxide semiconductor films including a plurality of crystal parts, and most of the crystal parts each fit inside a cube whose one side is less than 100 nm. Thus, there is a case where a crystal part included in the CAAC-OS film fits a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm. The density of defect states of the CAAC-OS film is lower than that of the microcrystalline oxide semiconductor film. The CAAC-OS film is described in detail below.

[0268] In a transmission electron microscope (TEM) image of the CAAC-OS film, a boundary between crystal parts, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS film, a reduction in electron mobility due to the grain boundary is less likely to occur.

[0269] According to the TEM image of the CAAC-OS film observed in a direction substantially parallel to a sample surface (cross-sectional TEM image), metal atoms are arranged in a layered manner in the crystal parts. Each metal atom layer has a morphology reflected by a surface over which the CAAC-OS film is formed (hereinafter, a surface over which the CAAC-OS film is formed is referred to as a formation surface) or a top surface of the CAAC-OS film, and is arranged in parallel to the formation surface or the top surface of the CAAC-OS film.

[0270] On the other hand, according to the TEM image of the CAAC-OS film observed in a direction substantially perpendicular to the sample surface (plan TEM image), metal atoms are arranged in a triangular or hexagonal configuration in the crystal parts. However, there is no regularity of arrangement of metal atoms between different crystal parts.

[0271] From the results of the cross-sectional TEM image and the plan TEM image, alignment is found in the crystal parts in the CAAC-OS film.

[0272] A CAAC-OS film is subjected to structural analysis with an X-ray diffraction (XRD) apparatus. For example, when the CAAC-OS film including an InGaZnO₄crystal is analyzed by an out-of-plane method, a peak appears frequently when the diffraction angle (2θ) is around 31°. This peak is derived from the (009) plane of the InGaZnO₄crystal, which indicates that crystals in the CAAC-OS film have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS film.

[0273] On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which an X-ray enters a sample in a direction substantially perpendicular to the c-axis, a peak appears frequently when 2θ is around 56°. This peak is derived from the (110) plane of the InGaZnO₄crystal. Here, analysis (φ scan) is performed under conditions where the sample is rotated around a normal vector of a sample surface as an axis (φ axis) with 2θ fixed at around 56°. In the case where the sample is a single-crystal oxide semiconductor film of InGaZnO₄, six peaks appear. The six peaks are derived from crystal planes equivalent to the (110) plane. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 22θ fixed at around 56°.

[0274] According to the above results, in the CAAC-OS film having c-axis alignment, while the directions of a-axes and b-axes are different between crystal parts, the c-axes are aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface. Thus, each metal atom layer arranged in a layered manner observed in the cross-sectional TEM image corresponds to a plane parallel to the a-b plane of the crystal.

[0275] Note that the crystal part is formed concurrently with deposition of the CAAC-OS film or is formed through crystallization treatment such as heat treatment. As described above, the c-axis of the crystal is aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface. Thus, for example, in the case where a shape of the CAAC-OS film is changed by etching or the like, the c-axis might not be necessarily parallel to a normal vector of a formation surface or a normal vector of a top surface of the CAAC-OS film.

[0276] Further, the degree of crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where crystal growth leading to the CAAC-OS film occurs from the vicinity of the top surface of the film, the degree of the crystallinity in the vicinity of the top surface is higher than that in the vicinity of the formation surface in some cases. Further, when an impurity is added to the CAAC-OS film, the crystallinity in a region to which the impurity is added is changed, and the degree of crystallinity in the CAAC-OS film varies depending on regions.

[0277] Note that when the CAAC-OS film with an InGaZnO₄crystal is analyzed by an out-of-plane method, a peak of 2θ may also be observed at around 36°, in addition to the peak of 2θ at around 31°. The peak of 2θ at around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. It is preferable that in the CAAC-OS film, a peak of 2θ appear at around 31° and a peak of 2θ do not appear at around 36°.

[0278] There are three methods for forming a CAAC-OS film.

[0279] The first method is to form an oxide semiconductor film at a temperature higher than or equal to 150° C. and lower than or equal to 500° C., preferably higher than or equal to 150° C. and lower than or equal to 450° C., more preferably higher than or equal to 200° C. and lower than or equal to 350° C., whereby crystal parts in which the c-axes are aligned in the direction parallel to a normal vector of a surface on which the oxide semiconductor film is formed or a normal vector of a surface of the oxide semiconductor film are formed in the oxide semiconductor film.

[0280] The second method is to form an oxide semiconductor film with a small thickness and then heat it at a temperature higher than or equal to 200° C. and lower than or equal to 700° C., whereby crystal parts in which the c-axes are aligned in the direction parallel to a normal vector of a surface on which the oxide semiconductor film is formed or a normal vector of a surface of the oxide semiconductor film are formed in the oxide semiconductor film.

[0281] The third method is to form a first oxide semiconductor film with a small thickness, then heat it at a temperature higher than or equal to 200° C. and lower than or equal to 700° C., and form a second oxide semiconductor film, whereby crystal parts in which the c-axes are aligned in the direction parallel to a normal vector of a surface on which the oxide semiconductor film is formed or a normal vector of a surface of the oxide semiconductor film are formed in the oxide semiconductor film.

[0282] In a transistor using the CAAC-OS for an oxide semiconductor film, variations in electric characteristics of the transistor due to irradiation with visible light or ultraviolet light is small. Thus, the transistor using the CAAC-OS for the oxide semiconductor film has high reliability.

[0283] Further, it is preferable that the CAAC-OS is formed by a sputtering method with a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, a crystal region included in the sputtering target may be separated from the target along an a-b plane; in other words, a sputtered particle having a plane parallel to an a-b plane (flat-plate-like sputtered particle or pellet-like sputtered particle) may flake off from the sputtering target. In that case, the flat-plate-like sputtered particle or the pellet-like sputtered particle reaches a surface on which the CAAC-OS is formed while maintaining its crystal state, whereby the CAAC-OS can be deposited.

[0284] For the deposition of the CAAC-OS, the following conditions are preferably employed.

[0285] By reducing the amount of impurities entering the CAAC-OS during the deposition, the crystal state can be inhibited from being broken by the impurities. For example, the concentration of impurities (e.g., hydrogen, water, carbon dioxide, or nitrogen) which exist in the deposition chamber may be reduced. Furthermore, the concentration of impurities in a deposition gas may be reduced. Specifically, a deposition gas whose dew point is lower than or equal to −80° C., preferably lower than or equal to −100° C. is used.

[0286] By increasing the heating temperature of the surface on which the CAAC-OS is formed (e.g., the substrate heating temperature) during the deposition, migration of a sputtered particle is likely to occur after the sputtered particle reaches the surface on which the CAAC-OS is formed. Specifically, the temperature of the surface on which the CAAC-OS is formed during the deposition is higher than or equal to 100° C. and lower than or equal to 740° C., preferably higher than or equal to 150° C. and lower than or equal to 500° C. By increasing the temperature of the surface on which the CAAC-OS is formed during the deposition, when the flat-plate-like or pellet-like sputtered particle reaches the surface on which the CAAC-OS is formed, migration occurs on the surface on which the CAAC-OS is formed, so that a flat plane of the sputtered particle is attached to the surface on which the CAAC-OS is formed.

[0287] Furthermore, it is preferable that the proportion of oxygen in the deposition gas be increased and the power be optimized in order to reduce plasma damage at the deposition. The proportion of oxygen in the deposition gas is higher than or equal to 30 vol %, preferably 100 vol %.

[0288] As an example of the sputtering target, an In—Ga—Zn-based compound target is described below.

[0289] The polycrystalline In—Ga—Zn-based metal oxide target is made by mixing InO_Xpowder, GaO_Ypowder, and ZnO_Zpowder in a predetermined molar ratio, applying pressure, and performing heat treatment at a temperature higher than or equal to 1000° C. and lower than or equal to 1500° C. This pressure treatment may be performed while cooling is performed or may be performed while heating is performed. Note that X, Y, and Z are each a given positive number. Here, the predetermined molar ratio of InO_Xpowder to GaO_Ypowder and ZnO_Zpowder is, for example, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, 3:1:2, 1:3:2, 1:6:4, or 1:9:6. The kinds of powder and the molar ratio for mixing powder may be determined as appropriate depending on the desired sputtering target.

[0290] Note that the structures and the like described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 5)

[0291] A semiconductor device (also referred to as a display device) having a display function can be manufactured using the transistor examples of which are shown in the above embodiments. Moreover, some or all of the driver circuits which include the transistor can be formed over a substrate where the pixel portion is formed, whereby a system-on-panel can be obtained. In this embodiment, an example of a display device using the transistor examples of which are shown in the above embodiments is described with reference to FIGS. 13A to 13C and FIGS. 14A and 14B. FIGS. 14A and 14B are cross-sectional views illustrating cross-sectional structures taken along chain line M-N in FIG. 13B.

[0292] In FIG. 13A, a sealant 905 is provided so as to surround a pixel portion 902 provided over a first substrate 901, and the pixel portion 902 is sealed with a second substrate 906. In FIG. 13A, a signal line driver circuit 903 and a scan line driver circuit 904 each are formed using a single crystal semiconductor or a polycrystalline semiconductor over a substrate prepared separately, and mounted in a region different from the region surrounded by the sealant 905 over the first substrate 901. Further, various signals and electric potentials are supplied to the signal line driver circuit 903, the scan line driver circuit 904, and the pixel portion 902 from a flexible printed circuit (FPC) 918.

[0293] In FIGS. 13B and 13C, the sealant 905 is provided so as to surround the pixel portion 902 and the scan line driver circuit 904 which are provided over the first substrate 901. The second substrate 906 is provided over the pixel portion 902 and the scan line driver circuit 904. Thus, the pixel portion 902 and the scan line driver circuit 904 are sealed together with a display element by the first substrate 901, the sealant 905, and the second substrate 906. In FIGS. 13B and 13C, a signal line driver circuit 903 which is formed using a single crystal semiconductor or a polycrystalline semiconductor over a substrate separately prepared is mounted in a region different from the region surrounded by the sealant 905 over the first substrate 901. In FIGS. 13B and 13C, various signals and electric potentials are supplied to the signal line driver circuit 903, the scan line driver circuit 904, and the pixel portion 902 from an FPC 918.

[0294] Although FIGS. 13B and 13C each show an example in which the signal line driver circuit 903 is formed separately and mounted on the first substrate 901, one embodiment of the present invention is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

[0295] Note that a connection method of a separately formed driver circuit is not particularly limited, and a chip on glass (COG) method, a wire bonding method, a tape automated bonding (TAB) method, or the like can be used. FIG. 13A shows an example in which the signal line driver circuit 903 and the scan line driver circuit 904 are mounted by a COG method. FIG. 13B shows an example in which the signal line driver circuit 903 is mounted by a COG method. FIG. 13C shows an example in which the signal line driver circuit 903 is mounted by a TAB method.

[0296] The display device includes in its category a panel in which a display element is sealed and a module in which an IC including a controller or the like is mounted on the panel.

[0297] A display device in this specification refers to an image display device or a light source (including a lighting device). Further, the display device also includes the following modules in its category: a module to which a connector such as an FPC or a TCP is attached; a module having a TCP at the tip of which a printed wiring board is provided; and a module in which an integrated circuit (IC) is directly mounted on a display element by a COG method.

[0298] The pixel portion and the scan line driver circuit provided over the first substrate include a plurality of transistors and any of the transistors which are described in the above embodiments can be used.

[0299] As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. A light emitting element includes, in its scope, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic electroluminescent (EL) element, an organic EL element, and the like. Further, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used. FIG. 14A illustrates an example of a liquid crystal display device using a liquid crystal element as the display element and FIG. 14B illustrates an example of a light-emitting display device using a light-emitting element as the display element.

[0300] As illustrated in FIGS. 14A and 14B, the display device includes a connection terminal electrode 915 and a terminal electrode 916. The connection terminal electrode 915 and the terminal electrode 916 are electrically connected to a terminal included in the FPC 918 through an anisotropic conductive agent 919.

[0301] The connection terminal electrode 915 is formed using the same conductive film as a first electrode 930, and the terminal electrode 916 is formed using the same conductive film as a pair of electrodes in each of a transistor 910 and a transistor 911.

[0302] Each of the pixel portion 902 and the scan line driver circuit 904 which are provided over the first substrate 901 includes a plurality of transistors. FIGS. 14A and 14B illustrate the transistor 910 included in the pixel portion 902 and the transistor 911 included in the scan line driver circuit 904. In FIG. 14A, an insulating film 924 is provided over each of the transistor 910 and the transistor 911, and in FIG. 14B, a planarization film 921 is further provided over the insulating film 924. Note that as a multilayer film 926 including an oxide semiconductor film in each of the transistors 910 and 911, the multilayer film 20 including an oxide semiconductor film described in Embodiment 1 or the multilayer film 34 including an oxide semiconductor film described in Embodiment 2 can be used as appropriate. As the insulating film 924, the protective film 26 described in Embodiment 1 can be used as appropriate. The insulating film 923 is an insulating film serving as a base film.

[0303] In this embodiment, any of the transistors described in the above embodiments can be used as the transistor 910 and the transistor 911 as appropriate. Any of the transistors described in Embodiment 1 to Embodiment 3 is used as the transistors 910 and 911, whereby a display device with high image quality can be fabricated.

[0304] Moreover, FIG. 14B shows an example in which a conductive film 917 is provided over the planarization film 921 so as to overlap with a channel region of the multilayer film 926 of the transistor 911 for the driver circuit. In this embodiment, the conductive film 917 is formed using the conductive film which is used as the first electrode 930. By providing the conductive film 917 so as to overlap with the channel region of the multilayer film 926, the amount of change in the threshold voltage of the transistor 911 between before and after a BT stress test can be further reduced. The conductive film 917 may have the same electric potential as or an electric potential different from that of the gate electrode of the transistor 911, and the conductive film 917 can serve as a second gate electrode. The electric potential of the conductive film 917 may be GND, 0 V, in a floating state, or the same electric potential or substantially the same electric potential as the minimum electric potential (Vss; for example, the electric potential of the source electrode in the case where the electric potential of the source electrode is a reference electric potential) of the driver circuit.

[0305] In addition, the conductive film 917 has a function of blocking an external electric field. In other words, the conductive film 917 has a function of preventing an external electric field (particularly, a function of preventing static electricity) from affecting the inside (a circuit portion including the transistor). Such a blocking function of the conductive film 917 can prevent a change in electrical characteristics of the transistor due to the influence of an external electric field such as static electricity. The conductive film 917 can be used for any of the transistors described in the above embodiments.

[0306] In the display panel, the transistor 910 included in the pixel portion 902 is electrically connected to a display element. There is no particular limitation on the kind of the display element as long as display can be performed, and various kinds of display elements can be used.

[0307] In FIG. 14A, a liquid crystal element 913 which is a display element includes the first electrode 930, a second electrode 931, and a liquid crystal layer 908. Note that an insulating film 932 and an insulating film 933 which serve as alignment films are provided so that the liquid crystal layer 908 is provided therebetween. The second electrode 931 is provided on the second substrate 906 side. The second electrode 931 overlaps with the first electrode 930 with the liquid crystal layer 908 provided therebetween.

[0308] A spacer 935 is a columnar spacer obtained by selective etching of an insulating film and is provided in order to control the distance between the first electrode 930 and the second electrode 931 (a cell gap). Alternatively, a spherical spacer may be used.

[0309] In the case where a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. Such a liquid crystal material exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on a condition.

[0310] Alternatively, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which a chiral material is mixed is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition which includes a liquid crystal showing a blue phase and a chiral material has a short response time of 1 msec or less, and has optical isotropy, which makes the alignment process unneeded and viewing angle dependence small. In addition, since an alignment film does not need to be provided and rubbing treatment is unnecessary, electrostatic discharge damage caused by the rubbing treatment can be prevented and defects and damage of the liquid crystal display device in the manufacturing process can be reduced. Thus, the productivity of the liquid crystal display device can be increased.

[0311] The first substrate 901 and the second substrate 906 are fixed in place by the sealant 925. As the sealant 925, an organic resin such as a thermosetting resin or a photocurable resin can be used.

[0312] Further, the transistor including an oxide semiconductor film used in the above embodiments has excellent switching characteristics. Furthermore, relatively high field-effect mobility is obtained, which enables high-speed operation. Consequently, when the above transistor is used in a pixel portion of a semiconductor device having a display function, high-quality images can be obtained. Since a driver circuit portion and the pixel portion can be formed over one substrate with the use of the above transistor, the number of components of the semiconductor device can be reduced.

[0313] The size of storage capacitor formed in the liquid crystal display device is set considering the leakage current of the transistor provided in the pixel portion or the like so that charge can be held for a predetermined period. By using the transistor including the highly-purified oxide semiconductor film, it is enough to provide a storage capacitor having capacitance that is ⅓ or less, preferably ⅕ or less of liquid crystal capacitance of each pixel; therefore, the aperture ratio of a pixel can be increased.

[0314] In the display device, a black matrix (a light-blocking film), an optical member (an optical substrate) such as a polarizing member, a retardation member, or an anti-reflection member, and the like are provided as appropriate. For example, circular polarization may be obtained by using a polarizing substrate and a retardation substrate. In addition, a backlight, a side light, or the like may be used as a light source.

[0315] As a display method in the pixel portion, a progressive method, an interlace method, or the like can be used. Further, color elements controlled in a pixel at the time of color display are not limited to three colors: R, G, and B (R, G, and B correspond to red, green, and blue, respectively). For example, R, G, B, and W (W corresponds to white), or R, G, B, and one or more of yellow, cyan, magenta, and the like can be used. Further, the sizes of display regions may be different between respective dots of color elements. One embodiment of the present invention is not limited to the application to a display device for color display but can also be applied to a display device for monochrome display.

[0316] In FIG. 14B, a light-emitting element 963 which is a display element is electrically connected to the transistor 910 provided in the pixel portion 902. Note that although the structure of the light-emitting element 963 is a stacked-layer structure of the first electrode 930, a light-emitting layer 961, and the second electrode 931, the structure is not limited thereto. The structure of the light-emitting element 963 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 963, or the like.

[0317] A partition wall 960 can be formed using an organic insulating material or an inorganic insulating material. It is particularly preferred that the partition wall 960 be formed using a photosensitive resin material to have an opening over the first electrode 930 so that a sidewall of the opening has an inclined surface with a continuous curvature.

[0318] The light-emitting layer 961 may be formed to have a single-layer structure or a stacked-layer structure including a plurality of layers.

[0319] A protective layer may be formed over the second electrode 931 and the partition wall 960 in order to prevent oxygen, hydrogen, moisture, carbon dioxide, or the like from entering the light-emitting element 963. As the protective layer, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, a DLC film, or the like can be formed. In addition, in a space which is sealed with the first substrate 901, the second substrate 906, and a sealant 936, a filler 964 is provided and sealed. It is preferred that, in this manner, the light-emitting element be packaged (sealed) with a protective film (such as a laminate film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the panel is not exposed to the outside air.

[0320] As the sealant 936, an organic resin such as a thermosetting resin or a photocurable resin, fritted glass including low-melting glass, or the like can be used. The fritted glass is preferred because of its high barrier property against impurities such as water and oxygen. Further, in the case where the fritted glass is used as the sealant 936, as illustrated in FIG. 14B, the fritted glass is provided over the insulating film 924, whereby adhesion of the insulating film 924 to the fritted glass becomes high, which is preferable.

[0321] As the filler 964, as well as an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used: polyvinyl chloride (PVC), an acrylic resin, polyimide, an epoxy resin, a silicone resin, polyvinyl butyral (PVB), ethylene vinyl acetate (EVA), or the like can be used. For example, nitrogen is used for the filler.

[0322] If necessary, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter may be provided as appropriate for a light-emitting surface of the light-emitting element. Further, a polarizing plate or a circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed.

[0323] The first electrode and the second electrode (each of which may be called a pixel electrode, a common electrode, a counter electrode, or the like) for applying voltage to the display element may have light-transmitting properties or light-reflecting properties, which depends on the direction in which light is extracted, the position where the electrode is provided, and the pattern structure of the electrode.

[0324] The first electrode 930 and the second electrode 931 can be formed using a light-transmitting conductive material such as indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.

[0325] Alternatively, the first electrode 930 and the second electrode 931 can be formed using one or more materials selected from metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag); an alloy of any of these metals; and a nitride of any of these metals.

[0326] The first electrode 930 and the second electrode 931 can be formed using a conductive composition including a conductive macromolecule (also referred to as a conductive polymer). As the conductive high molecule, what is called a π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof, and the like can be given.

[0327] Since the transistor is easily broken owing to static electricity or the like, a protective circuit for protecting the driver circuit is preferred to be provided. The protection circuit is preferred to be formed using a nonlinear element.

[0328] As described above, by using any of the transistors described in the above embodiments, a highly reliable semiconductor device having a display function can be provided.

[0329] Note that the structures, methods, and the like described in this embodiment can be used as appropriate in combination with any of the structures, methods, and the like described in the other embodiments and examples.

(Embodiment 6)

[0330] In this embodiment, a display device (also referred to as a touch panel) provided with a touch sensor (a contact detection device) is described below.

[0331] FIG. 24 is a top view illustrating a structural example of a pixel portion of a display device 900. FIG. 25 is a cross-sectional view taken along dashed-dotted line O-P in FIG. 24. Note that in FIG. 24, some components are not illustrated for clarity. Further, in this embodiment, the reference numerals used in Embodiment 5 are used as appropriate.

[0332] The pixel portion includes at least the transistor 910, a scan line part of which functions as a gate electrode 972, a signal line part of which functions as one electrode 974 of a pair of electrodes 974 and 975, the first electrode 930 serving as a pixel electrode, the second electrode 931 serving as a common electrode, and the spacer 935 (see FIG. 24).

[0333] The transistor 910 includes the gate electrode 972, a gate insulating film 976, the multilayer film 926, the pair of electrodes 974 and 975, and the insulating film 924. The gate electrode 972 is provided over the insulating film 923 serving as a base film over the first substrate 901. The gate insulating film 976 is provided over the gate electrode 972, the multilayer film 926 is provided over the gate insulating film 976 to overlap with the gate electrode 972, the pair of electrodes 974 and 975 is provided over the multilayer film 926, and the insulating film 924 is provided over the multilayer film 926 and the pair of electrodes 974 and 975 (see FIG. 25).

[0334] Further, an organic resin film 945 is provided over the insulating film 924. The second electrode 931 is provided over the organic resin film 945. An insulating film 937 is provided over the organic resin film 945 and the second electrode 931. An opening reaching the electrode 975 is formed in the insulating film 924, the insulating film 937, and the organic resin film 945, and the first electrode 930 is provided in the opening and over the insulating film 937 (see FIG. 25). That is, the first electrode 930 is electrically connected to one of the pair of electrodes 974 and 975.

[0335] Further, the insulating film 932 serving as an alignment film is provided over the insulating film 937 and the first electrode 930. The insulating film 933 serving as an alignment film is provided on a surface of the second substrate 906, which faces the first substrate 901, and the liquid crystal layer 908 is provided between the insulating film 932 and the insulating film 933. In addition to the above components, an optical member may be provided as appropriate. For example, a polarization plate can be provided on the outer side of each of the first substrate 901 and the second substrate 906.

[0336] The display device 900 includes a capacitive sensor as a touch sensor. An electrode 941 is provided on the outer side of the second substrate 906. Note that the polarization plate provided on the outer side of the second substrate 906 is provided between the electrode 941 and the second substrate 906.

[0337] The second electrode 931 on the first substrate 901 side functions as a common electrode of a pixel and one electrode of a capacitor of a touch sensor. The electrode 941 functions as the other electrode of the capacitor of the touch sensor. Further, a pixel portion of the display device 900 applies a pixel structure of the FFS mode; thus, a conductive film is not formed on the second substrate 906 side, so that the electrode 941 functions as a conductor for preventing the second substrate 906 from being charged with electricity.

[0338] The transistor 910 can be formed using a material and a method similar to those of the transistor 50 described in Embodiment 1. That is, the gate electrode 972, the gate insulating film 976, the multilayer film 926, the pair of electrodes 974 and 975, and the insulating film 924 can be formed using a material and a method similar to those of the gate electrode 15, the gate insulating film 17, the multilayer film 20, the pair of electrodes 21 and 22, and the protective film 26, respectively, of the transistor 50 described in Embodiment 1.

[0339] Further, one of or both the signal line driver circuit and the scan line driver circuit of the display device 900 can be formed by using a manufacturing process of the transistor 910. For example, a transistor and a diode which are included in one of or both the signal line driver circuit and the scan line driver circuit, and a lead wiring provided in a terminal portion connected to an FPC and the like, can be formed.

[0340] The organic resin film 945 can be formed using a material and a method applicable to the planarization film 921 or the partition wall 960 which are described in Embodiment 5. The insulating film 937 can be formed using a material and a method applicable to an insulating film (such as the gate insulating film 976 and the insulating film 924) included in the transistor 910.

[0341] One electrode 975 of the pair of electrodes 974 and 975 is in contact with the first electrode 930 through the opening formed in the insulating film 924, the insulating film 937, and the organic resin film 945. The opening can be formed by forming a resist mask through a photolithography process or the like and etching the insulating film 937 and the organic resin film 945 with the use of the resist mask. Specifically, the opening is formed through an etching process of part of the insulating film 924 and part of the organic resin film 945 and an etching process of part of the insulating film 937.

[0342] FIG. 26A shows a cross-sectional view of one example of a connection structure in which the second electrode 931 is connected to a wiring 977 which is electrically connected to the pair of electrodes 974 and 975. The wiring 977 is in contact with the second electrode 931 through an opening formed in the insulating film 924 and the organic resin film 945. With such a structure, an electric potential can be supplied to the second electrode 931 by supplying an electric potential to the wiring 977. Note that the wiring 977 can be formed by using a manufacturing process of the pair of electrodes 974 and 975.

[0343] FIG. 26B shows a cross-sectional view of one example of a connection structure of a wiring in a terminal portion connected to an FPC and the like. An electrode 979 is in contact with the wiring 977 through an opening formed in the insulating film 924 and the organic resin film 945, and is in contact with the wiring 978 through an opening formed in the gate insulating film 976, the insulating film 924, and the organic resin film 945. With such a structure, an electric potential can be supplied to the wiring 977 by supplying an electric potential to the wiring 978. Note that the wiring 978 can be formed by using a manufacturing process of the gate electrode 972.

[0344] As illustrated in FIG. 26B, the wiring 977 is connected to the wiring 978 through the electrode 979, whereby the number of photomasks can be reduced by one as compared to the case where a connection portion in which the wiring 977 is directly in contact with the wiring 978 is formed. It is because, in order to have a connection structure in which the wiring 977 is directly in contact with the wiring 978, a photomask for forming a contact hole in the gate insulating film 976 is needed before the pair of electrodes 974 and 975 is formed; however, the photomask is not needed for the connection structure in FIG. 26B.

[0345] Further, instead of the transistor 910 illustrated in FIG. 25, a transistor 912 illustrated in FIG. 27 is formed using a multi-tone mask, whereby the number of photomasks can be reduced. The multi-tone mask is a mask capable of light exposure with multi-level light intensity, and typically, light exposure is performed with three levels of light intensity to provide an exposed region, a half-exposed region, and an unexposed region. By one light exposure and development step with the use of the multi-tone mask, a resist mask with plural thicknesses (typically, two kinds of thicknesses) can be formed. Therefore, by the usage of the multi-tone mask, the number of photomasks can be reduced. Specifically, the multi-tone mask is used in a forming process of the multilayer film 927 and the pair of electrodes 928 and 929, whereby the one photomask can be cut. With the multi-tone mask, end portions of the multilayer film 927 are positioned on the outer side than end portions of the pair of electrodes 928 and 929.

[0346] FIG. 28 is a plan view showing a structural example of the second electrode 931 and the electrode 941 which are included in the display device 900. As illustrated in FIG. 28, the second electrode 931 and the electrode 941 each have a stripe shape, and are provided so as to be perpendicular to each other in a plane. Each second electrode 931 is connected to an FPC 954 attached to the substrate 901, through a lead wiring 951, and each electrode 941 is connected to an FPC 955 attached to the substrate 906, through a lead wiring 952.

[0347] FIG. 29A is a cross-sectional view taken along dashed-dotted line Q-R in FIG. 28 and FIG. 29B is a plan view of a region 953 in FIG. 28. As illustrated in FIG. 29A, the second electrode 931 is provided in common in a plurality of pixels, and the first electrode 930 is provided in each of the pixels and connected to the transistor 910. An electrostatic capacitor of a touch sensor is formed in a region where the second electrode 931 and the electrode 941 intersect with each other. The electrostatic capacitor is composed of the second electrode 931, the electrode 941, and a dielectric provided between the second electrode 931 and the electrode 941. The second electrode 931 is an electrode for supplying an electric potential to the electrostatic capacitor. The electrode 941 is an electrode for extracting current flowing in the electrostatic capacitor.

[0348] An operation of the display device 900 can be roughly divided into a display operation in which an image signal is input to the pixel and a sensing operation in which a touch is detected. In the display operation, an electric potential of the second electrode 931 is fixed at a low level. In a sensing period, pulse signals are sequentially applied to each second electrode 931 and the electric potential is a high level. At this time, if a finger is touching the display device 900, capacitance formed by the touch with the finger is applied to the electrostatic capacitor of the touch sensor; thus, current flowing in the capacitor is changed and the electric potential of the electrode 941 is changed. The electrodes 941 are sequentially scanned and the change in the electric potential of the electrode 941 is detected, whereby the location of the touch with the finger is detected.

[0349] As described above, in a display device including a liquid crystal element, as an electrode forming capacitance of the display device 900, a common electrode of the pixel and the conductor for preventing the second substrate 906 from being charged with electricity originally provided in a liquid crystal device of the FFS mode can be used; thus, a touch panel that is light and thin and with a high display quality can be provided.

[0350] Here, the second electrode 931 serving as a common electrode is provided below the first electrode 930 serving as a pixel electrode (on the first substrate 901 side); however, the second electrode 931 serving as a common electrode can be provided over the first electrode 930 serving as a pixel electrode.

[0351] Note that as the structure of the display device, a structure except the display device 900 described in this embodiment may be used. For example, an externally attached touch panel can be employed, in which capacitance is formed and a touch panel substrate is attached to the first substrate 901 side or the second substrate 906 side of a liquid crystal display device or a light-emitting display device. Further, with a conductive film which is attached outside the first substrate 901 or the second substrate 906 to prevent build-up of static electricity, a surface capacitive touch sensor can be formed. Hereinafter, a structural example of the touch sensor which is applied to the externally attached touch panel is described with reference to FIGS. 30A to 30C and FIGS. 31A and 31B.

[0352] FIG. 30A is an exploded perspective view showing a structural example of the touch sensor, FIG. 30B is a plan view showing a structural example of an electrode 981 of the touch sensor, and FIG. 30C is a plan view showing a structural example of an electrode 982 of the touch sensor.

[0353] As illustrated in FIGS. 30A to 30C, in a touch sensor 980, a plurality of electrodes 981 arranged in the X-axis direction and a plurality of electrodes 982 arranged in the Y-axis direction which intersects with the X-axis direction are formed over a substrate 986.

[0354] The electrodes 981 and the electrodes 982 each have a structure in which a plurality of quadrangular conductive films is connected to each other. The plurality of electrodes 981 and the plurality of electrodes 982 are each provided so that the quadrangular conductive films are not overlapped with each other. In a portion where the electrode 981 and the electrode 982 intersect with each other, an insulating film is provided between the electrode 981 and the electrode 982 so that the electrode 981 and the electrode 982 are not in contact with each other.

[0355] FIG. 31A is a cross-sectional view illustrating an example of connection structures of the electrode 981 and the electrode 982 and shows a cross-sectional view of a portion where the electrodes 981 and 982 intersect with each other as an example. FIG. 31B is an equivalent circuit diagram of the portion where the electrodes 981 and 982 intersect with each other. As illustrated in FIG. 31B, in the portion where the electrodes 981 and 982 intersect with each other, a capacitor 983 is formed.

[0356] As illustrated in FIG. 31A, in a sensor portion 989, the electrode 981 includes a conductive film 981a and a conductive film 981b which are in the first layer, and a conductive film 981c in the second layer over an insulating film 985. The conductive films 981a and 981b are connected to each other via the conductive film 981c. The electrode 982 is formed using the conductive film in the first layer. An insulating film 991 is formed to cover the electrode 981, the electrode 982, an electrode 984, and the insulating film 985. As the insulating films 985 and 991, for example, a silicon oxide film, a silicon oxynitride film, or the like may be used. Note that a base insulating film may be formed between the substrate 986 and the electrode 981 and between the substrate 986 and the electrode 984. As the base insulating film, for example, a silicon oxide film, a silicon oxynitride film, or the like can be used.

[0357] The electrodes 981 and 982 are formed using a conductive material having a light-transmitting property with respect to visible light. For example, as the conductive material having a light-transmitting property, indium tin oxide containing silicon oxide, indium tin oxide, zinc oxide, indium zinc oxide, and zinc oxide to which gallium is added are given.

[0358] The conductive film 981a is connected to the electrode 984 in a terminal portion 990. A terminal for connecting to the FPC is formed using the electrode 984. The electrode 982 is also connected to other electrode 984 like the electrode 981. The electrode 984 can be formed using a tungsten film, for example.

[0359] An opening is formed in the insulating film 985 and the insulating film 991 which are over the electrode 984 for electrically connecting the electrode 984 and the FPC. A substrate 987 is attached to and over the insulating film 991 using an adhesive, an adhesive film, or the like. The substrate 986 is attached to the first substrate 901 or the second substrate 906 of the display device using an adhesive or an adhesive film, whereby a touch panel is formed.

[0360] Note that the structures, methods, and the like described in this embodiment can be used as appropriate in combination with any of the structures, methods, and the like described in the other embodiments and examples.

(Embodiment 7)

[0361] In this embodiment, a driving method for reducing power consumption of a display device is described. By using the driving method in this embodiment, power consumption of a display device including an oxide semiconductor transistor in a pixel can be further reduced. With reference to FIGS. 33 and 34, low power consumption of a liquid crystal display device, which is an example of the display device, is described below.

[0362] FIG. 33 is a block diagram illustrating a structural example of a liquid crystal display device in this embodiment. As shown in FIG. 33, a liquid crystal display device 500 includes a liquid crystal panel 501 as a display module, a control circuit 510, and a counter circuit.

[0363] An image signal (Video), which is digital data, and a synchronization signal (SYNC) for controlling rewriting of a screen of the liquid crystal panel 501 are input to the liquid crystal display device 500. Examples of a synchronization signal include a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a reference clock signal (CLK).

[0364] The liquid crystal panel 501 includes a display portion 530, a scan line driver circuit 540, and a data line driver circuit 550. The display portion 530 includes a plurality of pixels 531. The pixels 531 in the same row are connected to the scan line driver circuit 540 through a common scan line 541, and the pixels 531 in the same column are connected to the data line driver circuit 550 through a common data line 551.

[0365] A high power supply voltage (VDD) and a low power supply voltage (VSS), which serve as power supply voltages, and a common voltage (hereinafter referred to as Vcom) are supplied to the liquid crystal panel 501. The common voltage (Vcom) is supplied to each pixel 531 in the display portion 530.

[0366] The data line driver circuit 550 processes an input image signal to generate a data signal, and outputs the data signal to the data line 551. The scan line driver circuit 540 outputs, to the scan line 541, a scan signal for selecting the pixel 531 into which a data signal is to be written.

[0367] The pixel 531 includes a switching element whose electrical connection to the data line 551 is controlled by a scan signal. When the switching element is turned on, a data signal is written into the pixel 531 through the data line 551.

[0368] An electrode to which Vcom is applied corresponds to a common electrode.

[0369] The control circuit 510 controls the whole liquid crystal display device 500 and includes a circuit which generates control signals for circuits included in the liquid crystal display device 500.

[0370] The control circuit 510 includes a control circuit generation circuit which generates control signals for the scan line driver circuit 540 and the data line driver circuit 550 on the basis of the synchronization signal (SYNC). Examples of a control signal for the scan line driver circuit 540 include a start pulse (GSP) and a clock signal (GCLK). Examples of a control signal for the data line driver circuit 550 include a start pulse (SSP) and a clock signal (SCLK). For example, the control circuit 510 generates a plurality of clock signals with the same cycle and shifted phases as the clock signals (GCLK and SCLK).

[0371] Further, the control circuit 510 controls output of an image signal (Video), which is input from the outside of the liquid crystal display device 500, to the data line driver circuit 550.

[0372] The data line driver circuit 550 includes a digital/analog conversion circuit (hereinafter referred to as a D-A conversion circuit 552). The D-A conversion circuit 552 converts an image signal to an analog signal, thereby generating a data signal.

[0373] Note that in the case where an image signal input to the liquid crystal display device 500 is an analog signal, the image signal is converted to a digital signal in the control circuit 510 and output to the liquid crystal panel 501.

[0374] An image signal is image data for each frame. The control circuit 510 has a function of performing image processing on the image signal and controlling output of the image signal to the data line driver circuit 550 on the basis of data obtained by the processing. For that function, the control circuit 510 includes a motion detection portion 511 which detects motion in the image data for each frame. The control circuit 510 stops output of an image signal to the data line driver circuit 550 when the motion detection portion 511 determines that there is no motion, and restarts the output of an image signal when the motion detection portion 511 determines that there is motion.

[0375] There is no particular limitation on the image processing for detecting motion which is performed in the motion detection portion 511. An example of a method for detecting motion is to obtain difference data from image data for two consecutive frames. It can be determined whether there is motion or not from the obtained difference data. Another example of the method is to detect a motion vector.

[0376] In addition, the liquid crystal display device 500 may be provided with an image signal correction circuit which corrects an input image signal. For example, an image signal is corrected such that a voltage higher than a voltage corresponding to the gray scale of the image signal is written into the pixel 531. Such correction can shorten the response time of the liquid crystal element. A method in which the control circuit 510 is driven with an image signal corrected in this manner is referred to as overdriving. In the case of performing high frame rate driving in which the liquid crystal display device 500 is driven at an integral multiple of the frame frequency of an image signal, image data for interpolation between two frames or image data for performing black display between two frames may be generated in the control circuit 510.

[0377] Hereinafter, the operation of the liquid crystal display device 500 for displaying an image with motion, such as a moving image, and an image without motion, such as a still image, is described with reference to a timing chart in FIG. 34. FIG. 34 shows the signal waveforms of a vertical synchronization signal (Vsync) and a data signal (Vdata) output to the data line 551 from the data line driver circuit 550.

[0378] FIG. 34 is a timing chart of the liquid crystal display device 500 during 3 m frame periods. Here, there is motion in image data in the first k frame periods and the last j frame periods and there is no motion in image data in the other frame periods. Note that k and j are each an integer greater than or equal to 1 and less than or equal to m−2.

[0379] In the first k frame periods, the motion detection portion 511 determines that there is motion in image data for each frame. The control circuit 510 outputs data signals (Vdata) to the data line 551 on the basis of the result of determination by the motion detection portion 511.

[0380] The motion detection portion 511 performs image processing for detecting motion and determines that there is no motion in image data for the (k+1)-th frame. Then, the control circuit 510 stops output of image signals (Video) to the data line driver circuit 550 in the (k+1)-th frame period on the basis of the result of determination by the motion detection portion 511. Thus, output of the data signal (Vdata) from the data line driver circuit 550 to the data line 551 is stopped. Further, the control circuit 510 stops the supply of control signals (e.g., a start pulse signal and a clock signal) to the scan line driver circuit 540 and the data line driver circuit 550 in order to stop rewriting data in the display portion 530. The control circuit 510 does not output an image signal to the data line driver circuit 550 nor output control signals to the scan line driver circuit 540 and the data line driver circuit 550, thereby keeping rewriting of the display portion 530 stopped, until the motion detection portion 511 determines that there is motion in image data.

[0381] Note that, in this specification, “not to supply” a signal to a liquid crystal panel means to apply voltage which is different from a predetermined voltage for operating a circuit to a wiring for supplying the signal, or to bring the wiring into an electrically floating state.

[0382] When rewriting of the display portion 530 is stopped, an electric field in one direction is kept applied to the liquid crystal element, which might lead to deterioration of liquid crystal in the liquid crystal element. In the case where such a problem is likely to occur, it is preferable that signals be supplied to the scan line driver circuit 540 and the data line driver circuit 550 from the control circuit 510 and data signals with an inverted polarity be written into the data line 551 at predetermined timings to invert the direction of the electric field applied to the liquid crystal element, regardless of the result of determination by the motion detection portion 511.

[0383] Note that the polarity of a data signal input to the data line 551 is determined relative to Vcom. The polarity is positive when the voltage of the data signal is higher than Vcom, and is negative when the voltage of the data signal is lower than Vcom.

[0384] Specifically, as shown in FIG. 34, in the (m+1)-th frame period, the control circuit 510 outputs control signals to the scan line driver circuit 540 and the data line driver circuit 550 and outputs, an image signal (Video) to the data line driver circuit 550. The data line driver circuit 550 outputs, to the data line 551, a data signal (Vdata) which has an inverted polarity with respect to a data signal (Vdata) output to the data line 551 in the k-th frame period. In this manner, a data signal (Vdata) with an inverted polarity is written into the data line 551 in the (m+1)-th frame period and in the (2 m+1)-th frame period, which are periods in which no motion is detected in image data. Rewriting of the display portion 530 is intermittently performed in periods in which there is no change in image data; thus, it is possible to reduce power consumption due to rewriting and prevent deterioration of the liquid crystal element.

[0385] When the motion detection portion 511 determines that there is motion in image data for any frame after the (2 m+1)-th frame, the control circuit 510 controls the scan line driver circuit 540 and the data line driver circuit 550 to perform rewriting of the display portion 530.

[0386] As described above, with the driving method in FIG. 34, the polarity of a data signal (Vdata) is inverted every m frame periods regardless of whether there is motion in image data (Video) or not. Meanwhile, the display portion 530 is rewritten every frame in periods in which an image with motion is displayed and is rewritten every m frames in periods in which an image without motion is displayed. Consequently, power consumed owing to rewriting of the display portion can be reduced. This can prevent an increase in power consumption due to an increase in driving frequency and the number of pixels.

[0387] As described above, in the liquid crystal device 500, the method for driving the liquid crystal display device is switched between in a moving image display mode and in a still image display mode; thus, it is possible to provide a liquid crystal display device with low power consumption while inhibiting deterioration of liquid crystal and maintaining display quality.

[0388] In the case where a still image is displayed, when a pixel is rewritten every one frame, human eyes perceive the rewriting of the pixel as flickers in some cases, which causes eyestrain. The pixel is not frequently rewritten in the display period of the still image in the liquid crystal device of this embodiment, which is effective for causing less eyestrain.

[0389] Thus, with the use of a liquid crystal panel in which a backplane is formed using an oxide semiconductor transistor, a middle size liquid crystal display device with high resolution and low power consumption, which is very suitable for a portable electronic device, can be provided.

[0390] Note that, in order to prevent deterioration of the liquid crystal, the interval between polarity inversions of data signals (here, m frame periods) is set to two seconds or shorter, preferably one second or shorter.

[0391] Although the detection of motion in image data is performed in the motion detection portion 511 in the control circuit 510, the detection of motion is not necessarily performed only in the motion detection portion 511. Data on whether there is motion or not may be input to the control circuit 510 from the outside of the liquid crystal display device 500.

[0392] Determination that there is no motion in image data is not always based on image data for two consecutive frames; the number of frames required for the determination may be set as appropriate depending on the usage mode of the liquid crystal display device 500. For example, rewriting of the display portion 530 may be stopped when there is no motion in image data for m consecutive frames.

[0393] Note that the structures, methods, and the like described in this embodiment can be used as appropriate in combination with any of the structures, methods, and the like described in the other embodiments and examples.

(Embodiment 8)

[0394] The semiconductor device which is one embodiment of the present invention can be applied to a variety of electronic appliances (including game machines). Examples of electronic appliances include a television device (also referred to as television or television receiver), a monitor of a computer or the like, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, an audio reproducing device, a game machine (e.g., a pachinko machine or a slot machine), and a game console, and the like. Examples of these electronic appliances are illustrated in FIGS. 15A to 15C.

[0395] FIG. 15A illustrates a table 9000 having a display portion. In the table 9000, a display portion 9003 is incorporated in a housing 9001 and an image can be displayed on the display portion 9003. The housing 9001 is supported by four leg portions 9002. Further, a power cord 9005 for supplying power is provided for the housing 9001.

[0396] The semiconductor device described in any of the above embodiments can be used for the display portion 9003. Thus, the display portion 9003 can have high display quality.

[0397] The display portion 9003 has a touch-input function. When a user touches displayed buttons 9004 which are displayed on the display portion 9003 of the table 9000 with his/her fingers or the like, the user can carry out operation of the screen and input of information. Further, when the table may be made to communicate with home appliances or control the home appliances, the display portion 9003 may function as a control device which controls the home appliances by operation on the screen. For example, with the use of the semiconductor device having an image sensor function, the display portion 9003 can have a touch-input function.

[0398] Further, the screen of the display portion 9003 can be placed perpendicular to a floor with a hinge provided for the housing 9001; thus, the table 9000 can also be used as a television device. When a television device having a large screen is set in a small room, an open space is reduced; however, when a display portion is incorporated in a table, a space in the room can be efficiently used.

[0399] FIG. 15B illustrates a television device 9100. In the television device 9100, a display portion 9103 is incorporated in a housing 9101 and an image can be displayed on the display portion 9103. Note that the housing 9101 is supported by a stand 9105 here.

[0400] The television device 9100 can be operated with an operation switch of the housing 9101 or a separate remote controller 9110. Channels and volume can be controlled with an operation key 9109 of the remote controller 9110 so that an image displayed on the display portion 9103 can be controlled. Furthermore, the remote controller 9110 may be provided with a display portion 9107 for displaying data output from the remote controller 9110.

[0401] The television device 9100 illustrated in FIG. 15B is provided with a receiver, a modem, and the like. With the receiver, general television broadcasts can be received in the television device 9100. Further, when the television device 9100 is connected to a communication network by wired or wireless connection via the modem, one-way (from a transmitter to a receiver) or two-way (between a transmitter and a receiver or between receivers) data communication can be performed.

[0402] Any of the semiconductor devices described in the above embodiments can be used for the display portions 9103 and 9107. Thus, the television device can have high display quality.

[0403] FIG. 15C illustrates a computer 9200, which includes a main body 9201, a housing 9202, a display portion 9203, a keyboard 9204, an external connection port 9205, a pointing device 9206, and the like.

[0404] Any of the semiconductor devices described in the above embodiments can be used for the display portion 9203. Thus, the computer 9200 can have high display quality.

[0405] The display portion 9203 has a touch-input function. When a user touches displayed buttons which are displayed on the display portion 9203 of the computer 9200 with his/her fingers or the like, the user can carry out operation of the screen and input of information. Further, when the computer may be made to communicate with home appliances or control the home appliances, the display portion 9203 may function as a control device which controls the home appliances by operation on the screen.

[0406] FIGS. 16A and 16B illustrate a foldable tablet terminal. In FIG. 16A, the tablet terminal is opened and includes a housing 9630, a display portion 9631a, a display portion 9631b, a display-mode switching button 9034, a power button 9035, a power-saving-mode switching button 9036, a clip 9033, and an operation button 9038.

[0407] Any of the semiconductor devices described in the above embodiments can be used for the display portion 9631a and the display portion 9631b. Thus, the display quality of the tablet terminal can be improved.

[0408] Part of the display portion 9631a can be a touch panel region 9632a and data can be input when a displayed operation key 9638 is touched. Although a structure in which a half region in the display portion 9631a has only a display function and the other half region also has a touch panel function is illustrated as an example, the structure of the display portion 9631a is not limited thereto. The whole area of the display portion 9631a may have a touch screen function. For example, the while area of the display portion 9631a can display keyboard buttons and serve as a touch screen while the display portion 9631b can be used as a display screen.

[0409] Like the display portion 9631a, part of the display portion 9631b can be a touch screen region 9632b. When a keyboard display switching button 9639 displayed on the touch panel is touched with a finger, a stylus, or the like, a keyboard can be displayed on the display portion 9631b.

[0410] Touch input can be performed concurrently on the touch screen regions 9632a and 9632b.

[0411] The display-mode switching button 9034 can switch display orientation (e.g., between landscape mode and portrait mode) and select a display mode (switch between monochrome display and color display), for example. The power-saving-mode switching button 9036 can control display luminance in accordance with the amount of external light in use of the tablet terminal detected by an optical sensor incorporated in the tablet. The tablet terminal may include another detection device such as a sensor for detecting orientation (e.g., a gyroscope or an acceleration sensor) in addition to the optical sensor.

[0412] Although the display portion 9631a and the display portion 9631b have the same display area in FIG. 16A, one embodiment of the present invention is not limited to this example. The display portion 9631a and the display portion 9631b may have different areas or different display quality. For example, one of them may be a display panel that can display higher-definition images than the other.

[0413] In FIG. 16B, the tablet terminal is folded and includes the housing 9630, a solar cell 9633, and a charge and discharge control circuit 9634. Note that in FIG. 16B, an example in which the charge and discharge control circuit 9634 includes the battery 9635 and the DCDC converter 9636 is illustrated.

[0414] Since the tablet can be folded in two, the housing 9630 can be closed when not in use. Thus, the display portions 9631a and 9631b can be protected, thereby providing a tablet with high endurance and high reliability for long-term use.

[0415] In addition, the tablet terminal illustrated in FIGS. 16A and 16B can have a function of displaying various kinds of data (e.g., a still image, a moving image, and a text image), a function of displaying a calendar, a date, the time, or the like on the display portion, a touch-input function of operating or editing the data displayed on the display portion by touch input, a function of controlling processing by a variety of kinds of software (programs), and the like.

[0416] The solar cell 9633, which is attached on the surface of the tablet terminal, supplies electric power to a touch screen, a display portion, an image signal processor, and the like. Note that the solar cell 9633 can be provided on one or both surfaces of the housing 9630, so that the battery 9635 can be charged efficiently. The use of a lithium ion battery as the battery 9635 is advantageous in downsizing or the like.

[0417] The structure and operation of the charge and discharge control circuit 9634 illustrated in FIG. 16B are described with reference to a block diagram of FIG. 16C. The solar cell 9633, the battery 9635, the DCDC converter 9636, a converter 9637, switches SW1 to SW3, and the display portion 9631 are shown in FIG. 16C, and the battery 9635, the DCDC converter 9636, the converter 9637, and the switches SW1 to SW3 correspond to the charge/discharge control circuit 9634 in FIG. 16B.

[0418] First, an example of the operation in the case where power is generated by the solar cell 9633 using external light is described. The voltage of power generated by the solar battery is raised or lowered by the DCDC converter 9636 so that the power has a voltage for charging the battery 9635. Then, when the power from the solar cell 9633 is used for the operation of the display portion 9631, the switch SW1 is turned on and the voltage of the power is raised or lowered by the converter 9637 so as to be a voltage needed for the display portion 9631. In addition, when display on the display portion 9631 is not performed, the switch SW1 is turned off and a switch SW2 is turned on so that charge of the battery 9635 may be performed.

[0419] Note that the solar cell 9633 is described as an example of a power generation means; however, without limitation thereon, the battery 9635 may be charged using another power generation means such as a piezoelectric element or a thermoelectric conversion element (Peltier element). For example, the battery 9635 may be charged with a non-contact power transmission module that transmits and receives power wirelessly (without contact) to charge the battery or with a combination of other charging means.

[0420] Note that the structures and the like described in this embodiment can be combined as appropriate with any of the structures and the like described in the other embodiments.

Example 1

[0421] In this example, measurement results of Vg-Id characteristics and a BT photostress test of a transistor are described.

[0422] First of all, a manufacturing process of a transistor included in a sample 1 is described. In this example, the process is described with reference to FIGS. 3A to 3D.

[0423] First, as illustrated in FIG. 3A, a glass substrate was used as the substrate 11, and the gate electrode 15 was formed over the substrate 11.

[0424] A 100-nm-thick tungsten film was formed by a sputtering method, a mask was formed over the tungsten film by a photolithography process, and part of the tungsten film was etched with the use of the mask, so that the gate electrode 15 was formed.

[0425] Next, the gate insulating film 17 was formed over the gate electrode 15.

[0426] The gate insulating film was formed by stacking a 50-nm-thick first silicon nitride film, a 300-nm-thick second silicon nitride film, a 50-nm-thick third silicon nitride film, and a 50-nm-thick silicon oxynitride film.

[0427] The first silicon nitride film was formed under the following conditions: silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia with a flow rate of 100 sccm were supplied to a treatment chamber of a plasma CVD apparatus as the source gas; the pressure in the treatment chamber was controlled to 100 Pa, and the power of 2000 W was supplied with the use of a 27.12 MHz high-frequency power source.

[0428] Next, the second silicon nitride film was formed under the conditions which are different from the conditions of the source gas of the first silicon nitride film in that the flow rate of ammonia was 2000 sccm.

[0429] Next, the third silicon nitride film was formed under the following conditions: silane with a flow rate of 200 sccm and nitrogen with a flow rate of 5000 sccm were supplied to the treatment chamber of the plasma CVD apparatus as the source gas; the pressure in the treatment chamber was controlled to 100 Pa, and the power of 2000 W was supplied with the use of a 27.12 MHz high-frequency power source.

[0430] Next, the silicon oxynitride film was formed under the following conditions: silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sccm were supplied to the treatment chamber of the plasma CVD apparatus as the source gas; the pressure in the treatment chamber was controlled to 40 Pa, and the power of 100 W was supplied with the use of a 27.12 MHz high-frequency power source.

[0431] In each of the forming processes of the first to third silicon nitride films and the silicon oxynitride film, the substrate temperature was 350° C.

[0432] Next, the multilayer film 20 overlapping with the gate electrode 15 with the gate insulating film 17 provided therebetween was formed.

[0433] Here, as the oxide semiconductor film 18, a 35-nm-thick first In—Ga—Zn oxide film was formed over the gate insulating film 17 by a sputtering method, and then as the oxide film 19 containing In or Ga, a 20-nm-thick second In—Ga—Zn oxide film was formed over the oxide semiconductor film 18. Next, a mask was formed over the oxide film 19 containing In or Ga by a photolithography process, and the oxide semiconductor film 18 and the oxide film 19 containing In or Ga were partly etched using the mask. Then, the etched oxide semiconductor film 18 and the etched oxide film 19 containing In or Ga were subjected to heat treatment, so that the multilayer film 20 was formed.

[0434] The first In—Ga—Zn oxide film was formed under the following conditions: a sputtering target where In:Ga:Zn=1:1:1 (atomic ratio) was used; argon with a flow rate of 50 sccm and oxygen with a flow rate of 50 sccm were supplied as a sputtering gas into a treatment chamber of a sputtering apparatus; the pressure in the treatment chamber was controlled to 0.6 Pa; and a direct-current power of 5 kW was supplied. Note that the first In—Ga—Zn oxide film was formed at a substrate temperature of 170° C.

[0435] The second In—Ga—Zn oxide film was formed under the following conditions: a sputtering target where In:Ga:Zn=1:3:2 (atomic ratio) was used; argon with a flow rate of 90 sccm and oxygen with a flow rate of 10 sccm were supplied as a sputtering gas into the treatment chamber of the sputtering apparatus; the pressure in the treatment chamber was controlled to 0.3 Pa; and a direct-current power of 5 kW was supplied. Note that the second In—Ga—Zn oxide film was formed at a substrate temperature of 25° C.

[0436] As the heat treatment, heat treatment at 450° C. under a nitrogen atmosphere for one hour and then heat treatment at 450° C. under a mixed atmosphere of nitrogen and oxygen for one hour were performed.

[0437] FIG. 3B can be referred to for the structure obtained through the steps up to here.

[0438] Next, after the gate electrode was exposed by partly etching the gate insulating film 17 (this step is not illustrated), the pair of electrodes 21 and 22 in contact with the multilayer film 20 was formed as illustrated in FIG. 3C.

[0439] Here, a conductive film was formed over the gate insulating film 17 and the multilayer film 20. As the conductive film, a 400-nm-thick aluminum film was formed over a 50-nm-thick tungsten film, and a 100-nm-thick titanium film was formed over the aluminum film. Then, a mask was formed over the conductive film by a photolithography process, and part of the conductive film was etched with the use of the mask, whereby the pair of electrodes 21 and 22 was formed.

[0440] Next, after the substrate was moved to a treatment chamber under reduced pressure and heated at 220° C., the substrate was moved to a treatment chamber filled with dinitrogen monoxide. Then, the multilayer film 20 was exposed to oxygen plasma which was generated by decomposition of dinitrogen monoxide in such a manner that an upper electrode provided in the treatment chamber was supplied with high-frequency power of 150 W with the use of a 27.12 MHz high-frequency power source.

[0441] Next, the protective film 26 was formed over the multilayer film 20 and the pair of electrodes 21 and 22 (see FIG. 3D). Here, as the protective film 26, the oxide insulating film 24 and the nitride insulating film 25 were formed.

[0442] First, the oxide insulating film 24 was formed in succession without exposure to the atmosphere after the above plasma treatment. A 400-nm-thick silicon oxynitride film was formed as the oxide insulating film 24.

[0443] The oxide insulating film 24 was formed by a plasma CVD method under the following conditions: silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 4000 sccm were used as a source gas, the pressure in the treatment chamber was 200 Pa, the substrate temperature was 220° C., and the high-frequency power of 1500 W was supplied to parallel plate electrodes. Under the above conditions, it is possible to form a silicon oxynitride film containing oxygen at a higher proportion than oxygen in the stoichiometric composition and from which part of oxygen is released by heating.

[0444] Next, water, nitrogen, hydrogen, and the like contained in the oxide insulating film 24 were released by heat treatment. Here, the heat treatment was performed in an atmosphere of nitrogen and oxygen at 350° C. for one hour.

[0445] Next, the substrate was transferred to a treatment chamber under reduced pressure and heated at 350° C., and the nitride insulating film 25 was formed over the oxide insulating film 24. Here, as the nitride insulating film 25, a 100-nm-thick silicon nitride film was formed.

[0446] The nitride insulating film 25 was formed by a plasma CVD method under the following conditions: silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and ammonia with a flow rate of 100 sccm were used as a source gas, the pressure in the treatment chamber was 100 Pa, the substrate temperature was 350° C., and the high-frequency power of 1000 W was supplied to parallel plate electrodes.

[0447] Next, although not illustrated, an opening which exposes part of the pair of electrodes 21 and 22 was formed by partly etching the oxide insulating film 24 and the nitride insulating film 25.

[0448] Next, a planarization film was formed (not illustrated) over the nitride insulating film 25. Here, the nitride insulating film 25 was coated with a composition, and exposure and development were performed, so that a planarization film having an opening through which the pair of electrodes is partly exposed was formed. Note that as the planarization film, a 1.5-μm-thick acrylic resin was formed. Then, heat treatment was performed. The heat treatment was performed at a temperature of 250° C. in an atmosphere containing nitrogen for one hour.

[0449] Next, a conductive film connected to part of the pair of electrodes was formed (not illustrated). Here, a 100-nm-thick ITO film containing silicon oxide was formed by a sputtering method. After that, heat treatment was performed at 250° C. in a nitrogen atmosphere for one hour.

[0450] Through the above process, the sample 1 including a transistor was formed.

[0451] Further, a sample including a transistor which is different from the transistor of the sample 1 in that the oxide film 19 containing In or Ga is not formed was formed as a sample 2. Note that after the pair of electrodes 21 and 22 was formed, a surface of the oxide semiconductor film 18 was subjected to cleaning using a phosphoric acid solution in which 85% phosphoric acid was diluted by 100 times.

[0452] Next, initial Vg-Id characteristics of the transistors included in the sample 1 and the sample 2 were measured. Here, change in characteristics of current flowing between a source electrode and a drain electrode (hereinafter referred to as the drain current), that is, Vg-Id characteristics were measured under the following conditions: the substrate temperature was 25° C., the electric potential difference between the source electrode and the drain electrode (hereinafter referred to as the drain voltage) was 1 V or 10 V, and the electric potential difference between the source electrode and the gate electrode (hereinafter referred to as the gate voltage) were changed from −20 V to +15 V.

[0453] FIG. 17A shows initial Vg-Id characteristics of the transistors included in the sample 1, and FIG. 17B shows initial Vg-Id characteristics of the transistors included in the sample 2. In FIGS. 17A and 17B, the horizontal axis indicates the gate voltage Vg and the vertical axis indicates the drain current Id. Further, the solid lines indicate the Vg-Id characteristics at the drain voltages Vd of 1 V and 10 V, and the dashed line indicates the field-effect mobility with respect to the gate voltages at the drain voltage Vd of 10 V. Note that the field-effect mobility was obtained by operation of each sample in a saturation region.

[0454] Note that in each of the transistors, the channel length (L) is 6 μm and the channel width (W) is 50 μm. Further, in each of the samples, 20 transistors having the same structure were formed on the substrate.

[0455] According to FIG. 17B, in the Vg-Id characteristics of the transistors included in the sample 2, gate voltage at which on-state current starts flowing (also referred to as rising gate voltage (Vg)) when a drain voltage Vd is 1 V is different from rising gate voltage of the on-state current when a drain voltage Vd is 10 V. Further, variation in the Vg-Id characteristics of the transistors included in the sample 2 is large. On the other hand, according to FIG. 17A, in the Vg-Id characteristics of the transistors included in the sample 1, the rising gate voltage (Vg) of the on-state current at the drain voltage Vd of 1 V and the rising gate voltage (Vg) of the on-state current at the drain voltage Vd of 10 V are substantially the same. Moreover, variation in the Vg-Id characteristics of the transistors included in the sample 1 is small. Thus, the structure in which the oxide semiconductor film 18 is not directly in contact with the oxide insulating film 24 is employed; specifically the oxide film 19 containing In or Ga is provided between the oxide semiconductor film 18 and the oxide insulating film 24, whereby the initial characteristics of the transistor are improved.

[0456] Next, a BT stress test and a BT photostress test were performed on each of the samples 1 and 2. Here, the BT stress test in which the predetermined voltage was applied to the gate electrode was performed under the following conditions: the substrate temperature was 80° C., the intensity of an electric field applied to the gate insulating film was 0.66 MV/cm, and the application time was 2000 seconds. Note that the BT stress test was performed in an air atmosphere in which the dew-point temperature is 12° C.

[0457] Under conditions similar to those of the above BT stress test, the BT photostress test in which the transistor is irradiated with white LED light with 3000 1× to apply the predetermined voltage to the gate electrode was performed. Note that the BT photostress test was performed in a dry-air atmosphere in which the dew-point temperature is −30° C.

[0458] Here, a measurement method of the BT stress test is described. First, as described above, initial Vg-Id characteristics of the transistor were measured.

[0459] Next, the substrate temperature was raised to 80° C., and then, the electric potentials of the source electrode and the drain electrode of the transistor were set to 0 V. Then, voltage was kept being applied to the gate electrode for 2000 seconds so that the intensity of the electric field applied to the gate insulating film was 0.66 MV/cm.

[0460] Note that in a negative BT stress test (dark, −GBT), a voltage of −30 V was applied to the gate electrode, and in a positive BT stress test (dark, +GBT), a voltage of 30 V was applied to the gate electrode. In a negative BT photostress test (photo, −GBT), a voltage of −30 V was applied to the gate electrode while the transistor was irradiated with white LED light with 3000 lx. In a positive BT photostress test (photo, +GBT), a voltage of 30 V was applied to the gate electrode while the transistor was irradiated with white LED light with 3000 lx.

[0461] Next, the substrate temperature was lowered to 25° C. while voltage was continuously applied to the gate electrode, and the source electrode and the drain electrode. After the substrate temperature reached to 25° C., the application of voltage to the gate electrode, and the source electrode and the drain electrode was stopped.

[0462] Further, FIG. 18 shows, in the samples 1 and 2, a difference between a threshold voltage in the initial characteristics of the transistors and a threshold voltage after BT stress tests (i.e., the amount of change of the threshold voltage (ΔVth)). FIG. 18 shows the amounts of change of the threshold voltage (ΔVth) in the positive BT stress test (dark, +GBT), the negative BT stress test (dark, −GBT), the positive BT photostress test (photo, +GBT), and the negative BT photostress test (photo, −GBT).

[0463] In this specification, in a curve (not illustrated) where the horizontal axis indicates the gate voltage (Vg [V]) and the vertical axis indicates the square root of drain current (Id^1/2[A]), the threshold voltage (Vth) is defined as a gate voltage at a point of intersection of an extrapolated tangent line of Id^1/2having the highest inclination with the Vg axis.

[0464] Further, according to FIG. 18, it is found that the absolute value of the amount of change in the threshold voltage of the transistors in the sample 1 decreases compared to the absolute value of the amount of change in the threshold voltage (ΔVth) of the transistors in the sample 2. In particular, the amount of change in the threshold voltage (ΔVth) due to the positive BT stress test (dark, +GBT) remarkably decreases. Thus, with the oxide film 19 containing In or Ga provided between the oxide semiconductor film 18 and the oxide insulating film 24, the reliability of the transistor can be improved.

[0465] In this manner, with the oxide film 19 containing In or Ga provided between the oxide semiconductor film 18 and the oxide insulating film 24, the electrical characteristics of the transistor can be improved. Specifically, both the initial characteristics and the reliability can be improved. Further, the oxide film 19 containing In or Ga can inhibit entry of elements (e.g., nitrogen) contained in the oxide insulating film 24 into the oxide semiconductor film 18 which is a channel region. Furthermore, the oxide film 19 containing In or Ga can inhibit the oxide semiconductor film 18 which is a channel region from receiving plasma damage at the time of forming the oxide insulating film 24 by a plasma CVD method with high power density.

Example 2

[0466] In this example, the number of oxygen vacancies contained in the oxide semiconductor film 18 of each of the transistors in the sample 1 and the sample 2 in Example 1 is described. In this example, samples having structures which are the same as the stacked structures of the transistors in the sample 1 and the sample 2 in Example 1 were formed, and analysis by an electron spin resonance (ESR) method was performed thereon in order to evaluate the number of oxygen vacancies contained in the oxide semiconductor film 18.

[0467] First, samples which were measured are described. In a sample 3, a 35-nm-thick oxide semiconductor film 18 was formed over quartz, a 20-nm-thick oxide film 19 containing In or Ga was formed over the oxide semiconductor film 18, and a 400-nm-thick oxide insulating film 24 was formed over the oxide film 19 containing In or Ga.

[0468] The oxide semiconductor film 18, the oxide film 19 containing In or Ga, and the oxide insulating film 24 in the sample 3 were formed under conditions similar to those of the sample 1 in Example 1.

[0469] In a sample 4, a 35-nm-thick oxide semiconductor film 18 was formed and a 400-nm-thick oxide insulating film 24 was formed over the oxide semiconductor film 18.

[0470] The oxide semiconductor film 18 and the oxide insulating film 24 of the sample 4 were formed under conditions similar to those of the sample 2 in Example 1.

[0471] Next, an analysis by the ESR method was performed on each of the samples 3 and 4. In the ESR measurement performed at a predetermined temperature, a value of a magnetic field (H₀) where a microwave is absorbed is used for an equation g=hv/βH₀, so that a parameter of a g-factor can be obtained. Note that the frequency of the microwave is denoted by v. Note that h and β represent the Planck constant and the Bohr magneton, respectively, and are both constants. In the analysis by the ESR method, a microwave power (9.06 GHz) was 20 mW, the direction of a magnetic field was parallel to a surface of each of the samples 3 and 4, and the measurement temperature was room temperature.

[0472] FIG. 19 shows results of the analysis by ESR. In FIG. 19, the horizontal axis represents the sample name and the vertical axis represents the spin density at a g-factor of 1.93 originating from the density of oxygen vacancies contained in the oxide semiconductor film 18 and the oxide film 19 containing In or Ga.

[0473] According to FIG. 19, the spin density of the sample 3 is lower than that of the sample 4. That is, the oxide film 19 containing In or Ga is provided between the oxide semiconductor film 18 and the oxide insulating film 24, which can inhibit the generation of the oxygen vacancies in the oxide semiconductor film 18 by plasma damage at the time of forming the oxide insulating film 24.

[0474] Further, although not illustrated, a 50-nm-thick oxide film 19 containing In or Ga was provided in the sample 3, whereby the spin density was less than or equal to the lower limit of detection. In this example, the lower limit of detection of the spin density is 1.0e+17 spins/cm³. Thus, in terms of reducing the oxygen vacancies, the 50-nm-thick oxide film 19 containing In or Ga is provided, whereby plasma damage at the time of forming the oxide insulating film 24 can be significantly reduced.

[0475] In this manner, by providing the oxide film 19 containing In or Ga, even in the case of forming the oxide insulating film 24 by a plasma CVD method with high power density, a transistor having favorable electrical characteristics and a semiconductor device including the transistor can be fabricated.

Example 3

[0476] In this example, a localized level of a multilayer film included in a transistor which is one embodiment of the present invention is described. Here, the results of evaluating the multilayer film by CPM measurement are described.

[0477] First, samples subjected to CPM measurement are described.

[0478] A 30-nm-thick first oxide film containing In or Ga was formed over a glass substrate, a 100-nm-thick oxide semiconductor film was formed over the first oxide film containing In or Ga, and a 30-nm-thick second oxide film containing In or Ga was formed over the oxide semiconductor film; thus, the multilayer film was formed.

[0479] In this example, the first oxide film containing In or Ga and the second oxide film containing In or Ga are oxide films each formed by a sputtering method using an In—Ga—Zn oxide (In:Ga:Zn=1:3:2 [atomic ratio]) target. Note that the films were formed in such a manner that an argon gas of 30 sccm and an oxygen gas of 15 sccm were used as a film formation gas, the pressure was set to be 0.4 Pa, the substrate temperature was set to be 200° C., and a DC power of 0.5 kW was applied.

[0480] Further, the oxide semiconductor film is an oxide semiconductor film formed by a sputtering method using an In—Ga—Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]) target. Note that the film was formed in such a manner that an argon gas of 30 sccm and an oxygen gas of 15 sccm were used as a deposition gas, the pressure was set to be 0.4 Pa, the substrate temperature was set to be 200° C., and a DC power of 0.5 kW was applied.

[0481] A sample manufactured in the above-described manner is referred to as a sample 5.

[0482] Next, CPM measurement was performed on the sample 5. Specifically, the amount of light with which a surface of the sample 5 between terminals is irradiated is adjusted so that a photocurrent value is kept constant in the state where voltage is applied between a first electrode and a second electrode provided in contact with the multilayer film of the sample, and then an absorption coefficient is derived from the amount of the irradiation light in an intended wavelength range.

[0483] FIGS. 20A and 20B shows results of fitting the absorption coefficient (thick dotted line) measured using a spectrophotometer and the absorption coefficient (thick solid line) measured by CPM in the range of energy higher than or equal to the energy gap of each layer included in the multilayer film. Note that in a curve of the absorption coefficient obtained by CPM measurement, the Urbach energy which is a slope of an Urbach tail (thin dotted line) was 78.7 meV. The integral value of the absorption coefficient in the energy range was derived in such a manner that the absorption coefficient (thin dotted line) of the Urbach tail was subtracted from the absorption coefficient derived from CPM measurement in the energy range shown with a dashed-line circle in FIG. 20A (see FIG. 20B). As a result, the absorption coefficient of this sample was found to be 2.02×10⁻⁴cm⁻¹.

[0484] From the above, it can be considered that the localized level of the multilayer film of the sample 5 is due to an impurity or a defect. Thus, the multilayer film was found to have extremely low density of states due to an impurity or a defect. That is, it can be found that the transistor including the multilayer film has stable electrical characteristics.

Example 4

[0485] In this example, the concentration of silicon in a multilayer film included in a transistor which is one embodiment of the present invention is described. Here, the results of evaluating the multilayer film by SIMS measurement are described.

[0486] First, samples which were measured by SIMS are described.

[0487] A 10-nm-thick oxide film 81 containing In or Ga was formed over a silicon wafer Si, a 10-nm-thick oxide semiconductor film 82 was formed over the oxide film 81 containing In or Ga, and a 10-nm-thick oxide film 83 containing In or Ga was formed over the oxide semiconductor film 82; thus, the multilayer film was formed.

[0488] In this example, the oxide film 81 containing In or Ga is an oxide film formed by a sputtering method using an In—Ga—Zn oxide (In:Ga:Zn=1:3:2 [atomic ratio]) target. Note that the film was formed in such a manner that an argon gas of 30 sccm and an oxygen gas of 15 sccm were used as a film formation gas, the pressure was set to be 0.4 Pa, the substrate temperature was set to be 200° C., and a DC power of 0.5 kW was applied.

[0489] The oxide semiconductor film 82 is an oxide semiconductor film formed by a sputtering method using an In—Ga—Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]) target. Note that the film was formed in such a manner that an argon gas of 30 sccm and an oxygen gas of 15 sccm were used as a film formation gas, the pressure was set to be 0.4 Pa, the substrate temperature was set to be 300° C., and a DC power of 0.5 kW was applied.

[0490] The oxide film 83 containing In or Ga is an oxide film formed by a sputtering method using an In—Ga—Zn oxide (In:Ga:Zn=1:3:2 [atomic ratio]) target. Note that the film was formed in such a manner that an argon gas of 30 sccm and an oxygen gas of 15 sccm were used as a film formation gas, the pressure was set to be 0.4 Pa, the substrate temperature was set to be 200° C., and a DC power of 0.5 kW was applied.

[0491] A sample which was not subjected to heat treatment after the multilayer film was formed and a sample which was subjected to heat treatment at 450° C. for 2 hours were prepared. The sample which was not subjected to heat treatment is referred to as a sample 6, and the sample which was subjected to heat treatment is referred to as a sample 7.

[0492] As for the sample 6 and the sample 7, the silicon concentration [atoms/cm³] in a depth direction was measured using a time-of-flight secondary ion mass spectrometry (ToF-SIMS). In FIG. 21A, the silicon concentration [atoms/cm³] converted from the secondary ion intensity of SiO₃in a depth direction of the multilayer film in the sample 6 is shown, and in FIG. 21B, the silicon concentration [atoms/cm³] converted from the secondary ion intensity of SiO₃in a depth direction of the multilayer film in the sample 7 is shown.

[0493] From FIGS. 21A and 21B, it was found that the silicon concentration is high at the interface between the silicon wafer and the oxide film 81 containing In or Ga and on the top surface of the oxide film 83 containing In or Ga. Moreover, it was found that the silicon concentration of the oxide semiconductor film 82 is about 1×10¹⁸atoms/cm³, the lower limit of detection in T of-SIMS. This is probably because, by providing the oxide film 81 containing In or Ga and the oxide film 83 containing In or Ga, the oxide semiconductor film 82 is not affected by silicon which is due to the silicon wafer, surface contamination, or the like.

[0494] Further, from the results shown in FIGS. 21A and 21B, it can be seen that silicon is less likely to be diffused by the heat treatment, though entry of silicon mainly occurs at the time of film formation.

[0495] Thus, with the use of a multilayer film as described in this example, a transistor having stable electrical characteristics can be manufactured.

Reference Example 1

[0496] Here, as the oxide insulating film 24 of the transistor described in any of the above examples, a silicon oxynitride film which contains more oxygen than that in the stoichiometric composition and from which part of oxygen is released by heating is described.

[0497] In order to evaluate that more oxygen than that in the stoichiometric composition is contained and part of oxygen is released by heating, TDS measurement was performed to measure the released amount of oxygen.

[0498] First, the structures of samples subjected to the measurement are described. In a reference sample 1, a 400-nm-thick silicon oxynitride film was formed over a silicon wafer under the following conditions. In the conditions, formation was performed by a plasma CVD method in which silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 4000 sccm were used as source gases, the pressure in a treatment chamber was 200 Pa, the substrate temperature was 220° C., and a high-frequency power of 1500 W was supplied to parallel plate electrodes.

[0499] A reference sample 2 is a reference sample in which a 400-nm-thick silicon oxynitride film was formed over a silicon wafer under the following conditions. As the conditions, the flow rate of silane was changed into 200 sccm in the conditions of the reference sample 1, and conditions except that are the same as those of the reference sample 1.

[0500] The results of TDS measurements of the reference sample 1 and the reference sample 2 are shown in FIGS. 22A and 22B. In FIGS. 22A and 22B, a peak of M/z=32 corresponding to the mass number of oxygen was observed from each of the reference sample 1 and the reference sample 2. Thus, as for the silicon oxynitride film in each of the reference sample 1 and the reference sample 2, it can be said that part of oxygen contained in the film is released by heating.

[0501] Note that the amount of oxygen released by heating can be evaluated by using the value obtained by converting the amount of oxygen into oxygen molecules (per unit area). In the reference sample 1, the amount of oxygen was 3.2×10¹⁴molecules/cm². In the reference sample 2, the amount of oxygen was 1.9×10¹⁴molecules/cm². Note that the value obtained by converting the amount of oxygen released from the reference sample 1 into oxygen atoms (per unit volume) was 1.6×10¹⁹atoms/cm³, and the value obtained by converting the amount of oxygen released from the reference sample 2 into oxygen atoms (per unit volume) was 9.5×10¹⁸atoms/cm³.

[0502] As described above, after the silicon oxynitride film which is formed under the conditions of Reference example 1 and Reference example 2 is provided in a region overlapping with the oxide semiconductor film, heat treatment is performed thereon, whereby the oxygen vacancies in the oxide semiconductor film can be filled, so that the transistor with favorable electrical characteristics can be fabricated.

Reference Example 2

[0503] Defect density of an oxide insulating film used in the reference sample 1 and the reference sample 2 in Reference example 1 is described. In this example, the number of defects in the oxide insulating film is described using the results of analysis by an electron spin resonance (ESR) method.

[0504] First, the structures of evaluated samples are described.

[0505] A reference sample 3 and a reference sample 4 each include a 100-nm-thick oxide semiconductor film formed over a quartz substrate and a 400-nm-thick oxide insulating film formed over the oxide semiconductor film.

[0506] The oxide semiconductor film in the reference sample 3 and the reference sample 4 was formed in such a manner that a sputtering target where In:Ga:Zn=1:1:1 (atomic ratio) was used, argon with a flow rate of 50 sccm and oxygen with a flow rate of 50 sccm were supplied as sputtering gases into a treatment chamber of a sputtering apparatus, the pressure in the treatment chamber was adjusted to 0.6 Pa, and a direct-current power of 5 kW was supplied. Note that the oxide semiconductor film was formed at a substrate temperature of 170° C.

[0507] Next, heat treatment at 450° C. under a nitrogen atmosphere for one hour was performed and then heat treatment at 450° C. under a mixed atmosphere of nitrogen and oxygen for one hour was performed.

[0508] Next, an oxide insulating film was formed over the oxide semiconductor film. A sample including the oxide insulating film formed under conditions similar to those of the silicon oxynitride film in the reference sample 1 is referred to as the reference sample 3.

[0509] A sample including the oxide insulating film formed over the oxide semiconductor film under conditions similar to those of the silicon oxynitride film in the reference sample 2 is referred to as the reference sample 4.

[0510] Next, analysis by an ESR method was performed on the reference sample 3 and the reference sample 4. Here, the analysis by the ESR method was performed under the following conditions. The measurement temperature was −170° C., the high-frequency power (power of microwaves) of 9.1 GHz was 1 mW, and the direction of a magnetic field was parallel to a film surface of each sample.

[0511] The spin density of signals which appears at g (g-factor)=2.001 originating from dangling bonds of silicon is shown in FIG. 23.

[0512] It can be found that the spin density in the reference sample 4 is lower than that in the reference sample 3. That is, in the film formation conditions of the oxide insulating film, when the flow rate of silane is 200 sccm and the flow rate of dinitrogen monoxide is 4000 sccm, it is possible to form a silicon oxynitride film with fewer defects, typically, a silicon oxynitride film in which the spin density of a signal which appears at g=2.001, is lower than 6×10¹⁷spins/cm³, preferably lower than or equal to 3×10¹⁷spins/cm³, more preferably lower than or equal to 1.5×10¹⁷spins/cm³by analysis by an ESR method.

[0513] As described above, the oxide insulating film is formed under the above conditions and the flow rate of silane is increased, whereby defect density in the formed oxide insulating film can be reduced.

Reference Example 3

[0514] Here, quantification of defect level generated in an energy gap of the oxide semiconductor film is described. In this reference example, measurement results of hard X-ray photoelectron spectroscopy (HAXPES) which is photoelectron spectroscopy using hard X-ray with high luminance are described.

[0515] Samples which were measured by HAXPES are described.

[0516] A sample (a sample 8) was fabricated, in which a 100-nm-thick silicon oxynitride film was formed over a silicon wafer, a 100-nm-thick oxide semiconductor film was formed over the silicon oxynitride film, and a 5-nm-thick silicon oxide film was formed over the oxide semiconductor film.

[0517] The sample 8 was formed by a plasma CVD method under the following conditions: silane with a flow rate of 1 sccm and dinitrogen monoxide with a flow rate of 800 sccm were used as a source gas, the pressure in a treatment chamber was 40 Pa, the substrate temperature was 400° C., and high-frequency power of 150 W (60 MHz) was supplied to parallel-plate electrodes.

[0518] In the sample 8, the oxide semiconductor film was formed by a sputtering method under the following conditions: an In—Ga—Zn-oxide target (In:Ga:Zn=1:1:1 [atomic ratio]) was used; argon with a flow rate of 30 sccm and oxygen with a flow rate of 15 sccm were used as a deposition gas; the pressure was 0.4 Pa; the substrate temperature was 300° C.; and a direct-current power of 0.5 kW was supplied.

[0519] In the sample 8, the silicon oxide film was formed by a sputtering method under the following conditions: a target including silicon was used; oxygen with a flow rate of 50 sccm were used as a deposition gas; the pressure was 0.4 Pa; the substrate temperature was 100° C.; and a direct-current power of 1.5 kW was supplied. Note that the silicon oxide film is a film containing oxygen at a higher proportion than oxygen in the stoichiometric composition and from which part of oxygen is released by heat treatment.

[0520] Further, a sample (a sample 9) was fabricated, in which a 100-nm-thick oxide semiconductor film was formed over a silicon wafer. Furthermore, a sample (a sample 10) was fabricated, in which a 100-nm-thick silicon oxynitride film was formed over a silicon wafer and a 100-nm-thick oxide semiconductor film was formed over the silicon oxynitride film.

[0521] In the samples 9 and 10, the oxide semiconductor film and the silicon oxynitride film were each formed by a method similar to that of the sample 8. Further, in each of the samples 8 to 10, after the oxide semiconductor film was formed, heat treatment at 450° C. in an atmosphere containing nitrogen and oxygen was performed. In the sample 8, after the silicon oxide film was formed, heat treatment at 300° C. in an oxygen atmosphere was further performed.

[0522] Next, the samples 8 to 10 were measured by HAXPES. HAXPES measurement is photoelectron spectroscopy using hard X-ray (approximately 6 to 8 keV) as excited X-ray.

[0523] FIG. 35 shows the valence band spectrum obtained by the HAXPES measurement of each of the samples. In FIG. 35, the horizontal axis represents the binding energy and the vertical axis represents the spectrum intensity. The position of 0 eV on the horizontal axis can be regarded as the conduction band of the oxide semiconductor film and the position of around 3 eV on the horizontal axis can be regarded as the valence band of the oxide semiconductor film. That is, the space between the position of 0 eV on the horizontal axis and the position of around 3 eV on the horizontal axis can be regarded as the energy gap of the oxide semiconductor film.

[0524] The intensity of the valence band spectrum depends on the defect level generated in the energy gap of the oxide semiconductor film. For example, when there is a defect level, the intensity of the valence band spectrum is increased.

[0525] It can be considered that, based on the principle of the HAXPES measurement, the signal detected by the HAXPES measurement reflects the defect in the vicinity of the surface of the sample. From the results of the samples 9 and 10 in FIG. 35, it can be considered that the defect level generated in the energy gap of the oxide semiconductor film corresponds to the defect in the vicinity of the surface of the oxide semiconductor film.

[0526] It is found that, in the range of 0 eV to 3 eV on the horizontal axis in FIG. 35, the intensity of the spectrum of the sample 8 is lower than that of the spectra of the samples 9 and 10. Thus, as in the sample 8, the silicon oxide film from which part of oxygen is released by heating is provided in contact with the oxide semiconductor film and heat treatment is performed, whereby the defect in the vicinity of the surface of the oxide semiconductor film (in the vicinity of the interface between the oxide semiconductor film and the silicon oxide film) can be repaired. Further, it can be considered that the defect level corresponds to oxygen vacancies included in the oxide semiconductor film. That is, the silicon oxide film from which part of oxygen is released by heating is provided in contact with the oxide semiconductor film and heat treatment is performed, whereby the oxygen vacancies in the vicinity of the surface of the oxide semiconductor film can be filled.

[0527] Here, the silicon oxide film provided over the oxide semiconductor film is formed by a sputtering method. However, it can be considered that, even if the silicon oxide film is formed by a plasma CVD method, the defect in the vicinity of the surface of the oxide semiconductor film can be repaired as long as the silicon oxide film is a silicon oxide film which contains oxygen at a higher proportion than oxygen in the stoichiometric composition and from which part of oxygen is released by heat treatment. Thus, it can be considered that the silicon oxide film formed by the method described in this specification, e.g., Embodiment 1, can repair the defect in the vicinity of the surface of the oxide semiconductor film.

Reference Example 4

[0528] Here, the energy barrier between a source and a drain of a transistor including an oxide semiconductor is described.

[0529] In the case where an intrinsic or substantially intrinsic oxide semiconductor film is used as an oxide semiconductor film which is to be a channel region, a barrier which is about half the energy gap of the oxide semiconductor film might be formed between the oxide semiconductor film and the pair of electrodes serving as a source electrode and a drain electrode in a transistor including the oxide semiconductor film. However, in practice, drain current starts flowing at a gate voltage of about 0 V in the Vg-Id characteristics of the transistor including the oxide semiconductor film, which suggests that there is a problem in the aforementioned idea.

[0530] Thus, as shown in FIG. 36A, a transistor with a structure including a gate insulating film GI, an oxide semiconductor film OS over the gate insulating film GI, and a source electrode S and a drain electrode D provided over the oxide semiconductor film OS was assumed, and the band structure of the transistor along dashed-dotted line H1-H2, in which the channel length (L) was varied, was derived from calculation. Note that in FIG. 36A, n-type low-resistance regions n are provided in regions of the oxide semiconductor film OS in contact with the source electrode S and the drain electrode D. That is, the oxide semiconductor film OS includes the low-resistance regions n and an intrinsic or substantially intrinsic region i. Note that in the calculation, the oxide semiconductor film OS was assumed to have a thickness of 35 nm and the gate insulating film GI was assumed to have a thickness of 400 nm to perform the calculation.

[0531] The width of band bending was estimated by solving Poisson's equation, whereby the width of band bending was found to be a length characterized by a Debye shielding length λ_D. Note that the Debye shielding length λ_Dcan be represented by the following equation, and in the following equation, k_Brepresents a Boltzmann constant.

[0532]

\begin{matrix} λ_{D} = \sqrt{\frac{ɛ ɛ_{0} k_{B} T}{e^{2} ni}} & [FORMULA 2] \end{matrix}

[0533] In the above equation, when the intrinsic carrier density ni of the oxide semiconductor film OS was 6.6×10⁻⁹cm⁻³, the relative permittivity c of the oxide semiconductor film OS was 15, and the temperature was 300 K, the Debye shielding length λ_Dwas determined to be 5.7×10¹⁰μm, which was an extremely large value. Thus, it can be found that the energy barrier between the low-resistance region n and the intrinsic or substantially intrinsic region i is half the energy gap of the oxide semiconductor film OS in the case where the channel length is longer than 1.14×10¹¹μm which is twice the Debye shielding length λ_D.

[0534] FIG. 37 shows the results of calculation of band structures where the channel lengths are 0.03 μm, 0.3 μm, 1 μm, 10 μm, 100 μm, and 1×10¹²μm. Note that the electric potentials of the source electrode and the drain electrode are fixed to GND (0 V). Note that in FIG. 37, “n” represents the low-resistance region, “i” represents the intrinsic or substantially intrinsic region interposed between the low-resistance regions, a dashed-dotted line represents Fermi energy of the oxide semiconductor film, and a dashed line represents midgap of the oxide semiconductor film.

[0535] It was found from FIG. 37 that, in the case where the channel length is 1×10¹²μm which is long enough, the difference in electron energy between the low-resistance region and the intrinsic or substantially intrinsic region is half the energy gap of the oxide semiconductor film. However, it was found that, as the channel length is reduced, the difference in electron energy between the low-resistance region and the intrinsic or substantially intrinsic region gradually becomes smaller and there is essentially no energy barrier when the channel length is shorter than or equal to 1 μm. Note that the electron energy of the low-resistance region is fixed by the pair of electrodes serving as a source electrode and a drain electrode.

[0536] As described above, it can be determined that the energy barrier between the low-resistance region and the intrinsic or substantially intrinsic region is sufficiently low when the channel length is short.

[0537] Here, the reason why the energy barrier between the low-resistance region and the intrinsic or substantially intrinsic region is sufficiently low when the channel length is short is considered.

[0538] Description is made on the schematic views of an oxide semiconductor film and the band structures of the oxide semiconductor film with reference to FIGS. 38A to 38C. In FIG. 38A, the conduction band bottom Ec_0 of an oxide semiconductor film 600 including an intrinsic or substantially intrinsic region 601 and low-resistance regions 602 and 603 is shown. Further, the channel length of the oxide semiconductor film 600 is denoted by L_0. In FIG. 38A, L_0>2λ_Dis satisfied.

[0539] FIG. 38B shows an oxide semiconductor film whose channel length is shorter than that in FIG. 38A, and the band structure thereof. In FIG. 38B, the conduction band bottom Ec_1 of an oxide semiconductor film 610 including an intrinsic or substantially intrinsic region 611 and low-resistance regions 612 and 613 is shown. Further, the channel length of the oxide semiconductor film 610 is denoted by L_1. In FIG. 38B, the channel length of L_1<L_0 and L_1<2λ_Dis satisfied.

[0540] FIG. 38C shows an oxide semiconductor film whose channel length is shorter than the oxide semiconductor films shown in FIGS. 38A and 38B, and the band structure thereof. In FIG. 38C, the conduction band bottom Ec_2 of an oxide semiconductor film 620 including an intrinsic or substantially intrinsic region 621 and low-resistance regions 622 and 623 is shown. Further, the channel length of the oxide semiconductor film 620 is denoted by L_2. The channel length of L_2<L_1 and L_2<<2λ_Dis satisfied.

[0541] The energy difference between the Fermi level Ef and the conduction band bottom Ec_0 is denoted by ΔH_0 in FIG. 38A, the energy gap between the Fermi level Ef and the conduction band bottom Ec_1 is denoted by ΔH_1 in FIG. 38B, and the energy gap between the Fermi level Ef and the conduction band bottom Ec_2 is denoted by ΔH_2 in FIG. 38C.

[0542] In the oxide semiconductor film, regions in contact with the pair of electrodes serve as the low-resistance regions. Thus, the closer the junction regions between the intrinsic or substantially intrinsic region and the low-resistance regions are, the more lowered in energy and more bent the conduction band bottom is. In the case where the channel length L_0 is long enough as shown in FIG. 38A, the energy barrier ΔH_0 corresponds to Eg(bandgap)/2.

[0543] On the other hand, when the channel length is reduced as shown in each of FIGS. 38B and 38C, the bent portions of the conduction band bottom (Ec_1, Ec_2) overlap with each other; thus, it is probable that the energy barriers ΔH_0 and ΔH_2 are lower than Eg/2. The phenomenon in which the conduction band bottom in the intrinsic or substantially intrinsic region is thus lowered by the reduction of the channel length is referred to as a conduction band lowering (CBL) effect in this specification.

[0544] Next, a bottom-gate transistor including a gate electrode GE provided under the gate insulating film GI in the structure shown in FIG. 36A was assumed, and the band structure of the transistor along dashed-dotted line H1-H2, in which the channel length (L) was varied, was derived from calculation. The structure of the transistor used in the calculation is shown in FIG. 36B. Note that in the calculation, the oxide semiconductor film OS was assumed to have a thickness of 35 nm and the gate insulating film GI was assumed to have a thickness of 400 nm were used to perform the calculation.

[0545] FIG. 39 shows the results of calculation of band structures where the channel lengths are 1 μm, 10 μm, 50 μm, 100 μm, 1×10⁵μm, and 1×10¹²μm. Note that the electric potentials of the source electrode, the drain electrode, and the gate electrode are fixed to GND (0 V). Note that in FIG. 39, “n” represents the low-resistance region, “i” represents the intrinsic or substantially intrinsic region interposed between the low-resistance regions, a dashed-dotted line represents Fermi energy of the oxide semiconductor film, and a dashed line represents midgap of the oxide semiconductor film.

[0546] The band structures shown in FIG. 39 are the results obtained by performing calculation in a manner similar to that in the structure shown in FIG. 36A. However, it can be found that, in the case where the gate electrode is provided as in the structure of FIG. 36B, the value of the energy barrier between the low-resistance region and the intrinsic or substantially intrinsic region does not depend on the channel length (L) and is substantially constant even when the channel length (L) is longer than 1 μm.

[0547] In FIG. 40, the height of the energy barrier with respect to the channel length (L length) in each of the structures of FIG. 36A and FIG. 36B is shown.

[0548] From FIG. 40, it can be seen that the height of the energy barrier in the structure of FIG. 36A without a gate electrode monotonically increases as the channel length increases and becomes half the energy gap of the oxide semiconductor film (i.e., 1.6 eV) when the channel length is 1×10¹²μm. On the other hand, it can be seen that the height of the energy barrier of the structure of FIG. 36B with the gate electrode does not depend on the channel length even when the channel length is longer than 1 μm.

[0549] From the above, since the energy barrier is lower than the value which is half the energy gap of the oxide semiconductor film by the CBL effect in the transistor including the intrinsic or substantially intrinsic oxide semiconductor film, it can be considered that drain current starts flowing at a gate voltage of about 0 V in the Vg-Id characteristics. Further, since the value of the energy barrier of the transistor whose channel length is longer than a certain length (1 μm) is constant without depending on the channel length, it can be considered that drain current starts flowing at a gate voltage of about 0 V in the Vg-Id characteristics in the transistor including the intrinsic or substantially intrinsic oxide semiconductor film.

[0550] The multilayer film included in the transistor of one embodiment of the present invention includes the intrinsic or substantially intrinsic oxide semiconductor film. Thus, it can be considered that, in the transistor including the multilayer film, drain current starts flowing at a gate voltage of about 0 V in the Vg-Id characteristics.

[0551] This application is based on Japanese Patent Application serial no. 2012-234616 filed with Japan Patent Office on Oct. 24, 2012, the entire contents of which are hereby incorporated by reference.

Claims

What is claimed is:

1. A semiconductor device comprising:

a transistor including:

an oxide semiconductor film containing In and Ga; and

an oxide film containing In or Ga adjacent to the oxide semiconductor film; and

a silicon oxide insulating film over the transistor,

wherein the silicon oxide insulating film contains oxygen at a higher proportion than a stoichiometric composition,

wherein a proportion of Ga in the oxide film containing In or Ga is higher than a proportion of Ga in the oxide semiconductor film, and

wherein change in a threshold voltage of the transistor by a bias-temperature stress test each in dark and photostress is within a range of more than or equal to −1.0 V and less than or equal to 1.0 V.

2. The semiconductor device according to claim 1, wherein the oxide film containing In or Ga is provided over the oxide semiconductor film.

3. The semiconductor device according to claim 1, wherein the silicon oxide insulating film is in contact with the oxide film containing In or Ga.

4. The semiconductor device according to claim 1, further comprising:

a pair of electrodes in contact with the oxide film containing In or Ga.

5. A semiconductor device comprising:

a transistor including:

a gate electrode over a substrate;

a gate insulating film covering the gate electrode;

a multilayer film overlapping with the gate electrode with the gate insulating film provided between the multilayer film and the gate electrode; and

a pair of electrodes in contact with the multilayer film; and

a silicon oxide insulating film covering the gate insulating film, the multilayer film, and the pair of electrodes,

wherein the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga,

wherein the silicon oxide insulating film contains oxygen at a higher proportion than a stoichiometric composition, and

6. The semiconductor device according to claim 5, wherein the oxide semiconductor film contains In or Ga.

7. The semiconductor device according to claim 5, wherein an energy level of a conduction band bottom of the oxide film containing In or Ga is closer to a vacuum level than an energy level of a conduction band bottom of the oxide semiconductor film.

8. The semiconductor device according to claim 7, wherein difference between the energy level of the conduction band bottom of the oxide film containing In or Ga and the energy level of the conduction band bottom of the oxide semiconductor film is greater than or equal to 0.05 eV and less than or equal to 2 eV.

9. The semiconductor device according to claim 5,

wherein each of the oxide semiconductor film and the oxide film containing In or Ga is a film containing an In—M—Zn oxide,

wherein the M is one selected from the group consisting of Al, Ti, Y, Zr, La, Ce, Nd, and Hf, and

wherein proportion of the M in the oxide film containing In or Ga is higher than proportion of the M in the oxide semiconductor film.

10. The semiconductor device according to claim 5,

wherein each of the oxide semiconductor film and the oxide film containing In or Ga is a film containing an In—Ga—Zn oxide, and

wherein proportion of the Ga in the oxide film containing In or Ga is higher than proportion of the Ga in the oxide semiconductor film.

11. The semiconductor device according to claim 5, wherein in the multilayer film, an absorption coefficient derived from a constant photocurrent method is lower than 1×10⁻³/cm in an energy range of 1.5 eV to 2.3 eV.

12. The semiconductor device according to claim 5, wherein silicon concentration in between the oxide semiconductor film and the oxide film containing In or Ga is lower than 2×10¹⁸atoms/cm³.

13. A method for manufacturing a semiconductor device comprising a transistor, comprising:

forming a gate electrode over a substrate,

forming a gate insulating film over the substrate;

forming a multilayer film over the gate insulating film, the multilayer film including an oxide semiconductor film and an oxide film containing In or Ga,

forming a pair of electrodes in contact with the multilayer film, and

forming an oxide insulating film over the multilayer film and the pair of electrodes,

wherein the oxide insulating film is formed by holding the substrate placed in a treatment chamber which is vacuum-evacuated at a temperature higher than or equal to 180° C. and lower than or equal to 260° C., setting pressure in the treatment chamber to be greater than or equal to 100 Pa and less than or equal to 250 Pa with introduction of a source gas into the treatment chamber, and supplying a frequency power higher than or equal to 0.17 W/cm²and lower than or equal to 0.5 W/cm²to an electrode provided in the treatment chamber,

14. The method for manufacturing a semiconductor device according to claim 13, wherein as the oxide insulating film, a silicon oxide film or a silicon oxynitride film is formed by using a deposition gas containing silicon and an oxidizing gas as source gases.

15. The method for manufacturing a semiconductor device according to claim 13, wherein as the oxide insulating film, a silicon oxynitride film is formed using silane and dinitrogen monoxide as source gases.

16. The semiconductor device according to claim 5, wherein the silicon oxide insulating film is in direct contact with a top surface of the oxide film containing In or Ga.

Patent Citations (131)

Patent	Date	Inventor	Cited By
US5528032(A)	1996-06-01	Uchiyama	Applicant
US5731856(A)	1998-03-01	Kim et al.	Applicant
US5744864(A)	1998-04-01	Cillessen et al.	Applicant
US6294274(B1)	2001-09-01	Kawazoe et al.	Applicant
US6563174(B2)	2003-05-01	Kawasaki et al.	Applicant
US6727522(B1)	2004-04-01	Kawasaki et al.	Applicant
US7049190(B2)	2006-05-01	Takeda et al.	Applicant
US7061014(B2)	2006-06-01	Hosono et al.	Applicant
US7064346(B2)	2006-06-01	Kawasaki et al.	Applicant
US7105868(B2)	2006-09-01	Nause et al.	Applicant
US7211825(B2)	2007-05-01	Shih et al	Applicant
US7282782(B2)	2007-10-01	Hoffman et al.	Applicant
US7297977(B2)	2007-11-01	Hoffman et al.	Applicant
US7323356(B2)	2008-01-01	Hosono et al.	Applicant
US7385224(B2)	2008-06-01	Ishii et al.	Applicant
US7402506(B2)	2008-07-01	Levy et al.	Applicant
US7411209(B2)	2008-08-01	Endo et al.	Applicant
US7453065(B2)	2008-11-01	Saito et al.	Applicant
US7453087(B2)	2008-11-01	Iwasaki	Applicant
US7462862(B2)	2008-12-01	Hoffman et al.	Applicant
US7468304(B2)	2008-12-01	Kaji et al.	Applicant
US7501293(B2)	2009-03-01	Ito et al.	Applicant
US7674650(B2)	2010-03-01	Akimoto et al.	Applicant
US7732819(B2)	2010-06-01	Akimoto et al.	Applicant
US2001/0046027(A1)	2001-11-01	Tai et al.	Applicant
US2002/0056838(A1)	2002-05-01	Ogawa	Applicant
US2002/0132454(A1)	2002-09-01	Ohtsu et al.	Applicant
US2003/0189401(A1)	2003-10-01	Kido et al.	Applicant
US2003/0218222(A1)	2003-11-01	Wager, III et al.	Applicant
US2004/0038446(A1)	2004-02-01	Takeda et al.	Applicant
US2004/0127038(A1)	2004-07-01	Carcia et al.	Applicant
US2005/0017302(A1)	2005-01-01	Hoffman	Applicant
US2005/0199959(A1)	2005-09-01	Chiang et al.	Applicant
US2006/0035452(A1)	2006-02-01	Carcia et al.	Applicant
US2006/0043377(A1)	2006-03-01	Hoffman et al.	Applicant
US2006/0091793(A1)	2006-05-01	Baude et al.	Applicant
US2006/0108529(A1)	2006-05-01	Saito et al.	Applicant
US2006/0108636(A1)	2006-05-01	Sano et al.	Applicant
US2006/0110867(A1)	2006-05-01	Yabuta et al.	Applicant
US2006/0113536(A1)	2006-06-01	Kumomi et al.	Applicant
US2006/0113539(A1)	2006-06-01	Sano et al.	Applicant
US2006/0113549(A1)	2006-06-01	Den et al.	Applicant
US2006/0113565(A1)	2006-06-01	Abe et al.	Applicant
US2006/0169973(A1)	2006-08-01	Isa et al.	Applicant
US2006/0170111(A1)	2006-08-01	Isa et al.	Applicant
US2006/0197092(A1)	2006-09-01	Hoffman et al.	Applicant
US2006/0208977(A1)	2006-09-01	Kimura	Applicant
US2006/0228974(A1)	2006-10-01	Thelss et al.	Applicant
US2006/0231882(A1)	2006-10-01	Kim et al.	Applicant
US2006/0238135(A1)	2006-10-01	Kimura	Applicant
US2006/0244107(A1)	2006-11-01	Sugihara et al.	Applicant
US2006/0284171(A1)	2006-12-01	Levy et al.	Applicant
US2006/0284172(A1)	2006-12-01	Ishii	Applicant
US2006/0292777(A1)	2006-12-01	Dunbar	Applicant
US2007/0024187(A1)	2007-02-01	Shin et al.	Applicant
US2007/0046191(A1)	2007-03-01	Saito	Applicant
US2007/0052025(A1)	2007-03-01	Yabuta	Applicant
US2007/0054507(A1)	2007-03-01	Kaji et al.	Applicant
US2007/0090365(A1)	2007-04-01	Hayashi et al.	Applicant
US2007/0108446(A1)	2007-05-01	Akimoto	Applicant
US2007/0152217(A1)	2007-07-01	Lai et al.	Applicant
US2007/0172591(A1)	2007-07-01	Seo et al.	Applicant
US2007/0187678(A1)	2007-08-01	Hirao et al.	Applicant
US2007/0187760(A1)	2007-08-01	Furuta et al.	Applicant
US2007/0194379(A1)	2007-08-01	Hosono et al.	Applicant
US2007/0252928(A1)	2007-11-01	Ito et al.	Applicant
US2007/0272922(A1)	2007-11-01	Kim et al.	Applicant
US2007/0287296(A1)	2007-12-01	Chang	Applicant
US2008/0006877(A1)	2008-01-01	Mardilovich et al.	Applicant
US2008/0038882(A1)	2008-02-01	Takechi et al.	Applicant
US2008/0038929(A1)	2008-02-01	Chang	Applicant
US2008/0050595(A1)	2008-02-01	Nakagawara et al.	Applicant
US2008/0073653(A1)	2008-03-01	Iwasaki	Applicant
US2008/0083950(A1)	2008-04-01	Pan et al.	Applicant
US2008/0106191(A1)	2008-05-01	Kawase	Applicant
US2008/0128689(A1)	2008-06-01	Lee et al.	Applicant
US2008/0129195(A1)	2008-06-01	Ishizaki et al.	Applicant
US2008/0166834(A1)	2008-07-01	Kim et al.	Applicant
US2008/0182358(A1)	2008-07-01	Cowdery-Corvan et al.	Applicant
US2008/0224133(A1)	2008-09-01	Park et al.	Applicant
US2008/0254569(A1)	2008-10-01	Hoffman et al.	Applicant
US2008/0258139(A1)	2008-10-01	Ito et al.	Applicant
US2008/0258140(A1)	2008-10-01	Lee et al.	Applicant
US2008/0258141(A1)	2008-10-01	Park et al.	Applicant
US2008/0258143(A1)	2008-10-01	Kim et al.	Applicant
US2008/0296568(A1)	2008-12-01	Ryu et al.	Applicant
US2009/0068773(A1)	2009-03-01	Lai et al.	Applicant
US2009/0073325(A1)	2009-03-01	Kuwabara et al.	Applicant
US2009/0114910(A1)	2009-05-01	Chang	Applicant
US2009/0134399(A1)	2009-05-01	Sakakura et al.	Applicant
US2009/0152506(A1)	2009-06-01	Umeda et al.	Applicant
US2009/0152541(A1)	2009-06-01	Maekawa et al.	Applicant
US2009/0278122(A1)	2009-11-01	Hosono et al.	Applicant
US2009/0280600(A1)	2009-11-01	Hosono et al.	Applicant
US2010/0065844(A1)	2010-03-01	Tokunaga	Applicant
US2010/0092800(A1)	2010-04-01	Itagaki et al.	Applicant
US2010/0109002(A1)	2010-05-01	Itagaki et al.	Applicant
US2011/0084273(A1)	2011-04-01	Yamazaki et al.	Applicant
US2011/0267083(A1)	2011-11-01	Tsuji	Applicant
US2011/0279144(A1)	2011-11-01	Kamata	Applicant
US2011/0281394(A1)	2011-11-01	Yamazaki	Examiner
US2012/0032163(A1)	2012-02-01	Yamazaki	Examiner
US2012/0113086(A1)	2012-05-01	Koyama	Applicant
US2012/0138922(A1)	2012-06-01	Yamazaki et al.	Applicant
US2012/0231580(A1)	2012-09-01	Yamazaki et al.	Applicant
US2012/0286252(A1)	2012-11-01	Seo et al.	Applicant
US2013/0264563(A1)	2013-10-01	Okazaki	Applicant
EP1737044(A1)	2006-12-01		Applicant
EP2226847(A2)	2010-09-01		Applicant
JP60-198861(A)	1985-10-01		Applicant
JP63-210022(A)	1988-08-01		Applicant
JP63-210023(A)	1988-08-01		Applicant
JP63-210024(A)	1988-08-01		Applicant
JP63-215519(A)	1988-09-01		Applicant
JP63-239117(A)	1988-10-01		Applicant
JP63-265818(A)	1988-11-01		Applicant
JP5-251705(A)	1993-09-01		Applicant
JP8-264794(A)	1996-10-01		Applicant
JP11-505377(A)	1999-05-01		Applicant
JP2000-044236(A)	2000-02-01		Applicant
JP2000-150900(A)	2000-05-01		Applicant
JP2002-076356(A)	2002-03-01		Applicant
JP2002-289859(A)	2002-10-01		Applicant
JP2003-086000(A)	2003-03-01		Applicant
JP2003-086808(A)	2003-03-01		Applicant
JP2004-103957(A)	2004-04-01		Applicant
JP2004-273614(A)	2004-09-01		Applicant
JP2004-273732(A)	2004-09-01		Applicant
JP2007-096055(A)	2007-04-01		Applicant
JP2007-123861(A)	2007-05-01		Applicant
WO2004/114391(A1)	2004-12-01		Applicant

Non-Patent Literature (69)

Ohara, H et al., “Amorphous In—Ga—Zn—Oxide TFTs with Suppressed Variation for 4.0 inch QVGA AMOLED Display,” AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 227-230, The Japan Society of Applied Physics.Applicant
Orita, M et al., “Amorphous transplant conductive oxide InGaO3(ZnO)m (m<4):a Zn4s conductor,” Philosophical Magazine, 2001, vol. 81, No. 5, pp. 501-515.Applicant
Orita, M et al., “Mechanism of Electrical Conductivity of Transparent InGaZnO4,” Phys. Rev. B (Physical Review. B), Jan. 15, 2000, vol. 61, No. 3, pp. 1811-1816.Applicant
Osada, T et al., “15.2: Development of Driver-Integrated Panel using Amorphous In—Ga—Zn—Oxide TFT,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 184-187.Applicant
Osada, T et al., “Development of Driver-Integrated Panel Using Amorphous In—Ga—Zn—Oxide TFT,” AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 33-36.Applicant
Park, J et al., “Dry etching of ZnO films and plasma-induced damage to optical properties,” J. Vac. Sci. Technol. B (Journal of Vacuum Science & Technology B), Mar. 1, 2003, vol. 21, No. 2, pp. 800-803.Applicant
Park, J et al., “Improvements in the Device Characteristics of Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors by Ar Plasma Treatment,” Appl. Phys. Lett. (Applied Physics Letters), Jun. 26, 2007, vol. 90, No. 26, pp. 262106-1-262106-3.Applicant
Park, J et al., “Electronic Transport Properties of Amorphous Indium—Gallium—Zinc Oxide Semiconductor Upon Exposure to Water,” Appl. Phys. Lett. (Applied Physics Letters), 2008, vol. 92, pp. 072104-1-072104-3.Applicant
Park, J et al., “High performance amorphous oxide thin film transistors with self-aligned top-gate structure,” IEDM 09: Technical Digest of International Electron Devices Meeting, Dec. 7, 2009, pp. 191-194.Applicant
Park, Sang-Hee et al., “42.3: Transparent ZnO Thin Film Transistor for the Application of High Aperture Ratio Bottom Emission AM-OLED Display,” SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 629-632.Applicant
Park, J et al., “Amorphous Indium—Gallium—Zinc Oxide TFTs and Their Application for Large Size AMOLED,” AM-FPD '08 Digest of Technical Papers, Jul. 2, 2008, pp. 275-278.Applicant
Park, S et al., “Challenge to Future Displays: Transparent AM-OLED Driven by Peald Grown ZnO TFT,” IMID '07 Digest, 2007, pp. 1249-1252.Applicant
Prins, M et al., “A Ferroelectric Transparent Thin-Film Transistor,” Appl. Phys. Lett. (Applied Physics Letters), Jun. 17, 1996, vol. 68, No. 25, pp. 3650-3652.Applicant
Sakata, J et al., “Development of 4.0-In. AMOLED Display With Driver Circuit Using Amorphous In—Ga—Zn—Oxide TFTs,” IDW '09 : Proceedings of the 16th International Display Workshops, 2009, pp. 689-692.Applicant
Son, K et al., “42.4L: Late-News Paper: 4 Inch QVGA AMOLED Driven by the Threshold Voltage Controlled Amorphous Gizo (Ga2O3—In2O3—ZnO) TFT,” SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 633-636.Applicant
Takahashi, M et al., “Theoretical Analysis of IGZO Transparent Amorphous Oxide Semiconductor,” IDW '08 : Proceedings of the 15th International Display Workshops, Dec. 3, 2008, pp. 1637-1640.Applicant
Tsuda, K et al., “Ultra Low Power Consumption Technologies for Mobile TFT-LCDs,” IDW '02 : Proceedings of the 9th International Display Workshops, Dec. 4, 2002, pp. 295-298.Applicant
Ueno, K et al., “Field-Effect Transistor on SrTiO3 With Sputtered AI2O3 Gate Insulator,” Appl. Phys. Lett. (Applied Physics Letters), Sep. 1, 2003, vol. 83, No. 9, pp. 1755-1757.Applicant
Van De Walle, C, “Hydrogen as a Cause of Doping in Zinc Oxide,” Phys. Rev. Lett. (Physical Review Letters), Jul. 31, 2000, vol. 85, No. 5, pp. 1012-1015.Applicant
Asakuma, N. et al., “Crystallization and Reduction of Sol-Gel-Derived Zinc Oxide Films by Irradiation With Ultraviolet Lamp,” Journal of Sol-Gel Science and Technology, 2003, vol. 26, pp. 181-184.Applicant
Asaoka, Y et al., “29.1: Polarizer-Free Reflective LCD Combined With Ultra Low-Power Driving Technology,” SID Digest '09 : SID International Symposium Digest of Technical Papers, 2009, pp. 395-398.Applicant
Chern, H et al., “An Analytical Model for the Above-Threshold Characteristics of Polysilicon Thin-Film Transistors,” IEEE Transactions on Electron Devices, Jul. 1, 1995, vol. 42, No. 7, pp. 1240-1246.Applicant
Cho, D et al., “21.2: Al and Sn-Doped Zinc Indium Oxide Thin Film Transistors for AMOLED Back-Plane,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 280-283.Applicant
Clark, S et al., “First Principles Methods Using CASTEP,” Zeitschrift fur Kristallographie, 2005, vol. 220, pp. 567-570.Applicant
Coates. D et al., “Optical Studies of the Amorphous Liquid-Cholesteric Liquid Crystal Transition: The Blue Phase,” Physics Letters, Sep. 10, 1973, vol. 45A, No. 2, pp. 115-116.Applicant
Costello, M et al., “Electron Microscopy of a Cholesteric Liquid Crystal and Its Blue Phase,” Phys. Rev. A (Physical Review. A), May 1, 1984, vol. 29, No. 5, pp. 2957-2959.Applicant
Dembo, H et al., “RFCPUS on Glass and Plastic Substrates Fabricated by TFT Transfer Technology,” IEDM 05: Technical Digest of International Electron Devices Meeting, Dec. 5, 2005, pp. 1067-1069.Applicant
Fortunato, E et al., “Wide-Bandgap High-Mobility ZnO Thin-Film Transistors Produced at Room Temperature,” Appl. Phys. Lett. (Applied Physics Letters), Sep. 27, 2004, vol. 85, No. 13, pp. 2541-2543.Applicant
Fung, T et al., “2-D Numerical Simulation of High Performance Amorphous In—Ga—Zn—O TFTs for Flat Panel Displays,” AM-FPD '08 Digest of Technical Papers, Jul. 2, 2008, pp. 251-252, The Japan Society of Applied Physics.Applicant
Godo, H et al., “P-9: Numerical Analysis on Temperature Dependence of Characteristics of Amorphous In—Ga—Zn—Oxide TFT,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 1110-1112.Applicant
Godo, H et al., “Temperature Dependence of Characteristics and Electronic Structure for Amorphous In—Ga—Zn—Oxide TFT,” AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 41-44.Applicant
Hayashi, R et al., “42.1: Invited Paper: Improved Amorphous In—Ga—Zn—O TFTs,” SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 621-624.Applicant
Hirao, T et al., “Novel Top-Gate Zinc Oxide Thin-Film Transistors (ZnO TFTs) for AMLCDS,” Journal of the SID , 2007, vol. 15, No. 1, pp. 17-22.Applicant
Hosono, H et al., “Working hypothesis to explore novel wide band gap electrically conducting amorphous oxides and examples,” J. Non-Cryst. Solids (Journal of Non-Crystalline Solids), 1996, vol. 198-200, pp. 165-169.Applicant
Hosono, H, “68.3: Invited Paper:Transparent Amorphous Oxide Semiconductors for High Performance TFT,” SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1830-1833.Applicant
Hsieh, H et al., “P-29: Modeling of Amorphous Oxide Semiconductor Thin Film Transistors and Subgap Density of States,” SID Digest '08 : SID International Symposium Digest of Technical Papers, 2008, vol. 39, pp. 1277-1280.Applicant
Ikeda, T et al., “Full-Functional System Liquid Crystal Display Using CG-Silicon Technology,” SID Digest '04 : SID International Symposium Digest of Technical Papers, 2004, vol. 35, pp. 860-863.Applicant
Janotti, A et al., “Native Point Defects in ZnO,” Phys. Rev. B (Physical Review. B), 2007, vol. 76, No. 16, pp. 165202-1-165202-22.Applicant
Janotti, A et al., “Oxygen Vacancies in ZnO,” Appl. Phys. Lett. (Applied Physics Letters), 2005, vol. 87, pp. 122102-1-122102-3.Applicant
Jeong, J et al., “3.1: Distinguished Paper: 12.1-Inch WXGA AMOLED Display Driven by Indium—Gallium—Zinc Oxide TFTs Array,” SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, No. 1, pp. 1-4.Applicant
Jin, D et al., “65.2: Distinguished Paper:World-Largest (6.5″) Flexible Full Color Top Emission AMOLED Display on Plastic Film and Its Bending Properties,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 983-985.Applicant
Kanno, H et al., “White Stacked Electrophosphorecent Organic Light-Emitting Devices Employing MOO3 as a Charge-Generation Layer,” Adv. Mater. (Advanced Materials), 2006, vol. 18, No. 3, pp. 339-342.Applicant
Kikuchi, H et al., “39.1: Invited Paper: Optically Isotropic Nano-Structured Liquid Crystal Composites for Display Applications,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 578-581.Applicant
Kikuchi, H et al., “62.2: Invited Paper: Fast Electro-Optical Switching in Polymer-Stabilized Liquid Crystalline Blue Phases for Display Application,” SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1737-1740.Applicant
Kikuchi, H et al., “Polymer-Stabilized Liquid Crystal Blue Phases,” Nature Materials, Sep. 1, 2002, vol. 1, pp. 64-68.Applicant
Kim, S et al., “High-Performance oxide thin film transistors passivated by various gas plasmas,” The Electrochemical Society, 214th ECS Meeting, 2008, No. 2317, 1 page.Applicant
Kimizuka, N et al., “Spinel,YBFE2O4, and YB2FE3O7 Types of Structures for Compounds in the In2O3 and Sc2O3—A2O3—Bo Systems [A; Fe, Ga, or Al; B: Mg, Mn, Fe, Ni, Cu,or Zn] at Temperatures Over 1000° C.,” Journal of Solid State Chemistry, 1985, vol. 60, pp. 382-384.Applicant
Kimizuka, N et al., “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m (m=3, 4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m (m=7, 8, 9, and 16) in the In2O3—ZnGa2O4—ZnO System,” Journal of Solid State Chemistry, Apr. 1, 1995, vol. 116, No. 1, pp. 170-178.Applicant
Kitzerow, H et al., “Observation of Blue Phases in Chiral Networks,” Liquid Crystals, 1993, vol. 14, No. 3, pp. 911-916.Applicant
Kurokawa, Y et al., “UHF RFCPUS on Flexible and Glass Substrates for Secure RFID Systems,” Journal of Solid-State Circuits , 2008, vol. 43, No. 1, pp. 292-299.Applicant
Lany, S et al., “Dopability, Intrinsic Conductivity, and Nonstoichiometry of Transparent Conducting Oxides,” Phys. Rev. Lett. (Physical Review Letters), Jan. 26, 2007, vol. 98, pp. 045501-1-045501-4.Applicant
Lee, H et al., “Current Status of, Challenges to, and Perspective View of AM-OLED,” IDW '06 : Proceedings of the 13th International Display Workshops, Dec. 7, 2006, pp. 663-666.Applicant
Lee, J et al., “World's Largest (15-Inch) XGA AMLCD Panel Using IGZO Oxide TFT,” SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 625-628.Applicant
Lee, M et al., “15.4: Excellent Performance of Indium—Oxide-Based Thin-Film Transistors by DC Sputtering,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 191-193.Applicant
Li, C et al., “Modulated Structures of Homologous Compounds InMO3(ZnO)m (M=In,Ga; m=Integer) Described by Four-Dimensional Superspace Group,” Journal of Solid State Chemistry, 1998, vol. 139, pp. 347-355.Applicant
Masuda, S et al., “Transparent thin film transistors using ZnO as an active channel layer and their electrical properties,” J. Appl. Phys. (Journal of Applied Physics), Feb. 1, 2003, vol. 93, No. 3, pp. 1624-1630.Applicant
Meiboom, S et al., “Theory of the Blue Phase of Cholesteric Liquid Crystals,” Phys. Rev. Lett. (Physical Review Letters), May 4, 1981, vol. 46, No. 18, pp. 1216-1219.Applicant
Miyasaka, M, “Suftla Flexible Microelectronics on Their Way to Business,” SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1673-1676.Applicant
Mo, Y et al., “Amorphous Oxide TFT Backplanes for Large Size AMOLED Displays,” IDW '08 : Proceedings of the 6th International Display Workshops, Dec. 3, 2008, pp. 581-584.Applicant
Nakamura, “Synthesis of Homologus Compound with New Long-Period Structure,” NIRIM Newsletter, Mar. 1995, vol. 150, pp. 1-4 with English translation.Applicant
Nakamura, M et al., “The phase relations in the In2O3—Ga2ZnO4—ZnO system at 1350° C.,” Journal of Solid State Chemistry, Aug. 1, 1991, vol. 93, No. 2, pp. 298-315.Applicant
Nomura, K et al., “Thin-Film Transistor Fabricated in Single-Crystalline Transparent Oxide Semiconductor,” Science, May 23, 2003, vol. 300, No. 5623, pp. 1269-1272.Applicant
Nomura, K et al., “Amorphous Oxide Semiconductors for High-Performance Flexible Thin-Film Transistors,” Jpn. J. Appl. Phys. (Japanese Journal of Applied Physics) , 2006, vol. 45, No. 5B, pp. 4303-4308.Applicant
Nomura, K et al., “Room-Temperature Fabrication of Transparent Flexible Thin-Film Transistors Using Amorphous Oxide Semiconductors,” Nature, Nov. 25, 2004, vol. 432, pp. 488-492.Applicant
Nomura, K et al., “Carrier transport in transparent oxide semiconductor with intrinsic structural randomness probed using single-crystalline InGaO3(ZnO)5 films,” Appl. Phys. Lett. (Applied Physics Letters) , Sep. 13, 2004, vol. 85, No. 11, pp. 1993-1995.Applicant
Nowatari, H et al., “60.2: Intermediate Connector With Suppressed Voltage Loss for White Tandem OLEDS,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, vol. 40, pp. 899-902.Applicant
Oba, F et al., “Defect energetics in ZnO: A hybrid Hartree-Fock density functional study,” Phys. Rev. B (Physical Review. B), 2008, vol. 77, pp. 245202-1-245202-6.Applicant
Oh, M et al., “Improving the Gate Stability of ZnO Thin-Film Transistors With Aluminum Oxide Dielectric Layers,” J. Electrochem. Soc. (Journal of the Electrochemical Society), 2008, vol. 155, No. 12, pp. H1009-H1014.Applicant
Ohara, H et al., “21.3: 4.0 In. QVGA AMOLED Display Using In—Ga—Zn—Oxide TFTs With a Novel Passivation Layer,” SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 284-287.Applicant