3D fin tunneling field effect transistor

[0001] Technical Field

[0002] The present invention relates to semiconductor devices, and more particularly to tunneling field effect transistors (TFETs) formed from fins to provide a greater effective channel width (W_eff).

[0003] Description of the Related Art

[0004] Tunneling FETs (TFETs) include an intrinsically better subthreshold slope (SS) and scaling capability than metal oxide semiconductor field effect transistors (MOSFETs). However, a primary problem of TFETs is their poor performance in drive current due to a limited effective channel width (Weff) for band-to-band tunneling. The poor performance has directed manufacturers away from using TFET technology.

[0005] A method for forming a tunneling field effect transistor includes forming gate structures over a semiconductor fin on a substrate having at least two pitches between the gate structures and recessing the fin between the gate structures. A first dielectric layer is deposited over the fin to fill in a first gap between the gate structures having a smaller pitch therebetween. A second gap between the gate structures having a larger pitch is filled with a second dielectric layer. The first gap is opened by etching the first dielectric layer while the second dielectric layer protects from opening the second gap. A source region is formed on the fin in the first gap. A dielectric fills the source region in the first gaps. The second gap is opened by etching the second dielectric layer and the first dielectric layer. A drain region is formed on the fin in the second gap.

[0006] Another method for forming a tunneling field effect transistor includes forming gate structures over a semiconductor fin on a substrate having at least two pitches between the gate structures; recessing the fin between the gate structures; depositing a first dielectric layer over the fin to fill in a first gap between the gate structures having a smaller pitch therebetween by employing pinch off to fill in the first gap while the second gap remains unfilled due to its larger dimension; filling a second gap between the gate structures having a larger pitch with a second dielectric layer; opening the first gap by etching the first dielectric layer while the second dielectric layer protects from opening the second gap; forming a source region on the fin in the first gap and along exposed vertical surfaces of the fin facing into the first gap; forming a dielectric fill on the source region in the first gaps; opening the second gap by etching the second dielectric layer and the first dielectric layer; and forming a drain region on the fin in the second gap and along exposed vertical surfaces of the fin facing into the second gap wherein the source region and the drain region include opposite dopant conductivities and the source region and the drain region occupy an entire width and height of the fin to increase a width of a channel formed longitudinally along the fin.

[0007] A tunneling field effect transistor (TFET) includes gate structures formed over a semiconductor fin on a substrate having at least two pitches between the gate structures including a first gap having a smaller pitch than a second gap having a larger pitch. A source region is formed in the fin across the first gap and extending to occupy an entire width and height of a fin cross-section, and a drain region is formed in the fin across the second gap and extending to occupy an entire width and height of a fin cross-section on a side opposite the source region on a gate structure.

[0008] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0038] In accordance with the present principles, tunneling FETs (TFETs) are provided using semiconductor fins to provide a channel. The TFETs include a three-dimensional (3D) structure, which provides better subthreshold slope (SS), scaling capability and drive current with an improved effective channel width (W_eff) for band-to-band tunneling. In one embodiment, asymmetrical source and drain regions are employed. The 3D structure of the TFET may be self-aligned without patterning source and drain regions (S/D regions) separately. This avoids a lithography step and the challenges associated with lithography including alignment problems. In addition, the 3D structures may be fabricated without S/D implantation. S/D implantation often leads to crystal damage and performance loss.

[0039] It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present invention.

[0040] It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0041] The present embodiments may include a design for an integrated circuit chip, which may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.

[0042] Methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

[0043] It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes Si_xGe_1-x where x is less than or equal to 1, etc. In addition, other elements may be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.

[0044] Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.

[0045] It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.

[0046] Referring now to the drawings in which like numerals represent the same or similar elements and initially to FIG. 1, a partially fabricated semiconductor device 10 is depicted in a perspective view in accordance with one illustrative embodiment. The device 10 may include a semiconductor-on-insulator (SOI) substrate 12, although other substrates and substrate materials may be employed. The SOI substrate 12 includes a bulk substrate 15, which may include Si, Ge, SiGe, SiC, III-V materials or any other suitable material. The SOI substrate 12 includes a buried dielectric layer 14, which may include an oxide, although other dielectric materials may be employed.

[0047] A semiconductor layer formed on the buried dielectric layer 14 is patterned into fins, for example a fin 24 shown in FIG. 1. The fins then have gate structures 32 formed over the fins, e.g., fin 24. The gate structures 32 include a dummy gate 22. The dummy gate 22 may include polysilicon. In a gate-first embodiment, a gate conductor (on a gate dielectric may be formed instead of the dummy gate 22.

[0048] The gate structures 32 are spaced apart by a small gate pitch 16 and a large gate pitch 18. The large gate pitch region 18 will be for the formation of a drain region 30 on the fin 24, and the small pitch region will be for the formation of a source region 28. The gate pitches may include a ratio (large/small) of between, e.g., about 1.2 to about 2.5.

[0049] The gate structures 32 include spacers 20 formed thereon. The spacers 20 may include a nitride material. A spacer stringer 26 is formed along a base of the fin 24 (like a spacer). The spacer stringer 26 may include a nitride material.

[0050] Referring to FIG. 2, the fin 24 is recessed between the gate structures 32. In one embodiment, a reactive ion etch (RIE) is performed to reduce the fin 24 selective to the dielectric materials of the gate structures 32. The etch process forms recesses 34 by reducing the source region 28 and the drain region 30 of the fin 24. This exposes an internal portion of the fin 24.

[0051] Referring to FIG. 3A, a dielectric layer 40 is formed over the structure of device 10. The deposition of the dielectric layer 40 causes pinch-off in the small gap 16 between gate structures 32, but not in the large gap 18 between the gate structures 32. The dielectric layer 40 may include an oxide, e.g., a silicon oxide, although other dielectric materials may be employed.

[0052] Referring to FIG. 3B, a cross-sectional view taken at section line B-B of FIG. 3A is depicted. Section line B-B cuts through the fin 24 in a longitudinal direction.

[0053] Referring to FIG. 4A, another dielectric layer 42 is formed over the structure of device 10. The deposition of the dielectric layer 42 fills in any remaining gaps. The dielectric layer 10 may include a nitride, e.g., a silicon nitride, although other dielectric materials may be employed. The dielectric layer 42 should be selectively etchable with respect to dielectric layer 40.

[0054] Referring to FIG. 4B, a cross-sectional view taken at section line B-B of FIG. 4A is depicted. Section line B-B cuts through the fin 24 in a longitudinal direction.

[0055] Referring to FIG. 5A, the dielectric layer 42 is planarized to form a planar top surface 44. The planarization may include a chemical mechanical polish (CMP), although other planarizing processes may be employed. The planarization process stops on the dielectric layer 40 and a slight overpolish may be acceptable.

[0056] Referring to FIG. 5B, a cross-sectional view taken at section line B-B of FIG. 5A is depicted. Section line B-B cuts through the fin 24 in a longitudinal direction.

[0057] Referring to FIG. 6A, the dielectric layer 40 is removed between gate structures 32 in the small pitch gap 16 by a wet etch process. The wet etch process is performed over the device 10 to remove the pinched off and exposed dielectric 40, but the dielectric layer 40 in the large gap 18 between gate structures 32 is protected by dielectric layer 42. The wet etch process may include an HF etch or equivalent. The wet etch process exposes the fin 24 in regions 46 between the gate structures 32.

[0058] Referring to FIG. 6B, a cross-sectional view taken at section line B-B of FIG. 6A is depicted. Section line B-B cuts through the fin 24 in a longitudinal direction.

[0059] Referring to FIG. 7A, a dopant donor layer 48 is deposited conformally over the device 10. The donor layer 48 may include boron or other dopants. In one embodiment, donor layer 48 includes B₂H₆.

[0060] Referring to FIG. 7B, a cross-sectional view taken at section line B-B of FIG. 7A is depicted. Section line B-B cuts through the fin 24 in a longitudinal direction. The donor layer 48 makes contact with the fin 24 in the small gap 16. After deposition of the donor layer 48, a drive-in process is performed to cause dopants from the donor layer 48 to diffuse into the fin 24 to form source regions 50. The drive-in process includes an anneal process to drive the dopants into the fin 24 where contact is made between the fin 24 and the donor layer 48. In one embodiment, the source regions 50 include SiB (SiB_x). In another embodiment, instead of depositing a donor layer 48 and performing a drive-in process, a doped epitaxial layer (not shown) may be selectively grown on exposed areas of the fin 24 (in the small gap 16). The doped epitaxial layer may include, e.g., B-doped SiGe. The selectively grown doped epitaxial layer would then be annealed to drive in dopants to form the source region 50. The epitaxial layer may then be removed.

[0061] The source region 50 is advantageously self-aligned on the fin 24 using the gate structures 32 to delineate the source region 50. The source region 50 is formed without lithographic patterning and without employing ion implantation to dope the source region 50.

[0062] Referring to FIG. 8A, an organic dielectric layer (ODL) 52 is deposited over the device 10 and planarized to fill the small gaps 16. The planarization of the ODL 52 may include CMP, although other planarizing processes may be employed. The planarization process stops on the dielectric layer 42.

[0063] Referring to FIG. 8B, a cross-sectional view taken at section line B-B of FIG. 8A is depicted. Section line B-B cuts through the fin 24 in a longitudinal direction.

[0064] Referring to FIG. 9A, dielectric layer 42 and dielectric layer 40 are removed from the large gap 18 to expose the fin 24. The dielectric layer 42 is removed selectively to the ODL 52 and materials of the gate structures 32. This is followed by the dielectric layer 40 being removed selectively to the ODL 52 and materials of the gate structures 32. The dielectric layer 42 may be removed by a wet or dry etch. Dielectric layer 40 may be removed by a wet etch, e.g., HF. This exposes the fin 24 in the large gap 18 in preparation of the formation of drain regions.

[0065] Referring to FIG. 9B, a cross-sectional view taken at section line B-B of FIG. 9A is depicted. Section line B-B cuts through the fin 24 in a longitudinal direction.

[0066] Referring to FIG. 10A, an optional ODL strip is performed to remove ODL 52 from the small gap 16. An anneal process is performed to oxidize the donor layer 48 to form a dielectric layer. An oxide clean process is then performed to clean the exposed fin 24 in preparation of the formation of a drain region. The clean process may include a diluted HF etch (DHF).

[0067] Referring to FIG. 10B, a cross-sectional view taken at section line B-B of FIG. 10A is depicted. Section line B-B cuts through the fin 24 in a longitudinal direction.

[0068] Referring to FIG. 11A, a drain region 56 is formed. The drain region 56 may be formed using an epitaxially grown layer 54 on the exposed fin 24 in the large gap 18. The epitaxially grown layer 54 includes a dopant that is driven into the fin 24 during a drive-in process (anneal). The epitaxially grown layer 54 may include, e.g., SiP to drive in P dopants. In one embodiment, the drain region 56 includes SiP_x. Other dopants may be employed. Note that the source region 50 and the drain region 56 include dopants of opposite conductivity as a feature of a TFET in accordance with the present principles.

[0069] In another embodiment, the drain region 56 may be formed similarly to the source regions 50. In this embodiment, a dopant donor layer (not shown) may be deposited (e.g., PH₃, AsH₃, etc.) over the device 10 and a drive-in process is performed to dope the fin 24 to form drain region 56.

[0070] The drain region 56 is advantageously self-aligned on the fin 24 using the gate structures 32 to delineate the drain region 56. The drain region 56 is formed without lithographic patterning and without employing ion implantation to dope the drain region 56.

[0071] Referring to FIG. 11B, a cross-sectional view taken at section line B-B of FIG. 11A is depicted. Section line B-B cuts through the fin 24 in a longitudinal direction.

[0072] Referring to FIG. 12A, the oxidized donor layer 48 is stripped from the device 10. The stripping process may include a boiling HNO₃ etch (e.g., 65%) or an Aqua Regia to strip out, e.g., oxidized B₂H₆.

[0073] Referring to FIG. 12B, a cross-sectional view taken at section line B-B of FIG. 12A is depicted. Section line B-B cuts through the fin 24 in a longitudinal direction. The fin sections (24) under the gate structures 32 provide a large effective channel width for tunneling charge. The source regions 50 and the drain regions 56 extend over the entire cross-section of the fins 24 and provide a high drive current over conventional planar devices due at least to the large effective channel width. The three-dimensional TFET is also isolated from the bulk substrate (15).

[0074] Referring to FIG. 13A, a replacement metal gate process is performed to remove the dielectric material 22 (e.g., polysilicon and hard mask) between spacers 20 by an etch process, e.g., RIE. Then, a gate dielectric 70 is formed in contact with the fin 24. The gate dielectric 70 may include high-k dielectric materials, e.g., HfO₂ or the like. Then, a gate conductor 68 is formed on the gate dielectric 70 between the spacers 20. The gate conductor 68 may include a metal, such as W, Cu, Al, etc.

[0075] A flowable dielectric layer 60 is then deposited over the device 10. The flowable dielectric layer 60 may include an oxide material. A lithography process is employed to define an etch mask for etching contact openings 62. The contact openings 62 are etched down to the source region 50 and the epitaxially grown layer 54. The etch process may form a recess notch 64 in the epitaxially grown layer 54. This increases contact area for the later formed contacts.

[0076] Referring to FIG. 13B, a cross-sectional view taken at section line B-B of FIG. 13A is depicted. Section line B-B cuts through the fin 24 in a longitudinal direction. The epitaxially grown layer 54 is etched further to form the recess notch 64 to increase contact area and therefore reduce contact resistance to the drain region 54/56 by a contact.

[0077] Referring to FIG. 14, a cross-sectional view taken at a same position as section line B-B of FIG. 13A is depicted. Section line B-B cuts through the fin 24 in a longitudinal direction. A liner 72 is formed in the contact openings 62. This is followed by a conductive material deposition process to form contacts 74. The liner 72 may include Ti, TiN, TaN, NiPt, Ni, etc. The conductive material deposition may include W, Al, Cu or other metals. A CMP or other planarizing process is performed to remove the liner 72 and conductive material for contacts 74 from a top surface.

[0078] Referring to FIG. 15, a cross-sectional view taken at a same position as section line B-B of FIG. 13A is depicted. Section line B-B cuts through the fin 24 in a longitudinal direction. Gate contact openings are etched though the flowable dielectric layer 60 and gate contacts 76 are formed. The gate contacts 76 land on the gate conductor 68. The gate contacts 76 may include W, Al, Cu or similar metals. A CMP or other planarizing process is performed to remove the material for gate contacts 76 from a top surface.

[0079] The source region 50 and the drain region 56 are formed across the entire width and the entire height of fin channel sections 24′. This optimizes the effective channel width and permits the TFET device 10 to overcome performance issues encountered by conventional devices.

[0080] Referring to FIG. 16, a comparison of a metal oxide semiconductor field effect transistor (MOSFET) 100 versus a tunneling field effect transistor (TFET) 102 is shown. The MOSFET 100 includes a same doping conductivity (N++) for source (S) and drain (D) regions. The TFET 110 includes different doping conductivity for source (S) (P++) and drain (D) (N++) regions. The MOSFET 100 conducts over an energy barrier (Fermi energy (E_F)) when a gate voltage (Vg) is applied to a gate (G). The TFET 110 conducts or tunnels through an energy barrier when the gate voltage (Vg) is applied to the gate (G).

[0081] Referring to FIG. 17, methods for forming a tunneling field effect transistor are illustratively shown. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

[0082] In block 202, gate structures are formed over a semiconductor fin on a substrate having at least two pitches between the gate structures. The gate structures may include dummy gate structures although the gate structures may include active gate structures in a gate first process. In block 204, the fin is recessed between the gate structures. The recess exposes vertical surfaces of the fin. Recessing the fin between the gate structures enables the source region and the drain region to be formed to occupy an entire width and height of the fin to increase a width of a channel formed longitudinally along the fin.

[0083] In block 206, a first dielectric layer is deposited over the fin to fill in a first gap between the gate structures having a smaller pitch therebetween. In one embodiment, the first dielectric layer fills in the first gap by employing pinch off during the depositing to fill in the first gap while the second gap remains unfilled due to its larger dimension.

[0084] In block 208, a second gap between the gate structures having a larger pitch is filled with a second dielectric layer. In block 210, the first gap is opened by etching the first dielectric layer while the second dielectric layer protects from opening the second gap.

[0085] In block 212, a source region is formed on the fin in the first gap. In block 213, a dopant donor layer is deposited. In block 215, dopants are driven into the fin with an anneal process. The donor dopant layer is oxidized and stripped off later in the process before forming the drain region. In an alternate embodiment, the source region is formed by epitaxially growing a dopant donor layer selectively on the fin in the first gap in block 217. In block 219, dopants are driven into the fin with an anneal process. The dopant donor layer may be removed.

[0086] In block 220, a dielectric fill is provided on the source region in the first gaps. The dielectric fill may include an ODL and has a selectivity to permit removal of oxide and nitrides with respect to the ODL. In block 222, the second gap is opened by etching the second dielectric layer and the first dielectric layer.

[0087] In block 224, a drain region is formed on the fin in the second gap. In block 225, the drain region formation on the fin in the second gap may include depositing a dopant donor layer. In block 227, dopants are driven in with an anneal process.

[0088] In an alternate embodiment, the drain may be formed by epitaxially growing a dopant donor layer selectively on the fin in the second gap in block 229. In block 231, dopants are driven in with an anneal process. The dopant donor layer may remain as part of the drain region in any embodiment. The source region and the drain region include opposite dopant conductivities to form a TFET.

[0089] In block 232, a replacement metal gate process may be performed to replace a dummy gate with active gates. In block 234, source and drain contacts are formed in a patterned interlevel dielectric (ILD) layer. In block 236, gate contacts are formed in the ILD In block 238, processing continues.

[0090] Having described preferred embodiments 3D fin tunneling field effect transistor (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims.