Conductive pad structure for hybrid bonding and methods of forming same

[0001] The present invention relates generally to bonding, and, in particular embodiments, a conductive pad structure for hybrid bonding and methods of forming same.

[0002] Typically, in a semiconductor device, various electronic components (e.g., transistors, diodes, resistors, capacitors, and the like) are formed in device dies on a wafer. These device dies may then be sawed and bonded to other device dies to form functional devices. For example, in image sensing technologies, a complementary metal-oxide semiconductor (CMOS) image sensor (CIS) may include pixel arrays (e.g., connected to photo diodes) formed on one device die, and logical control circuits may be formed on another device die. These separate dies may be bonded together using a hybrid bonding process to form a functional device. Hybrid bonding is also used in other applications to form three dimensional integrated circuits (3DICs) where multiple dies are stacked on one another.

[0003] In hybrid bonding, conductive pads on a top surface of one die may be directly bonded to conductive pads on a top surface of the other die, for example, using fusion bonding and annealing processes. However, as a result of the annealing process, the material of the conductive pads may be stretched (e.g., as a result of increased ductility) and voids may be formed between the bonded conductive pads, especially in the corner regions.

[0017] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0018] The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.

[0019] A conductive pad structure for hybrid bonding and the method of forming the same are provided in accordance with an embodiment. The intermediate stages of manufacturing an embodiment are illustrated. The variations of the embodiments are then discussed.

[0020] Embodiments will be described with respect to a specific context, namely hybrid bonding of stacked device dies for image sensing. Other embodiments may also be applied, however, to other applications of bonding device dies such as in 3DIC packages.

[0021] FIGS. 1 through 9 illustrate cross-sectional views of intermediary steps of forming a conductive pad for hybrid bonding in accordance with various embodiments. FIG. 1 illustrates a cross-sectional view of a portion of a first device die 100. In image sensing technologies, first device die 100 may include photodiodes interconnected to form a pixel array. First device die 100 includes a substrate 102, which may be a bulk silicon substrate although other semiconductor materials including group III, group IV, and group V elements may also be used. Alternatively, substrate 102 may be a silicon-on-insulator (SOI) substrate. Active devices (not shown) such as transistors and photodiodes may be formed on the top surface of substrate 102.

[0022] First device die 100 further includes interconnect layers 104 formed over substrate 102. Interconnect layers 104 may include an inter-layer dielectric (ILD) and/or inter-metal dielectric layers (IMD) containing conductive features (e.g., metal lines and vias, not shown) formed over substrate 102 using any suitable method. Interconnect layers 104 may connect various active devices in substrate 102 to form functional circuits. The ILD/IMDs may comprise low-k dielectric materials having k values, for example, lower than about 4.0 or even 2.8. In some embodiments, interconnect layers 104 may comprise un-doped silicate glass (USG), and the like. Interconnect layers 104 may have a thickness of about 2200 Å although the actual dimensions of interconnect layers 104 may vary depending on layout design.

[0023] An isolation layer 106 may be formed over interconnect layers 104. Isolation layer 106 may comprise silicon nitride, silicon oxide, or the like. Isolation layer 106 may have a thickness of about 500 Å, although the actual dimension isolation layer 106 may vary depending on layout design.

[0024] Redistribution layers (RDLs) 108 may be formed over isolation layer 106. RDLs 108 may comprise polymer layers or dielectric layers (e.g., comprising USG) having interconnect structures (e.g., metal lines and vias) that route the electrical circuits formed in interconnect layers 104 to desired locations in first device die 100. RDLs 108 may have a thickness of about 3000 Å, although the actual dimensions RDLs 108 may vary depending on layout design.

[0025] An oxide layer 110 is formed on a top surface of first device die 100. Oxide layer 110 may comprise silicon oxynitride (SiON), SiO₂, SiN, SiC, or the like. Oxide layer 110 may have a thickness of about 3000 Å and may be used as a bonding interface layer for bonding first device die 100 to another device die during a subsequent hybrid bonding process (described further herein in FIGS. 8 and 9). Although oxide layer 110 is described herein as an oxide layer, any interfacial layer suitable for direct bonding to another interfacial layer (e.g., through fusion bonding) may be used in alternative embodiments in lieu of an oxide.

[0026] FIG. 2 illustrates the patterning of first device die 100 to form an opening 112 for a conductive pad. First device die 100 may be patterned, for example, using a combination of photolithography and etching. While FIG. 2 illustrates opening 112 extending through oxide layer 110 into RDLs 108, the layers of first device die 100 that are patterned for opening 112 may vary depending on a desired depth of opening 112. For example, opening 112 may have a depth from a top surface of first device die 100 of between about 0.1 μm and about 1 μm.

[0027] FIG. 3 illustrates the formation of a liner 114 over oxide layer 110 and covering sidewalls and a bottom surface of opening 112. Liner 114 may be deposited using any conformal deposition method such as chemical vapor deposition (CVD), or the like. Liner 114 may comprise silicon nitride, titanium nitride, titanium oxide, or any material that may be removed at a greater rate than oxide layer 110 and RDLs 108. In various embodiments, liner 114 may be between about 300 Å and about 1000 Å or more thick.

[0028] FIG. 4 illustrates another patterning of first device die 100 to extend opening 112 further into first device die 100. This second patterning may be achieved, for example, using an anisotropic etching process so that the vertical dimension of opening 112 is increased without substantially increasing the horizontal dimensions of opening 112. As a result of the patterning, lateral portions of liner 114 (e.g., covering oxide layer 110 and bottom surfaces of opening 112) may be removed. That is, a top surface of oxide layer 110 may be exposed. Vertical portions of liner 114 (e.g., on sidewalls of opening 112) may remain in first device die 100. After the second patterning, liner 114 may only partially cover sidewalls of opening 112. Furthermore, as a result of the patterning, oxide layer 110 may be thinned. For example, in embodiments where oxide layer 110 was deposited to have a thickness of about 5000 Å, after the patterning, oxide layer 110 may have a thickness of about 2500 Å. Furthermore, because the etching rate of liner 114 may be greater than the etching rate of oxide layer 110, less oxide layer 110 may be removed than liner 114 during etching. Thus, a top surface of oxide layer 110 may or may not be substantially level with a top surface of liner 114.

[0029] While FIG. 4 illustrates opening 112 extending through oxide layer 110, RDLs 108, and isolation layer 106 into interconnect layers 104, the layers of first device die 100 that are patterned to extend opening 112 may vary depending on a desired depth of opening 112. For example, opening 112 may have a depth from a top surface of first device die 100 after expansion of between about 0.2 μm and about 2 μm.

[0030] In FIG. 5, remaining portions of liner 114 are selectively removed using any suitable method, such as an etching process using a chemical etchant that etches liner 114 at a faster rate than device layers contacting liner 114 (e.g., oxide layer 110 and RDLs 108). For example, a solution of 85% phosphoric acid (H₃PO₄) may be used when liner 114 comprises SiN, oxide layer 110 comprises SiON, and RDLs 108 comprise USG. The exact chemistry used during etching may vary depending on the materials used to form the applicable device layers in first device die 100. In various embodiments, a ratio of removal rates of liner 114 to oxide layer 110 to RDLs 108 may be about 60 to 30 to 1. Furthermore, because oxide layer 110 may have a higher removal rate than RDLs 108, sidewalls of oxide layer 110 may or may not be vertically aligned with sidewalls of RDLs 108 in opening 112.

[0031] As a result of removing liner 114, a top portion of opening 112 has a horizontal dimension W1 that is larger than a horizontal dimension W2 of a bottom portion of opening 112. Horizontal dimensions W1 and W2 may be a length/width, diameter, or the like depending on a top down shape of opening 112. In various embodiments, horizontal dimensions W1 and W2 may be between about 0.1 μm and 10 μm. A difference in dimension between W1 and W2 may depend on the thickness of liner 114. For example, in embodiments where liner 114 was about 500 Å thick, W1 may be about 0.1 μm larger than W2. Generally, a difference between W1 and W2 may be at least about 0.05 μm.

[0032] FIG. 6 illustrates the filling of opening 112 with a conductive material 116, for example, copper or a copper alloy. The filling of opening 112 may include an electro-chemical plating (ECP) process. Conductive material 116 may overflow opening 112 and cover a top surface of oxide layer 110. In various embodiments, a barrier layer (not shown) and/or a seed layer (not shown) may be formed, for example, using physical vapor deposition, CVD, or the like in opening 112 prior to the filling of opening 112 with conductive material 116.

[0033] Subsequently, as illustrated by FIG. 7, a planarization (e.g., a chemical mechanical polish (CMP)) may be performed to remove overflow portions of conductive material 116 to form conductive pad 118 in first device die 100. The planarization may result in the dishing of conductive pad 118 (i.e., a top surface of conductive pad 118 may be non-planar and concave). This dishing may be intentional to allow room for conductive pad 118 to expand in a subsequent annealing process. The dishing may remove a depth H1 of conductive pad 118, and the planarization process may be controlled so that depth H1 is less than about 50 Å to ensure proper bonding of first device die 100 to another device die.

[0034] As a result of the process steps illustrated by FIGS. 1 through 7, conductive pad 118 is formed in first device die 100. Additionally, in an embodiment, conductive pad 118 is formed of a single continuous material (e.g., copper) having no internal interfaces formed therein. Conductive pad 118 is shaped to include a top portion having a horizontal dimension W1 and a vertical dimension H2. Conductive pad 118 further includes a bottom portion having a horizontal dimension W2 and a vertical dimension H3. In various embodiments, horizontal dimension W1 is larger than horizontal dimension W2. Horizontal dimensions W1 and W2 may be between about 0.1 μm and about 10 μm. Horizontal dimensions W1 and W2 may be a length/width, diameter, or the like depending on a top-down shape of conductive pad 118. Centerlines of the top and bottom portions may be vertically aligned.

[0035] In a top down view, conductive pad 118 may have any shape such as a square, rectangle, circle, oval, or the like. Furthermore, vertical dimensions H1 and H2 of the top and bottom portions of conductive pad 118, respectively, may or may not be equal, and vertical dimensions H1 and H2 may be between about 0.1 μm and about 1 μm.

[0036] Thus, as illustrated by FIG. 7, the shape of conductive pad 118 provides for additional metallic material in center regions 118A of conductive pad 118 compared to corner regions 118B of conductive pad 118. This shape of conductive pad 118 reduces the overall surface stress of conductive pad 118. For example, in simulations where conductive pad 118 comprises copper and the dimensions of W1, W2, H2, and H3 are 1 μm, 0.5 μm, 0.5 μm, and 1 μm, respectively, the thermal stress at the surface of conductive pad 118 is 4.938×10⁻⁵ Newtons. However, in simulations where the dimensions of W1, W2, H2, and H3 were 1 μm, 0 μm, 0.5 μm, and 0 μm, respectively, (e.g., where the metallic material was uniformly distributed), the surface stress of the conductive pad was higher at 5.977×10⁻⁵ Newtons. The reduction of surface stress reduces the probability of forming voids, particularly in corner regions 118B, during subsequent bonding processes. Although FIG. 7 only illustrates first device die 100 having a single conductive pad 118, first device die 100 may include multiple conductive pads 118 formed simultaneously.

[0037] FIGS. 8A through 9 illustrate the bonding of first device die 100 to a second device die 200 through hybrid bonding. In image sensing technologies, second device die 200 may include logical control circuits for controlling the pixel array in first device die 100. Second device die 200 may include a substrate 202 (e.g., having active devices, not shown), interconnect layers 204 (e.g., forming logic control circuits), an isolation layer 206, RDLs 208, and an oxide layer 210. The various layers of second device die 200 may be substantially similar to the layers of first device die 100, and detailed description of these device layers is omitted for brevity. Second device die 200 further includes a conductive pad 218, which may be substantially similar in shape to conductive pad 118.

[0038] FIG. 8A illustrates the bonding of oxide layers 110 and 210 using, for example, a fusion bonding process. In various embodiments, the fusion bonding may be done using a bonding tool 300 illustrated in FIG. 8B. The bonding may begin by loading first device die 100 and second device die 200 into load ports 302A and 302B, respectively. A movement module 304 may move first device die 100 to a surface activation module 306. In an embodiment, surface activation module 306 may be a plasma module that exposes the surface of oxide layer 110 to a plasma environment. Alternatively, surface activation module 306 may be a wet cleaning module that performs a wet clean to activate the surface of oxide layer 110. For example, oxide layer 110 may be cleaned using a procedure such as an SC-1 or SC-2 cleaning procedure to form a hydrophilic surface. In yet another alternative, surface activation module 306 may be an etching module that treats the surface of oxide layer 110 to form a hydrophobic surface, for example, using an etching solution of hydrogen fluoride (HF) or ammonium fluoride (NH₄F).

[0039] Subsequently, movement module 304 may move first device die 100 to a cleaning module 308 to clean the surface of oxide layer 110. Movement module 304 may move first device die 100 to a bonding module 310 to await bonding. Movement module 304 may also move second device die 200 to surface activation module 306. A similar surface activation treatment may be applied to a surface of oxide layer 210 as the treatment applied to oxide layer 110. For example, a plasma treatment, wet cleaning, or etching may be applied to the surface of oxide layer 210 depending on the surface activation process used on oxide layer 110. Subsequently, the movement module 304 may move second device die 200 to cleaning module 308 to clean the surface of oxide layer 210, and second device die 200 may be moved to bonding module 310 for bonding with first device die 100.

[0040] Bonding module 310 may include an alignment tool to align oxide layers 110 and 210 of first device die 100 and second device die 200. Oxide layers 110 and 210 are then contacted together to begin the hybrid bonding procedure. At this stage, conductive pads 118 and 218 may not be bonded, and a void 120 may be disposed between conductive pads 118 and 218 due to dishing.

[0041] After oxide layer 110 is in contact with oxide layer 210, a thermal annealing process may be utilized to strengthen the bond between oxide layers 110 and 210 and to additionally bond conductive pads 118 and 218 as illustrated by FIG. 9. The annealing process conditions may include increasing the temperature of first and second device dies 100 and 200 from room temperature (e.g., about 20° Celsius (C.)) to a suitable annealing temperature (e.g., between about 150° C. and about 400° C.) at a rate of 5° C. per minute. The temperature of first and second device dies 100 and 200 may be maintained at the annealing temperature for about two hours. The annealing process expands the conductive material of conductive pads 118 and 218 to fill void 120, bonding conductive pads 118 and 218 and electrically connecting first and second device dies 100 and 200. As a result of the shape of conductive pads 118 and 218 and reduced surface stress, the bonded conductive pads 118 and 218 may be substantially free of voids. Furthermore, the reduced surface stress may allow for the annealing process to be performed in easier process conditions (e.g., at a lower temperature).

[0042] FIG. 10 illustrates a process flow 400 for hybrid bonding device dies in accordance with various embodiments. In step 402, a die (e.g., first device die 100) is patterned to form an opening. The die may include an oxide layer (e.g., oxide layer 110) at a top surface, which may be used as a bonding interface in hybrid bonding. Next, in step 404, a liner (e.g., liner 114) is formed over the die and covering sidewalls and a bottom surface of the opening. The liner may be formed of any material that may be selectively removed at a greater rate than any layers of first device die 100 in physical contact with the liner.

[0043] In step 406, another etching is performed in first device die 100 to expand the opening further into the die, for example, using an anisotropic etching process. The anisotropic etching may not substantially expand the opening in a lateral direction. As a result of the etching, lateral portions of the liner (e.g., covering a top surface of the die and bottom surface of the opening) may be removed. Remaining portions of the liner on sidewalls of the opening may not be removed and may partially cover sidewalls of the expanded opening.

[0044] In step 408, the liner is removed, for example by selecting a chemical etchant that selectively removes the liner without significantly removing other portions of the device die. For example, when the liner comprises SiN and the other device layers in contact with the liner comprise SiON and USG, a solution of 85% phosphoric acid may be used to remove the liner. As a result of removing the liner, a top portion of the opening may have a first width that is larger than a second width of a bottom portion of the opening.

[0045] In step 410, the opening is filled with a metallic material (e.g., copper). The filling of the metallic material may overflow the opening. Subsequently, in step 412, a CMP may be performed to remove excess metallic material to form a conductive pad. The CMP process may further dish a top surface of the conductive pad (i.e., form a non-planar, concave top surface). This dishing may be intentional to allow expansion room for the conductive pad during a subsequent bonding process. The resulting conductive pad may have a center portions having additional conductive material than corner portions. This shape of the resulting conductive pad reduces the thermal stress on a top surface of the conductive pad.

[0046] In step 414, the oxide layer of the die may be bonded (e.g., fusion bonded) to an oxide layer of another device die. The other device die may also have a second conductive pad that is substantially similar, particularly in shape, to the conductive pad formed in steps 402 through 412. The bonding of the oxide layers may not bond the conductive pads, and a void may be defined between the conductive pads due to dishing.

[0047] Finally, in step 416, an annealing process is performed to bond the two conductive pads and fill the void. The annealing process may be performed by ramping up the temperature of the bonded dies from room temperature to 300° C. at a rate of 5° C. per minute. The temperature of the bonded dies may be maintained at about 300° C. for about two hours. As a result of the shape of the conductive pads and the reduced thermal stress, the resulting bonded conductive pads may be substantially free of any voids.

[0048] FIGS. 11A through 11C illustrate varying views of a bonded first and second device dies 100 and 200 in an example embodiment where first device die 100 is a CMOS image sensor (CIS) die and second device die 200 is a logic control die. FIG. 11A shows a cross-sectional view, FIG. 11B illustrates an in-depth view of the cross-sectional view of FIG. 11A, and FIG. 11C illustrates a top down view. First device die 100 may include photodiodes 101, transfer transistors 103, and metallization layers 105 (e.g., interconnect layers 104). Metallization layers 105 may electrically connect photodiodes 101 and transfer transistors 103 to form functional circuits. These functional circuits may include a pixel array in a center region of first device die 100 as illustrated by FIG. 11C. The functional circuits of first device die 100 may also include an analogue to digital convertor (ADC) 107, correlated double sampling (CDS) circuits 109, a row decoder 111, and the like. As also illustrated by FIG. 11C, a plurality of conductive pads 118 for bonding may be disposed on peripheral regions of first device die 100.

[0049] Second device die 200 may include logic arrays 201 and metallization layers 205 (e.g., interconnect layers 204). The metallization layers may interconnect logic arrays 201 to form digital signal processing circuits (e.g., application specific integrated circuits (ASIC)) that provide control functions for the image sensor formed by first device die 100 and second device dies 200 as also illustrated by FIG. 11C. A plurality of conductive pads 218 may be located at peripheral regions the top surface of second device die 200.

[0050] FIG. 11B illustrates a detailed cross-sectional view of a portion 100A/200A of bonded first and second device dies 100 and 200. Hybrid bonding may be used to bond oxide layer 110 and conductive pads 118 of first device die 100 to oxide layer 210 and conductive pads 218 of second device die 200, respectively. Conductive pads 118 and 218 are shaped so that center portions of conductive pads 118 and 218 are thicker (e.g., has more conductive material) than corner regions of conductive pads 118 and 218. This shape of conductive pads 118 and 218 reduces thermal stress at the interface between conductive pads 118 and 218, which reduces the formation of voids after hybrid bonding.

[0051] In accordance with an embodiment, a method includes patterning an opening through a layer at a surface of a device die. The method further includes forming a liner on sidewalls of the opening, patterning the device die to extend the opening further into the device die. After patterning the device die, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.

[0052] In accordance with another embodiment, a method includes etching a first opening through an oxide layer on a surface of a first device die. The first opening has a first horizontal dimension. A liner is formed over the first device die. The liner covers sidewalls and a bottom surface of the first opening. The method further includes etching a second opening connected to the first opening in the first device die by etching through first portions of the liner on the bottom surface of the first opening. The second opening has a second horizontal dimension smaller than the first horizontal dimension. Second portions of the liner on sidewalls of the first opening are removed. A first conductive pad is formed in the first and second openings, and the first device die is bonded to a second device die. The first conductive pad is bonded to a second conductive pad on a surface of the second device die.

[0053] In accordance with yet another embodiment, a device includes an oxide layer at a top surface of a device die and a conductive pad in the device die. The conductive pad includes a top portion at the top surface of the first device die having a first horizontal dimension and a bottom portion connected to the top portion with no internal interface between the top portion and the bottom portion. The bottom portion has a second horizontal dimension, and the first horizontal dimension is larger than the second horizontal dimension.

[0054] While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.