Electrostatic chuck including declamping electrode and method of declamping

[0001] The invention relates to improvements in electrostatic chuck designs and methods of declamping wafers.

[0002] Various chucking arrangements have been developed for clamping wafers during processing thereof in vacuum chambers such as plasma etch chambers, plasma enhanced physical vapor deposition chambers, chemical vapor deposition chambers, plasma enhanced chemical vapor deposition chambers, and atomic layer deposition chambers. One challenge has been the residual sticking force between the wafer and the chuck during declamping operations. Thus, there is a need for improved chuck designs and methods of declamping which address the sticking problem.

[0003] Disclosed herein is a semiconductor wafer processing apparatus for processing semiconductor wafers. The processing apparatus comprises a processing chamber in which a semiconductor wafer is processed, a process gas source in fluid communication with the processing chamber adapted to supply process gas into the processing chamber, a vacuum source adapted to exhaust process gas and byproducts of the processing from the processing chamber, and an electrostatic chuck assembly comprising a support surface in a layer of ceramic material on which the semiconductor wafer is supported during processing of the wafer in the chamber; at least one electrostatic clamping electrode embedded in the layer of ceramic material, the at least one electrostatic clamping electrode operable to apply an electrostatic clamping force to the wafer on the support surface when an electrostatic clamping voltage is applied to the clamping electrode; and at least one declamping electrode embedded in the layer of ceramic material above the at least one electrostatic clamping electrode operable to provide a path for draining any residual charge between the wafer and the support surface when the electrostatic clamping voltage is no longer applied to the clamping electrode.

[0004] Also disclosed herein is an electrostatic chuck assembly useful in a semiconductor wafer processing chamber of a semiconductor wafer processing apparatus. The electrostatic chuck assembly comprises a support surface in a layer of ceramic material on which a semiconductor wafer is supported during processing of the wafer in the chamber, at least one electrostatic clamping electrode embedded in the layer of ceramic material, the at least one electrostatic clamping electrode operable to apply an electrostatic clamping force to a wafer on the support surface when an electrostatic clamping voltage is applied to the clamping electrode, and at least one declamping electrode embedded in the layer of ceramic material above the at least one electrostatic clamping electrode operable to provide a path for draining any residual charge between the wafer and the support surface when the electrostatic clamping voltage is no longer applied to the clamping electrode.

[0005] Further disclosed herein is a method of declamping a semiconductor wafer from a support surface of an electrostatic chuck assembly after processing the semiconductor wafer. The method comprises supplying the process gas from the process gas source into the processing chamber, processing a semiconductor wafer in the processing chamber while applying a voltage to the at least one electrostatic clamping electrode so as to clamp the semiconductor wafer to the support surface of the electrostatic chuck assembly while electrically floating the at least one declamping electrode during the processing, and shutting off the voltage to the electrostatic clamping electrode and electrically connecting the declamping electrode to a conductive path after processing the semiconductor wafer to provide a path for draining any residual charge between the wafer and the support surface with the at least one declamping electrode thereby declamping the wafer from the support surface of the electrostatic chuck assembly.

[0014] Disclosed herein are embodiments of an electrostatic chuck with improved declamping capability for use in a semiconductor wafer processing apparatuses. The semiconductor wafer processing apparatus preferably includes a processing chamber (i.e. vacuum chamber) in which a semiconductor wafer is processed, a process gas source in fluid communication with the processing chamber adapted to supply process gas into the processing chamber, and a vacuum source adapted to exhaust process gas and byproducts of the processing from the processing chamber. The processing apparatus is preferably a plasma processing apparatus which further includes a RF energy source adapted to energize the process gas supplied into the processing chamber into a plasma state in the processing chamber. The semiconductor wafer processing apparatus also preferably includes a control system configured to control processes performed by the processing apparatus and a non-transitory computer machine-readable medium comprising program instructions for control of the processing apparatus. The processing chamber may be a plasma etching, a chemical vapor deposition chamber, a plasma enhanced chemical vapor deposition chamber, and atomic layer deposition chamber, a plasma enhanced atomic layer deposition apparatus, or the like (all of which are herein referred to as a vacuum chambers) of the semiconductor wafer processing apparatus. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present embodiments. It will be apparent, however, to one skilled in the art that the present embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure present embodiments disclosed herein. Additionally, as used herein, the term “about” when used with reference to numerical values refers to ±10%.

[0015] Electrostatic chuck assemblies (as used herein “ESCs”) are commonly used to clamp a wafer (e.g. Johnsen Rahbek effect or Coulombic effect) and provide thermal control of the wafer (i.e. semiconductor substrate) during semiconductor fabrication processes. ESCs provide a clamping force to hold the wafer thereon when voltage (DC or AC) is applied to one or more clamping electrodes in the ESC wherein the electrostatic clamping electrode can be a monopolar or bipolar electrostatic clamping electrode. Upon the removal of the applied voltage, clamp force is expected to go to zero wherein the wafer can be easily removed. The wafer and the one or more clamp electrodes act as the electrodes of a capacitor in the presence of externally applied electric field (through a power supply). The electrostatic chuck assembly preferably includes lift pins which are operable to lower a wafer onto the support surface of the ESC before the wafer is processed, and raise the wafer from the support surface of the ESC after the wafer has been processed. An exemplary embodiment of an electrostatic chuck assembly including lift pins which are operable to lower and raise a wafer can be found in commonly-assigned U.S. Pat. No. 6,567,258 which is incorporated by reference herein in its entirety.

[0016] While under ideal conditions, the clamp force between the wafer and the clamping electrode of the ESC vanishes completely when the externally applied voltage is turned off, this is not often true under actual conditions. For example, buildup of thin films on the support surface of the ESC can lead to charge trapping on the surface of the ESC assembly. Such a charge may take longer to dissipate relative to the externally applied field, and can result in a residual sticking force on the wafer even after the applied field is switched off. For example, buildup of thin films on the ESC support surface in plasma etching chambers can be caused by fluorination of the ESC (ceramic) surface by chamber clean processes. Additionally, by-products from plasma processing can deposit on the ESC support surface leading to films capable of trapping charge.

[0017] Smoothening of the ESC assembly support surface due to repeated processing of wafers can also lead to residual sticking force. Due to differences between the coefficient of thermal expansion between a wafer, (i.e. a silicon substrate) and the ESC with a ceramic support surface, the wafer surface grinds against the ESC ceramic when plasma heat load induces the heating of the wafer (and the consequently wafer expansion). Since the wafer is being held by the clamp force during processing, this grinding between the wafer and the ESC support surface results in significant smoothening of the ESC ceramic upon extended use. The smoothened ceramic support surface results in a significant increase in actual contact area between the wafer and the ESC. Further reduction of effective distance between the ESC support surface and the wafer backside increases the clamp force due to any charge present at the interface since the force varies at 1/d², where d is the distance between the wafer backside and the ceramic surface. Typically, the distance d is approximately equal to the roughness of the ESC surface (as shown in FIG. 1), so a smoother ESC surface results in a higher sticking force if any residual charge exists on the wafer surface. As mentioned previously, the residual charge may be present due to small amount of leakage current through the ESC ceramic or charge trapping by films on the ESC surface.

[0018] The residual sticking force on the wafer can lead to significant problems when the wafer is lifted up from the ESC surface including wafer popping, particle generation, and even wafer breakage.

[0019] While the wafer is clamped, small spaces/gaps between the wafer and the ESC support surface are preferably filled with helium (usually at pressures between 1-100 Torr) to provide an improved heat transfer coefficient relative to just physical contact between the wafer and the ESC.

[0020] FIG. 1 illustrates the residual forces between the rough ceramic support surface 2 of an ESC and a wafer 4 after removal of the clamping voltage. The residual sticking force can lead to problems when the wafer is lifted up from the ESC surface such as wafer popping, particle generation and even wafer breakage.

[0021] FIG. 2 shows an ESC assembly 40 (ESC) which is coupled to a control system 24 which is operable to control processes performed by the ESC such as raising and lowering lift pins (not shown) included therein. Holes 6 near the ESC edge deliver heat transfer gas (e.g. helium) to the backside of the wafer 4. The ESC assembly 40 has a support surface in a layer of ceramic material on which the semiconductor wafer 4 is supported. The support surface has a 1-10 mm outer annular edge seal 48 at an outer periphery thereof such that a clamped wafer is able to sustain up to about a 100 Torr pressure difference between the wafer backside and the pressure in the vacuum chamber of the semiconductor wafer processing apparatus such that the pressure of the heat transfer gas supplied to the backside of the wafer 4 can be maintained, thus enhancing thermal conductivity between the ESC 40 and wafer. Additionally, the ESC support surface includes a mesa pattern including a plurality of mesas 20 distributed on its upper surface such that contact area between the wafer 4 and the ESC surface is reduced. In such a configuration, about 3 to 10% of the area of the support surface is mesas 20 and the outer annular edge seal 48.

[0022] The mesas 20 can each have a height of about 5 to 40 microns. The mesas 20 can be of virtually any size, shape, and arrangement. For example, the mesas 20 can be elliptical, polygonal, and/or torroidal wherein the mesas 20 have vertical or sloped walls. The top surface of each of the mesas 20 can be concave, flat, or convex, and the corners can be sharp or rounded. The mesas 20 can take on a “bump” shape wherein a partial spherical shape is emerging from a flat surface. A preferred mesa shape and size is circular with vertical walls, wherein each mesa has a diameter of about 1 mm. Preferably the mesas 20 have a spacing of about 5 mm therebetween wherein the mesas substantially cover the ESC support surface.

[0023] The ESC ceramic 10 is preferably bonded onto a cooling plate (baseplate) 12 wherein the cooling plate has coolant channels 14 such that temperature of the cooling plate can be controlled by connecting the cooling plate to a temperature control unit (chiller) which circulates fluid. The thermal resistance of the bond layer 16 between the ceramic and the cooling plate can be selected such that temperature difference between the ceramic and the cooling plate can be between 2° C. and 90° C. at 10 W/cm² heat flux into the wafer 4. In addition, heaters (not shown) embedded in a heater layer 84 can form independently controllable heater zones to independently control and tune the spatial and temporal temperature of the support surface of ESC 40 as well as the spatial and temporal temperature of the wafer 4 supported on the support surface.

[0024] The ESC 40 includes at least one electrostatic clamping electrode, such as clamping electrode 8 and annular clamping electrode 8a, embedded inside the ESC ceramic layer 10 that are connected to an external power supply (not shown) to enable wafer clamping when an electrostatic clamping voltage is applied to the at least one clamping electrode. The electrostatic chuck assembly 40 also includes at least one declamping electrode, such as declamping electrode 18, embedded in the layer of ESC ceramic layer 10. The at least one declamping electrode is above the at least one electrostatic clamping electrode, wherein the at least one declamping electrode is operable to provide a path for draining any residual charge between the wafer 4 and the support surface of the ESC when the electrostatic clamping voltage is no longer applied to the at least one clamping electrode. For example, during wafer processing, the at least one declamping electrode is kept electrically floating such that it does not interfere with the at least one electrostatic clamping electrode. After the wafer has been processed, the control system 24 is configured to control a switch 41 such that conductive path 42 electrically connects the at least one declamping electrode 18 to ground or a voltage source, during declamping, such that any residual charge built up between the wafer 4 and the support surface may be drained. Again, the conductive path 42 can be connected to ground to drain any residual charge or alternatively the conductive path 42 can be connected to a voltage source wherein the voltage of the voltage source is selected such that any residual charge between the wafer and the support surface is drained such that the wafer 4 is declamped from the support surface of the ESC 40.

[0025] The at least one electrostatic clamping electrode 8 includes at least one pattern of an electrically conductive material and the at least one declamping electrode 18 includes at least one pattern of an electrically conductive material wherein the at least one pattern of the clamping electrode 8 and the at least one pattern of the declamping electrode 18 preferably overlap and have the same pattern. Preferably the at least one declamping electrode 18 included in the ESC assembly is about 10 microns or less beneath the upper surface of the support surface of the ESC assembly, and the at least one clamping electrode 8 is about 100 microns or more beneath the upper surface of the support surface of the ESC assembly.

[0026] For example, in an embodiment as illustrated in FIG. 2 the at least one clamping electrode includes a bipolar clamping electrode 8 and annular clamping electrode 8a which surrounds the clamping electrode 8. A declamping electrode 18 is above clamping electrode 8 wherein the declamping electrode 18 and clamping electrode 8 overlap and have the same pattern. Preferably during declamping, the declamping electrode 18 is connected to ground or a voltage source such that any residual charge between wafer 4 and the support surface of the ESC 40 can be drained. For example as illustrated in FIG. 2, the control system 24 can control switch 41 such that the declamping electrode 18 is electrically connected to ground by conductive path 42 during a declamping step.

[0027] In an alternate embodiment, as illustrated by FIG. 3, the declamping electrode 18 can be surrounded by an annular declamping electrode 18a, wherein the annular declamping electrode 18a overlaps an annular clamping electrode 8a and the annular declamping electrode 18a and the annular clamping electrode 8a have the same pattern. Preferably during declamping, the declamping electrode 18 and the annular declamping electrode 18a are connected to ground or a voltage source such that any residual charge between wafer 4 and the support surface of the ESC 40 can be drained. For example as illustrated in FIG. 3, the control system 24 can control switch 41 and voltage source 21 such that the declamping electrode 18 and the annular declamping electrode 18a are electrically connected to the voltage source 21 by conductive path 42 during a declamping step wherein the voltage sources provides a voltage configured to drain any residual charge between the wafer 4 and the support surface of the ESC 40.

[0028] In an alternate embodiment, as illustrated in FIG. 4, the at least one electrostatic declamping electrode can be an annular declamping electrode 18a wherein the annular declamping electrode 18a is beneath the outer annular edge seal 48 of the support surface. The annular declamping electrode 18a of the at least one electrostatic declamping electrode is above the at least one electrostatic clamping electrode 8. Optionally, the at least one electrostatic declamping electrode can also include a declamping electrode 18 which is above electrostatic clamping electrode 8 as illustrated in FIGS. 2 and 3 wherein the electrostatic clamping electrode 8 and the declamping electrode 18 overlap and have the same pattern. In a further embodiment, as illustrated in FIG. 5, the annular clamping electrode 8a can be located beneath the outer annular edge seal 48 and the annular declamping electrode 18a. During processing, separate voltages can be applied to the annular clamping electrode 8a and the clamping electrode 8 such that a tight edge seal may be maintained between the outer annular edge seal 48 and the wafer 4. In an embodiment, as illustrated in FIG. 6, the ESC assembly 40 can also include an inner annular edge seal 48a wherein a first annular declamping electrode 18a can be included under the outer annular edge seal 48 and a second annular declamping electrode 18b can be included under the inner annular edge seal 48a wherein the inner annular edge seal 48a can separate regions of the support surface into zones wherein heat transfer gas (e.g. helium) is delivered to the backside of the wafer 4.

[0029] FIG. 7 illustrates a preferred embodiment of the ESC 40, wherein the clamping electrode 8 is patterned such that it is not directly below a mesa 20 of the plurality of mesas. In a further preferred embodiment, as illustrated in FIG. 8, the declamping electrode 18 can overlap with the clamping electrode 8 wherein the declamping electrode 18 and the clamping electrode 8 have the same pattern such that the declamping electrode 18 and the clamping electrode 8 are not directly below a mesa 20 of the plurality of mesas and further, the declamping electrode 18 and the clamping electrode 8 are not directly below any surface which supports the wafer 4. By arranging the pattern of the at least one clamping electrode and/or the at least one declamping electrode such that the at least one clamping electrode and/or the at least one declamping electrode are not directly below a mesa 20 of the plurality of mesas, and further not directly below any surface which supports the wafer 4, the amount of charge which becomes trapped between the wafer 4 and the support surface of the ESC is reduced.

[0030] During processing operations, such as plasma processing, process gas from a process gas source is supplied into a processing chamber (i.e. vacuum chamber) wherein the process gas is generated into plasma by supplying RF energy into the processing chamber such that the wafer may then be processed by a plasma etching or a plasma enhanced deposition process. While processing the semiconductor wafer in the vacuum chamber, a voltage is applied to the at least one electrostatic clamping electrode so as to clamp the semiconductor wafer to the support surface of the electrostatic chuck assembly while the at least one declamping electrode is kept electrically floating. After processing the wafer, the voltage to the electrostatic clamping electrode is turned off and the declamping electrode is electrically connected to a conductive path to provide a path for draining any residual charge between the semiconductor wafer and the support surface with the at least one declamping electrode thereby declamping the wafer from the support surface of the electrostatic chuck assembly. The conductive path can be connected to ground or a voltage source to thereby provide a path for draining residual charge between wafer and the support surface of the electrostatic chuck assembly. In an embodiment, the conductive path can be connected to a voltage source which has a polarity which is reverse to the voltage used to clamp the wafer on the support surface of the ESC thus facilitating the removal of residual charge between the wafer and the support surface. The wafer can then be raised from the support surface of the electrostatic chuck after the residual charge has been drained, or in an alternate embodiment, the wafer can be raised while any residual charge between the support surface and the wafer is drained.

[0031] While the invention has been described in detail with reference to specific embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made, and equivalents employed, without departing from the scope of the appended claims.